JPS60254820A - Zero-cross detecting circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for an external coupling capacitor and to facilitate IC-implementation by forming the circuit by using a differential amplifier composed of a CMOS. CONSTITUTION:A fine AC to be sampled is inputted to the gate of an FETT1. The gate of an FETT2 is grounded to form a constant current source. Then when the AC applied to the T1 drops below the ground potential VSS and the current flowing through the T1 becomes larger than the current flowing through the T2, the potential at a point (a) varies from a level L to a level H. When the current flowing through the T1 is smaller than the current flowing through the T2, on the other hand, the level at the point (a) varies from H to L. Consequently, a zero-cross point is detected. Thus, the circuit is formed to eliminate the need for an external coupling capacitor and, therefore, facilitate IC-implementation.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an input detection circuit, and particularly to an input detection circuit (MOS).
This invention relates to a zero-cross detection circuit using a differential amplifier configured with multiple resistors.

The detection circuit according to the invention can be used, for example, at 50 Hz of the commercial power supply.
and 60 Hz at the input stage of the device.

[Conventional technology]

FIGS. 2(a) and 2(b) show a conventional zero-cross detection circuit. (, ) and (b) differ in the connection of the feedback resistor R, but there is no substantial difference in operation. The coupling capacitance C is usually 0
．． It has a capacitance of 1 to 1.0 μF and is externally attached to the integrated circuit chip. This is obviously because the dimensions do not allow chip integration. A sampled on the coupling capacitance C
C voltage is input and impark! A square wave is output from . In this case, the threshold value of the inverter Is is set approximately at the center of the falling edge of the input/output characteristic switching from high level to low level, and the input AC is applied near this threshold value.

[Problem that the invention seeks to solve]

In the above configuration, the published coupling capacity is required,
Its capacitance is typically 0.1 to 1.0 μF.

Therefore, such a large capacity is an obstacle to integrated circuit implementation. Furthermore, since this circuit is basically a differential circuit, it is necessary to use a large era of about 1 to 3y P -P when transmitting the amplitude of the AC input.

[Means for solving problems]

An object of the present invention is to provide a zero-cross detection circuit that solves the above problems, and its means include a differential amplifier that applies a sampling voltage to the dirt of one transistor and biases the dirt of the other transistor to ground potential. and,
a zero cross comprising an inverter circuit that receives the output of the differential amplifier as an input, compares the sampling voltage with the threshold voltage based on a threshold voltage set to the ground potential, and switches between a high level and a low level; This is accomplished by a detection circuit.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to all the accompanying drawings.

FIG. 1(,) is a circuit diagram showing an embodiment of the zero-cross detection circuit of the present invention. FIG. 1(,) shows the entire zero-cross detection circuit using a differential amplifier constructed of CMO8. Ts, T friend is P channel, Ts.

T4 is an N-channel MO8) transistor.

A minute AC sampled is input to the gate of T+. The dart at T2 is grounded and serves as a constant current source. T
AC applied to ground potential of R vs8 and dart of T+
The potential at point a switches between high level and low level depending on the magnitude of the input.

That is, when the AC input applied to %TI becomes less than Vs8 and the current flowing through T+ becomes larger than the current flowing through T, the level changes from low level to high level at point a. Conversely, when the current flowing through T+k is smaller than the current flowing through T2, the level changes from high level to low level at point a. This allows zero-cross detection.

FIG. 1(b)H is a circuit diagram showing another embodiment of the zero-cross detection circuit of the present invention. Figure 1(b) #-i'NMO8
This figure shows a zero-cross detection circuit using a differential amplifier configured as follows. 'r't, 'r'*N-channel depletion type transistors 'r'R, 'r', are N-channel enhancement type transistors. As mentioned above, the sampled AC input is directly applied to the dart at 'I't, and the dart at τ2 is biased to v88. When the dart input at T'l is higher than v8s, the 'r's current Since the current flowing through T'' becomes larger than the current flowing through T'', the level at point b rises and exceeds the threshold voltage of the next stage inverter circuit, V. A low level is output to UT. Conversely, T' When the dart force of No. 1 becomes lower than Vss, the level at point b drops and VKFi high level is output.This makes it possible to detect zero cross at 0υ.

In both circuits (a) and (b), by setting the gain of the differential amplifier sufficiently large, AC input can be detected even at minute amplitudes, and AC input can be directly connected to the device without the need for coupling capacitance. Input can be applied.

〔Effect of the invention〕

As explained above, the zero-cross detection circuit according to the present invention does not require the published coupling capacitance, and therefore it is possible to reduce the number of parts and is suitable for integration into an integrated circuit.

[Brief explanation of the drawing]

FIG. 1(,) is a circuit diagram showing a zero-cross detection circuit as one embodiment of the present invention, FIG. 1(b) is a circuit diagram showing a zero-cross detection circuit as another embodiment of the present invention, and FIG. Figures (a) and (b) are circuit diagrams showing conventional zero-cross detection circuits. (Explanation of symbols) TR, Tx...P channel MO8) transistor, Ta
, Ta...N channel MO8) transistor, T', .
T', . . . N-channel depletion type MOS transistor %T'8. T',...N-channel enhancement type MO3) transistor. Patent applicant Fujitsu Ltd. Patent attorney Akira Aoki Patent attorney Kazuyuki Nishidate 1) Yukio Patent attorney Akiyuki Yamaguchi Figure 1 (C1) Figure 1 (b) Figure 2 (CL )

Claims (1)

[Claims] 1. A differential amplifier that applies a sampling voltage to the dirt of one transistor and biases the dirt of the other transistor to ground potential, and a threshold that uses the output of the differential amplifier as input and is set to the ground potential. A zero-cross detection circuit comprising an inverter circuit that compares the sampling voltage and the threshold voltage based on voltage and switches between a high level and a low level.