JPS60254663A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To contrive the reduction of chip size by a method wherein an oxide film which determines the capacitance between a control gate and a floating gate is formed on a semiconductor substrate. CONSTITUTION:A source region 10, a drain region 7 and an n type impurity region 9 as the control gate CG are formed on the p type semiconductor substrate 1. A floating gate 4 is C-shaped and is formed on the channel region between the regions 10 and 7 via a gate oxide film 12, and the other part of the gate 4 is formed on the regions 7 and 9 via ultrathin oxide films 5 and 6. An oxide film 16, an aluminum wiring 17, and a protection film 18 are formed on the gate 4. Then, capacitors C1 and C2 are formed between the gate 4 and the region 7 and between the gate 4 and the region 9, and information is written and erased by injecting and releasing electrons through the film 6 to the gate 4 by impressing electric fields on the region 9 and the gate CG.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device, and particularly to an electrically erasable programmable memory (EEPROM) and a method for manufacturing the same.

[Technical background of the invention and its problems]

Many proposals have been made regarding the cell structure of an EEPROM, among which one is known in which writing and erasing is performed on a floating gate using a tunnel current from an extremely thin oxide film on a semiconductor substrate.

IE is a specific example of a conventional EEPROM cell structure.
E E jourrai of 5 solid-slat
e circuits.

What is described in Volsc-18, No. 5, p532 is shown in FIG. A source region 5 and a drain region are formed on the surface of the P-type semiconductor substrate Sub, and a first polysilicon layer Po1 as a floating gate is formed.
yi, a second polysilicon layer Po1y2 as a control gate is formed. floating goo tl
oly1 is formed on the chitnel region between the source region S and the train region via a gate oxide film Qxidei, and on the drain region via an extremely thin oxide film Oxide2. ]] The human gate Po1V is formed on the gate PO1yI via an oxide film Oxide3.

Writing and erasing information to the floating gate Po1V1 is performed using the drain region and the control gate Po1y2.
This is done by applying an electric field between the 70-Teinggut Po1y1 and the drain region to inject or emit electrons through the extreme N oxide model QXide2 using the tunneling effect between the 70-Teinggut Po1y1 and the drain region. This changes the threshold value vth of this floating gate transistor and stores information.

The tunnel current density J due to the tunnel effect strongly depends on the electric field E and is given by the following equation.

However, A and Eo are constants. Therefore, in order to shorten the writing time (and widen the difference in the threshold value vth between 11 and 0''), the control gate P
It is necessary to efficiently transmit the voltage applied to o1y2 to the floating gate Po1yl.

For that purpose, control gates Po1y2 and 7
0 and the capacitance C2 between the tying gate po+y1 and 〕〕O
It was necessary to increase the ratio C2/C1 of the capacitance C between the gate Po1y and the drain region to three times or more.

In order to increase the capacitance C2, oxidation % Q xide
-3 can be made thinner, but in general, it is difficult to control and cover the unevenness of the polysilicon layer and the grain growth of the oxide film, so the oxide film on the polysilicon layer is formed thinner than the oxide film on the semiconductor substrate. It was difficult. Therefore, in order to increase the capacitance C2, the floating gate Po1
The overlapping area between y1 and control gate POIV2 has to be increased, resulting in an increase in the cell occupation area. On the other hand, the ultra-thin oxide film Oxide2 must be thin in order to obtain a large tunnel current. For example, if the ultra-thin oxide film Qxide2 is 100 and the Ilt film Oxide3 is 800, the area where the floating gate Po1y1 and the control gate Po1y2 overlap needs to be 2418, which is the area of the ultra-thin oxide film Oxide2.

Also, ultra-thin oxide IN! which determines the capacitance C1! Oxide2
Since the oxide film 0Xide3, which determines the capacitance C2, is manufactured in a different process, if the conditions of each process are different, the capacitance C1,
There was a problem in that C2 did not reach the expected value, and the ratio C/C1 varied greatly from lot to lot or from wafer to wafer. For this reason, it is necessary to design a pattern taking into consideration such variations in the manufacturing process, which also causes an increase in the area occupied by the cell.

Furthermore, it is difficult to control the shape of the edge of the floating gate Po1y1, and for example, the edge e may become sharp as shown in FIG. Then, an electric field concentrates on this edge e, and the charge accumulated in the floating gate Po1yl gradually leaks, leading to a risk of memory loss.

[Purpose of the invention]

The present invention has been made in consideration of the above circumstances, and it is an object of the present invention to provide a semiconductor storage device with a small cell occupation area and less variation due to manufacturing conditions, and a method of manufacturing the same.

[Summary of the invention]

In order to achieve the above object, a semiconductor memory device according to the present invention includes a drain region and a source region formed on a surface of a semiconductor substrate, and an impurity of a conductivity type opposite to that of the semiconductor substrate formed on the surface of the semiconductor substrate and functioning as a control gate. a floating gate formed on the impurity region and the train region through an extremely thin insulating film, and formed on a channel region between the drain region and the source region through an insulating film. It has a transistor.

Further, the method for manufacturing a semiconductor memory device according to the present invention includes a first step of forming an impurity region and a drain region in first and second regions on a surface of a semiconductor substrate, and a step of forming an insulating film on the semiconductor substrate. a third step of etching the insulating film on the first region and the second region, and simultaneously forming first and second ultra-thin insulating films thereon, respectively; a fourth step of forming a 70-gate transistor on a third region above and in contact with the train region and on the first and second ultra-thin oxide films; and a fifth step of forming a source region in the fourth region of the surface of the semiconductor substrate.

[Embodiments of the invention]

A semiconductor memory device according to an embodiment of the present invention is shown in FIGS. 1 to 4. The memory cell of this semiconductor device has a structure in which a floating gate transistor 1-4 and a helical transistor T8 are directly connected, as shown in the equivalent circuit of FIG.

The layout pattern of the 70-gate transistor 1F is shown in the upper part of FIG. 1, and the cross-sectional structure is shown in FIG. A source region 10 and a drain region 7 are formed close to each other on a P-type semiconductor substrate 1, and an n-type impurity region 9 as a control gate CG is further formed. The floating gate 4 has a U-shape and is formed on the channel region between the source region 10 and the drain region 7 with a gate oxide film 12 in between, and the other part of the floating gate 4 is formed with an extremely thin oxide film. They are formed on drain region 7 and impurity region 9, respectively, with a 5.degree. Here, it is desirable that the thickness of the ultra-thin oxide film 5 be the same as or greater than the thickness of the ultra-thin oxide film 6. As a result, a capacitor C1 is formed between the 70-ring gate 4 and the drain region 7, and a capacitor C2 is formed between the 70-ring gate 4 and the impurity region 9. Furthermore, an oxide film 16 is formed on the 70-ring gate 4. The source region 10 is connected to the source terminal S by an aluminum wiring 17 via a contact 15 . Aluminum wiring 170 is safe! 18 is formed.

The layout pattern of the select transistor 1-8 is shown on the right side of FIG. 1, and the cross-sectional structure is shown in FIG. N-type source region 7 and drain region 1 on P-type semiconductor substrate 1
1 are formed close to each other.

This source region 7 is an impurity region that is continuous with the drain region 7 of the floating gate transistor T.

A select gate 8 is formed on the channel region between the source region 7 and the train region 11 with a goo 1-oxide film 13 interposed therebetween. Further, an oxide film 16, an aluminum wiring 19, and a protective film 18 are formed in the same manner as in the case of the transistor T 70.This aluminum wiring 19 is connected to the drain region 11 through a contact 14.

To infiltrate and erase the information in this memory cell, an electric field is applied to the drain region 7 and the control group (CG), and the polar N oxidation is carried out. This is done by injecting or emitting electrons into the floating gate 4 through I6. The threshold value Vth of the floating gate transistor T depends on whether or not charges are accumulated in the 70-ting gates 1-4.
changes, and information is memorized.

In this memory cell, the oxide films 6 and 5 that determine the sizes of capacitances c and c2 are both extremely thin oxide films, so the capacitance ratio C/
In order to make C1 3 or more, the overlapping area S2 of the floating gate 4 and the impurity region 9, etc., which are in contact with each other through the ultra-thin oxide film 5, is reduced by the area S2 where the floating gate 4 and the drain region 7, which are in contact with each other through the ultra-thin oxide film 5, overlap. The overlapping area S1 may be made three times or more. In this embodiment, since the oxide film 5 that determines the capacitance C2 is formed on the semiconductor substrate 1, it can be formed extremely thin, and the area occupied by the capacitance C2 can be reduced. .

Difference in threshold voltage Δ■t when information is “0” and “1”
The relationship between h and writing time t is as follows. Generally, the tunnel current density J is given as follows, where E is the applied voltage.

J, = AL2exp (-----'- Therefore, the electric field between the floating gate 4 and the drain region 7 is E, the overlapping area is 8170-1, the electric field between the floating gate 4 and the impurity region 9 is E2, and the overlapping area is 82). The temporal change in the electric field Q accumulated in the gate 4 is as follows, and the difference in threshold voltage Δvth is 6 A=9.9×10 A/V2, E=2.8×108 V/α. Based on the above relationship, when the thickness of the ultra-thin oxide film 5゜6 is 100, and the write voltage is 20V, what is the relationship between the threshold voltage difference ΔVth and the write time?
FIG. 5 shows 1 as a parameter. Here, the broken line indicates the case where the oxide film between the control gates is thick as in the conventional case and there is no need to consider the tunnel effect. As shown in Figure 5, the writing time t
If it is less than 1 m5ec, there is almost no difference between the solid line and the broken line, and the tunnel effect can be ignored, and there is no problem even if an extremely thin oxide film is used. In particular, the characteristics of this embodiment are sufficiently satisfactory, taking into account that in recent years there has been a demand for shortening the write time t.

Next, a method for manufacturing this semiconductor memory device will be explained with reference to FIG. Here, FIG. 6 is the same cross section as the cross section of FIG. 2.

First, an oxide film 20 is formed on the P-type semiconductor substrate 1, and then impurities are diffused into the region covered by the floating gate where the drain region vL7 and the impurity region 9 will be formed (FIG. 6(a)). .

Next, the oxide film 20 on this diffused region is etched to form the extreme S oxide films 5 and 6 (FIG. 6(b)). Next, a polysilicon floating gate 4 is placed on these ultra-thin oxide films 5 and 6 and on the region that will become the channel region.
(Fig. 6(C)).

Next, resist 21, source area tii! 10. The drain region 7 and the impurity region 9 are formed to define patterns, and the impurities are diffused (FIG. 6(d)). Next, an oxide film 16 is deposited and contacts 15 are formed as shown in FIG. 6(e).
), the aluminum wiring 17 and the protective film 18 are roughly formed, and the manufacturing of the floating transistor T is completed (
Figure 6(f)). This manufacturing method is characterized in that the ultra-thin oxide films 5 and 6 are made in the same process, so that the characteristics of these ultra-thin oxide films 5 and 6 are the same. Therefore, the capacitance ratio C2/C1 can be reliably determined only by the area ratio.

Modified examples of the memory cell layout pattern are shown in FIGS. 7, 8, and 9. The layout pattern in Figure 7 is
The 70-ting gate 4 is shaped like a figure 8, and the tip of the figure 5 crosses the train region 7. This allows the width of the entire memory cell to be reduced.

In the layout pattern of FIG. 8, the floating gate 4 is F-shaped. This allows the vertical length of the entire memory cell to be shortened. The layout pattern of FIG. 9 is the same as that of FIG. 1 in that the 70-ting gate 4 is U-shaped, but the capacitance C1 is not the area of the ultra-thin oxide film 6 but the tip of the 70-ting gate 4. Since it is determined by the area where the projection part and the projection part provided in the drain region 7 overlap, there is an advantage that the dimensional accuracy of the polar*m film 6 is not strict.

Further, instead of the oxide film, an insulating film such as a nitride film on a silicon substrate or an oxide film in a nitrogen atmosphere may be used.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a semiconductor memory device with a small cell occupation area and less variation due to manufacturing conditions, and a method of manufacturing the same.

Regarding the cell occupation area, for example, while the conventional 2μm rule required approximately 280μd, the present invention requires approximately 14μd.
It will be reduced in half to 0μ. Therefore, the bit density can be approximately doubled. On the other hand, the capacitance 1tC2/C1 can be increased without extremely increasing the cell area, and the write voltage can be decreased.

If the write voltage is reduced, reliability is improved and the portion formed in consideration of the application of high voltage can be made smaller, making it possible to reduce the overall chip size. Moreover, if the ultra-thin oxide films 5 and 6 are manufactured at the same time, their characteristics can be made the same, so that variations due to manufacturing conditions can be extremely reduced.

[Brief explanation of drawings]

FIG. 1 is a plan view of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a sectional view taken along line AA of the same semiconductor memory device, FIG. 5 is a graph showing the characteristics of the semiconductor memory device. FIG. 6 is a process diagram showing the method for manufacturing the semiconductor memory device according to the present invention. 7, 8, and 9 are plan views showing modified examples of the semiconductor manufacturing apparatus according to the present invention, and FIG. 10 is a partial sectional view of a conventional semiconductor memory device. 1... Semiconductor substrate, 4... 70-Teinggut,
5.6... Ultra-thin oxide film, 7... Drain region, region (source region), 8... Select gate, 9... Impurity region, 10... Source region, 11... Drain Region, 12° 13... Gate oxide film, 14.15... Contact, 16... Oxide film, 1.7.19... Aluminum wiring, 18... Protective film, D... Drain , S... Source, TS... Select transistor, T... Floating gate transistor, SG... Select gate, CG... Control gate. Applicant's Representative Inomata Kiyoshi District 1 Figure 5 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] 1. A drain region and a source region formed on the surface of a semiconductor substrate; an impurity region formed on the surface of the semiconductor substrate and having a conductivity type opposite to that of the semiconductor substrate and functioning as a control gate; A 70-ting gate transistor having the drain region and a 70-ting gate formed through an extremely thin insulating film, respectively, and a 70-ting gate formed on a channel region between the drain region and the source region with an insulating film in between. semiconductor storage device. 2. A select transistor having a drain region and a source region formed on the surface of the semiconductor substrate, and a select gate provided on a channel region between the train region and the source region; a drain region connected to the source region of the transistor, a source region formed on the surface of the semiconductor substrate, an impurity region formed on the surface of the semiconductor substrate and functioning as a control gate, and the impurity region and the drain region, respectively. 1. A semiconductor memory device comprising: a floating gate transistor formed through an extremely thin insulating film, and a floating gate formed over a channel region between the train region and the source region through an insulating film. 3. A first step of forming an impurity region and a drain region in first and second regions on the surface of the semiconductor substrate; a second step of forming an insulating film on the semiconductor substrate; a third step of etching the insulating film on the second region and simultaneously forming first and second ultra-thin insulating films thereon; forming a source region in a fourth region of the semiconductor substrate surface adjacent to the third region; a fifth step of forming a semiconductor memory device.