JPS60254250A - Control sequencer for microdiagnosis having dual microprogram counter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an information processing system having a self-test function. More specifically, built-in tests (BIT) are used to detect faults and to help isolate faults to the hardware module level.
5t) Digital micro-diagnostic test routines that combine hardware and micro-operability tests to test the hardware parts of a computer system.
Concerning computer systems.

BACKGROUND OF THE INVENTION Any information handling system, especially digital computer systems, requires some level of testing or diagnostics to ensure operability. Typical software testing targets only a small portion of a computer system during a given period of time. The hardware support test facility, also referred to as BIT, performs additional system testing. However, it is not a complete diagnostic method as it is very expensive.

BIT has been achieved through three activities such as initial diagnosis, online BIT and offline technology. The initial diagnostic program may include microdiagnostics and operability tests that are performed when the computer system is first turned on or while engaging in the initial program rotor 9.

Online BIT includes all areas of fault monitoring activities that occur while the computer is operating, such as self-testing hardware fault monitors that continuously monitor critical points within the computer. Off-line BIT becomes necessary when initial attempts at isolating computer failures fail requiring more thorough testing procedures. Logic scan design (LSD: L
Off-line techniques such as Logic ScanDesign and Science Analysis can be performed. Logic scan design is a method of serially linking internal nodes that provides improved testability, especially for large scale integration (LSI) logic designs. This method takes account of all internal logic states to be held in serially accessible registers, thereby observing and controlling these internal states. After repairs have been made, cidernature analysis involves the accumulation of thousands of internal test point sequences into one cidernature word 9 which is serially read and validated by an external diagnostic exerciser. This external diagnostic exerciser attempts to isolate faulty modules in the computer system by performing diagnostic routines while maintaining precise control over the internal states of the computer under test. Online BIT involves the use of microdiagnostic test routines stored in the microprogram control unit not only at power turn-on, but also during normal computer operation, which would otherwise be possible without this method. Provides a means for detecting failures much earlier than otherwise possible. However, previous attempts to employ microdiagnostics in microprogrammed control units have been based on forcing the computer or data processing system into an idle state of the system, thereby terminating normal processing operations. Therefore, a significant amount of additional supporting hardware was required.

SUMMARY OF THE INVENTION The present invention provides the ability to create a
An information processing system having a microprogram control unit that executes a microdiagnosis microprogram is disclosed. A memory is adapted to store a plurality of microinstructions for executing both background and foreground microprograms.

The microprogram control unit has two microprogram counters, namely a first microprogram counter;
A counter participates in the execution of the foreground program, and a second microprogram counter controls the foreground program operation by using two microprogram counters that control the background microdiagnostic microprogram without affecting the foreground program operation. contains a control sequencer for independently controlling the ration and background microprograms. The control sequencer further includes a speculative/remainder encoding method for detecting microinstruction addresses and data errors.

Further, this background microdiagnostic microprogram includes a plurality of test modules stored in memory, each of which tests a particular portion of the information handling system, each of these test modules contains short cycle code for proof of execution of each test module.

The present invention further discloses a method for executing a background microprogram during operation of a foreground program in an information handling system having a microprogram control unit. That is, the method includes the steps of: storing a plurality of microinstructions for executing a background microprogram and a foreground microprogram; and at least two microprogram counters, a first microprogram counter;
independently controlling the foreground program operation and the background microprogram with two microprogram counters, a counter participating in the execution of the foreground program and a second microprogram counter controlling the background microprogram. There is.

The present invention further provides that the foreground program is
BACKGROUND A method for performing fault detection in an information handling system having a microprogram control unit that executes a microprogram is disclosed. That is, the method includes the steps of storing a plurality of microinstructions for executing a background microprogram and a foreground microprogram, each of these microinstructions having an address of each of said microinstructions and the contents of said address. a step of storing a first code for proof; a step of controlling a foreground program and a background microprogram with at least two microprogram counters; representing a code for a current microinstruction address from said first code; The steps that generate the remaining code,
generating and storing a second code for the next microinstruction address during the most recently executed fourth microinstruction ration; and comparing the remaining code with the stored second code to detect a failure. including steps to

(Explanation of Examples) Significant improvement in the built-in information processing test (BIT) function
As shown in FIG. 1, this has been achieved in accordance with the present invention.

The present invention utilizes two independent microprogram counters to perform on-line BIT microdiagnostic tests without interrupting a normally operating information processing system. The second micro-diagnostic microprogram counter 26 is used during the idle time of the micro-instructions executing the foreground programs. Control the execution of background microdiagnostic tests that are running concurrently.

Microprograms are implemented using standard machine microinstructions to perform tasks directed to specific applications. One 74 chrome program is stored in memory unit 6.
6. Controlled by microprogram counter 81 according to microinstructions stored in 6. The output from the 74-crore instruction obtained from memory unit 66 is ration two 1'i! , which is coupled to a mapping PROM 74 and a mapping FROM 741d, which determines the starting microinstruction address in control storage 70 for a microprogram implementing the microinstruction specified by ration code 9. do. The microprogram read from control storage 70 is supplied to control sequencer 76 . The control sequencer 76 is
The above two microprogram counters 24 and 2
Contains 6. Thus, microprogram counter 24 generates the address of the next microinstruction for the microinstruction being executed by the foreground program of information handling system 60 shown in FIG.

FIG. 1 will be explained. The micro-diagnostic micro-program counter 26 is used during the performance of background micro-diagnostics that are performed simultaneously with foreground micro-programs during operational potential micro-diagnostic tests that are performed during idle machine time or power turn-on of the processing system 60. generates the address of the next microdiagnostic microinstruction. Operation possibility microdiagnosis is performed when the foreground program is not activated and the microprogram counter 2
4 in a sequential manner under the control of Multiplexer 28 selects the microprogram counter according to address select 148 signals generated by control switch 161 logic based on specific control bits of the microinstruction coupled to control switch 161 from control register 71 coupled to control store 70. (MPC) 24 or microdiagnosis microprogram counter 26.

The output of multiplexer 28 is connected to output address multiplexer 32. Control switch 161 also provides a microprogram counter (MPC) source selection 152 that is coupled to microprogram counter 24.
generates a background branch select 160 signal which is coupled to the microdiagnostic microprogram counter 26, thereby causing the microprogram counters 24 and 26 to be activated when the address of the next microinstruction is being selected.
Switch.

The output of microprogram counter 24 is also coupled to microprogram stack 3o. Microprogram stack 3o includes a stack and associated stack pointers for handling microprogram interrupt subroutines. The microprogram stack is an 18-bit wide, 6-level, last-in/first-out (LIFO) register that is used during stack PUSH and POP operations. This stack pointer is set to 6 states UP/UP by parity prediction logic.
The stack operation described above is controlled by the execution of the DOWN counter. Parity prediction logic, typically used in conjunction with counters, predicts the next state of parity after a clocked counter output. The loop stack described above stores the current microprogram counter position and corresponding code in the LIFO as determined by the stack pointer logic described above. The PUSH operation stores the microprogram counter, and the POP operation moves the selected LIFO location to the stack output. The implementation and operation of microprogram stacks are known to those skilled in the art.

Microprogram stack 30018 bit outputs are connected to output address multiplexer 32 and microprogram counter 24.

Output -y)'' The other input to the multiplexer 32 is an 18-bit word that is directly concatenated from the multiplexer 28 and outputs the current microprogram by transferring control to a predetermined address in the control store 70. At9res jam 48 signal, source select 55 signal from control store 700 microinstruction read through control register 71 and 13-bit a1-''res and branch status multiplexer 22
contains an 18-bit word 9 containing a 5-bit code from The address jam 48 signal immediately suspends the current microdiagnostic microprogram being executed, places the contents of the foreground microprogram counter on stack 30, and forces the control store 70 address into a predetermined state. If a background microdiagnosis is being performed, this background microdiagnosis is terminated, the background microprogram counter 26 is initialized to (0001) 16, the mode is switched to foreground, and the contents of the foreground microprogram counter 24 are is placed at the top of the microprogram stack 30. Output address φ multiplexer 32 selects microinstruction address 50 for entry point into control store 70 from its various address inputs. A map enable 52 signal is also generated by output address multiplexer 32. Microinstruction address mapping FROM7
4, the above address determines the microprogram entry address in control store 70. A microinstruction word from control store 70 provides two control signals to the inputs of control switch 161, toggle 163 and INHIBIT 164, as shown in FIG. 5 and described below.

FIG. 1 will be explained again. Controller 20 receives inputs from internal data path 40, branch state multiplexer 22, and function select 19 signals from control register 71. Controller 20 implements several logical functions for control sequencer 76, such as decoding function selection 19 Kobi and combining internal fault conditions into a single fault indication called fault 54. The output of the control device 20 is
Branch state multiplexer 22 and microprogram
It is connected to the stack 30 and performs the decoded functions by defining the operations to be performed. This branch state multiplexer 22 includes a control device 20,
Control register 71, branch status 42 and code checker 56
receives signals from the microprogram counter 24 and microdiagnostic microprogram counter 26.
and generates a branch address which is coupled to an output address multiplexer 32. Therefore, the source of the microinstruction aviles 50 is the mapping FROM 74 as well as the branch state, the microprogram φ counter 24
and 26, the microprogram stack 30 or the address jam 48.

Depending on which executive mode is being implemented, background or foreground, only one of the two microprogram counters 24 and 26 is available to the output address multiplexer 32 at a time. In all cases, the available microprogram counter will be incremented by 1 at the end of the microcycle, unless the executing microcycle is in a process in switched execution mode. loaded. In this state, output address multiplexer 3
2c. The microprogram counter that is about to take control is forced to supply the microinstruction address to the control storage device 70. Meanwhile, the currently available but outgoing microprogram counter is loaded with the address that this counter was intended to provide to the output address multiplexer 32. This is the address to which this microprogram will return when execution control returns to the outgoing microprogram counter. Control sequencer 76 is commanded to switch microprogram counters 24 and 26 from the microprogram itself as a result of preprogramming.

The address of the next microinstruction to be executed is sourced from the controlling microprogram counter, and the address defined by one microinstruction source selection field is sent to the outgoing microprogram counter. It will be done.

FIG. 2 will be explained. FIG. 2 shows a block diagram of an information processing system 600. This information processing system 60 includes a control unit 62, an arithmetic unit 64, a memory unit 66, and an input/output unit 90. The control unit 62 and the calculation unit 64 together form a central processing unit, which includes:
system address bus 85 and system data bus 85;
memory via system bus 89, including bus 87.
It interfaces to unit 66 and input/output unit 90.

Control unit 62 includes a control sequencer 76 as shown in FIG. The control sequencer 76 provides microinstruction addresses 50 to a memory or control store 70 as determined by examination of microinstruction data, processor bus data, or some predetermined state within the central processing unit. .

Once during each control sequencer system clock cycle of 106, the next address determination is made. Each microinstruction of a microprogram defines the source of the aviles for the next stage of the microprogram. The output of control store 70 includes a control register 71 having 136 bits making up one microinstruction word. 8KX24 bit mapping FROM that is one of several sources for microinstruction address 50
74 converts the instruction stream from the control register 71 or the operand code and operand definition factor in the internal data bus 4° into a microinstruction address. Information processing system 6
Each module of 0 has built-in test) (BIT) data.
・Built-in test/maintenance control equipment to collect condition information (
BMC) 72 is installed. Each BMG72 has a system level bit maintenance device with a system BIT7
3 Reports state information. This system bit maintenance denominator may be present in the input/output unit 90, although not shown. The system rail device determines which module caused the failure based on analysis of all failure reports and issues a failure indication.

FIG. 2 will be explained again. The arithmetic unit 64 includes a register arithmetic and logic unit (RALU) 80, which includes a register array including a microprogram counter 81, a multifunction ALU (as shown in FIG. Contains extended logic and various data paths. The functions performed by RALU 80 are primarily determined by microprogram control unit 62. RALU80 is a system bus
Interface 88 K-coupled to internal data bus 40. The RALU is also coupled to a multiplier 78 that is used for extended precision information and floating point rations. Implementations of both RALU 80 and multiplier 78 are known to those skilled in the art.

RALU is also an Associative Registration Arithmetic Logic Unit) (ARA
(LU) 82, which associative registration logic unit 82 functions as a memory management unit by associating a virtual address with a virtual address boundary and then adding an appropriate relocation amount to the virtual address. . A
RALU 82 may be implemented with two separate ARALUs, where one ARALU stores virtual address boundaries and the relocation amount is stored in a register of the second ARALU. The first ARALU subtracts the incoming virtual address from each of the 16 virtual address boundaries. While this subtraction is occurring, the second ARALU adds the incoming virtual address to each of the 16 relocation quantities. When the first ARALU identifies a first virtual address boundary, i.e. is greater than or equal to the incoming virtual address, the entry point is sent to the second ARALU and the second
ARALU then outputs the appropriate address onto system address bus 85.

Memory unit 66 includes two 16K x 48 bit memory units.
It includes random access memories 100 and 102, but can be easily expanded. A memory address controller 96 is connected between system address bus 85 and memories 100 and 102. This control device performs all the functions necessary to control Memo IJ 100 and 102. 1st Ritz Puller/Bite Adjuster (
RIBA) 94 is connected between system data bus 87 and memory 100, and a second ripple/byte adjuster (RIBA) 98 is connected between system data bus 87 and memory 100.
7 and memory 102. This RIBA
94 and 98 are data adjustment, byte and no-f.
It is a multifunctional element that performs word transfer, error detection and correction, ripple error correction, and bus interfacing. Ripple error correction is performed by replacing any defective memory device in a linear array of equivalent devices with its nearest neighbor and then replacing this device with its nearest neighbor. These entire processes continue until the last active device is replaced by the first available swap.
"Ripple" down the array of subelements. The advantage of this switching method over conventional direct replacement methods is its amenability to control algorithms that are relatively simple and reliably implemented. More details about the Rippler are disclosed in US Pat. No. 3,805,039.

The input/output unit 90 has an I10 control device 91 and an I1
0 interface 92. I10 controller 91 generates appropriate interrupts to implement I10 instructions and control the various I10 ports.

I10 interface 92 includes standard peripherals, specific interfaces such as parallel or serial interfaces. The input/output unit 90 also includes a priority interrupt network 84 for handling interrupts, a processor control register 86 for holding information related to the current state of the information handling system, and system bus control, system bus arbitration instructions. It includes a system bus interface 88 for prefetch control and storage clock distribution control.

FIG. 3 will be explained. In this figure, an example of the logic for the background microprogram counter 24 and the background microdiagnostic microprogram counter 26 is shown. The microprogram counter 24 is 13
It includes a 4/1 multiplexer 120 connected to a bit register 124, which stores the microinstruction address. A 4/1 multiplexer 122 is also connected to a 5-bit register 126. This register 126 is for storing microprogram counter code for detecting addressing errors. This 5-bit microprogram counter code is generated by code generator 142 as a function of a 13-bit microinstruction address. The code thus generated is matched with an equivalent code extracted from the microcode bits entering the control sequencer 76 from the control register 71 in order to check the control store 70 against the control sequencer 76 address path. As shown in Figures 1 and 4, the coat 9
A comparison is made in the tester 56. Micro program/
The counter 24 also receives the address from the stack address line 154 and the associated stack code) 1
58 is applied to the microprogram countercoat 9 register 126.

Background Microdiagnostics Microprogram counter 26 includes a 2/1 multiplexer 13 connected to a 13-bit register 136 for storing microinstruction addresses.
2 and 5 bit microzologram counter code 1
• includes a 2/1 multiplexer 134 connected to a 5-bit register 138 for storing . Microinstruction address 50 is passed through address incrementer 1 before being stored in register 124 or register 136.
Increment by 40. Code generator 142 generates microprogram counter code associated with the microinstruction address and described below in FIG.

Foreground microprogram counter 24 receives addresses via the multiway branch address 150 line, stack 154 line, or microinstruction address 50 line when gated by the MPC source select 152 signal. The background microdiagnostic microprogram counter 26 receives addresses via the microinstruction address 50 line or the multiway branch address 150 line when gated by the background branch select 160 signal. When a microdiagnostic abort condition occurs, the DIA
The GABORT44 signal is set to address as shown in Figure 5.
This is caused by a jam 48, which transfers control to the foreground microprogram counter 24. Address selection 148 signal is program φ counter address 1
44 and its associated program counter code 143
selects whether it comes from the foreground microprogram counter 24 or the back microdiagnostic microprogram Φ counter 26. The integrated circuits required to perform the logic functions shown in FIG. 3 are well known to those skilled in the art.

FIG. 4, FIG. 9, and FIG. 10 will be explained.

These figures illustrate a fault detection circuit for detecting data errors in the microinstruction address and control sequencer 76 by a predict/remainder method.

Exclusively ORing the data bits within a particular microinstruction address, the next address 103 field, the control field 104, and the microinstruction address itself, as shown in FIGS. 9 and 10. generates a cyclic parity code, and the resulting cyclic parity code is placed in the coat 105 field of the microinstruction.

Logic within the code checker 56 removes the contribution of the next address 103 and control field "104 to this code. The encoder 107 connected to the exclusive OR 109 removes the next address 103 field 8 contribution The encoder 108 connected to the control field 104 removes the control field 104 contribution and thereby represents the remainder code, which is a test for the current microinstruction address, at the output of the exclusive OR 1,1,0.The prediction for the current microinstruction address The code entered was previously stored in the code register 113. Therefore, the exclusive 0RIII basically performs a comparison of the expected code at its input with the remaining code and is connected to the zero detector 112. Exclusive○ If the output of R111 is non-zero, FAIL
54 signals are generated. The previous microinstruction rotot9 code register 113 expected code 9 for the next address, which by definition must be equal to the remainder code generated at the output of exclusive 0R110. The appropriate loading of code register 113 is controlled by the control sequencer clock 106 signal.

Branch state multiplexer 22 indicates that the next microinstruction address 50 is
It receives the 13-bit next address 103 from control register 71 and the associated 5-bit code from encoder 107 to handle branch conditions correctly. As previously explained, output address multiplexer 32 selects the source for the next microinstruction 50 and the associated expected code is sent to code register 113.

The expected/remaining code failure detection method allows control register 7
1, that the data from the control storage unit 70 was correctly read out via the control storage unit 70, that no failure occurred in any address line of the control storage unit 70, and that there was no data error in the control storage output. , and that no data path errors occurred between control store 70 and control sequencer 76.

FIG. 5 will be explained. A microdiagnostic control switch 161 is illustrated in this figure. Control storage device 70
Two microinstruction signals called switch 163 and INHIBITl, 64 from the control switch 161
control the operation of Both signals must be asserted to affect the switching function. One of the signals INHIBIT 164 is used to control the switching between background and foreground. This D-flip clock 168 generates the microdiagnostic enable 171 signal and initiates the microprogram transparent counter selection activity as follows. AND gate 165 indicates that INHIBIT is logic 0
If so, the D clip flop 168 is toggled. NOR gate 166 gates to D-clip flop 168 via control sequencer Φ clock 106 YAND gate 167. If the address jam 48 signal is activated when background mote 9 is enabled (when flip-flop 168 is set),
The DIAGA BORT 44 signal goes active (logic 1), which resets the clip-flop 168, i.e., the end of the background microprogram (the background microprogram counter 26 is started) before the address jam sequence is performed. ) and transfer to the foreground mode of the control sequencer. Further flexibility is provided by allowing micro-diagnostic enable 171 to be used as a branch state identification of whether a background micro-diagnostic or enablement micro-diagnostic test is in progress.

FIG. 5 will be explained again. This control switch 161
During background microdiagnosis, At9ResJam4
If an 8 occurs, the foreground o is automatically transferred to the ration. This condition generates the DIAflABORT44 signal, which signal is used to initialize the background microprogram counter to (000i) 1.6 and restart the background microdiagnostic routine. AND
NO gate 166, microdiagnostic enable 171 and address jam 48 are connected to branch state multiplexer 22.
TRUE 21 and source select 55 from control register 71 are inputs to decoder 169, which develops four outputs to control microprogram counters 24 and 26 and multiplexer 28.

Background branch select 160 controls the loading of the background microdiagnostic microprogram counter 26, MPC source select 152 controls the loading of the foreground microprogram counter, and the Aviles select 148 signal is routed through multiplexer 28 to the foreground microprogram counter. Select either a counter or a background microdiagnostic microprogram counter and associated microprogram counter code.

The microdiagnostic tests used in conjunction with the BIT HART9 hardware, microcobi routines and macro operability tests, provide fault detection and assist in fault isolation to module hardware. The Maheklo operability test is a microdiagnostic test used to confirm the basic operability of an information handling system. Microdiagnosis is divided into operability microdiagnosis and background microdiagnosis. This readiness micro-diagnosis supports the macro readiness test, and this readiness micro-diagnosis tests the hardware circuitry that prevents execution of the 17th readiness instruction in case of a failure. is performed during initial power-up of the system by Operability Micro-Diagnostics and Background Micro-diagnostics is used to achieve a high percentage of fault detection and to aid in fault isolation by test circuits that cannot or are insufficiently tested using BIT hardware exclusively. work together.

FIG. 6 will be explained. This figure shows a composition as a hierarchical structure of microdiagnosis.

Each box in FIG. 6 represents a microprogram test module, which may be a control or test module. The control module consists of two or more call instructions and one return instruction. The control module is
Call either the lower control module or the test module. The test module explicitly tests the functional areas of information handling system 60. Examples of control modules include nib 42 f4 f1 f8 actuation potential micro-diagnostic 180 and background micro-diagnostic 181. Background microdiagnosis 181 is generally R
OM186, control sequencer 187, floating point 18
8. Registered arithmetic logic unit 189 and register 1
It consists of 90 modules. These microdiagnostics are designed such that the active microdiagnosis 180 and the background microdiagnosis 181 share a microtest module or common microinstruction code 0 as shown in FIG. The fault 182 module is called by the microprogram when a fault is detected. The purpose of the Fault 182 module is to establish a stable system state (
That is, the purpose is to establish a "jump by itself" and alert the BIT maintenance control device 72 of the failure. Each function test/
The module has a short cycle coat defined for its function. This call r originates in one module and is passed as a parameter to the next module. The next module tests the short cycle code value passed when the program is entered, and if it is incorrect, the BIT hardware is notified of a failure.

This short cycle code is generated by incrementing the passed code by some constant. Short cycle/
The code is tested when running background micro-diagnostics 181 and operability micro-diagnostics 180.

One complete operability micro-diagnostic test sequence includes system bus interface 183, priority interrupt network 184, RAM 185, ROM
186, control sequencer 187, floating point 188, and registered arithmetic logic unit 189. A complete sequence of background microdiagnostics includes the steps of executing the following test modules: That is, ROM 186
, control sequencer 187 , floating point 188 , registered arithmetic logic unit 189 and registers 190 modules. ROM 186, control sequencer 187,
floating point 188 and registered arithmetic logic unit 18
9 test modules perform operability micro-diagnostics 18
Since it is the same test module for both 0 and background microdiagnostics 181, the amount of control storage 70 required can be minimized.

This readiness micro-diagnosis 180 is performed immediately after the initial program load and power-up of the information handling system by testing the circuitry that prevents execution of the first macro readiness command. Supports language mapping functionality testing (software testing). This readiness micro-diagnosis 180 does not preserve the previous state of the information handling system;
Assume that the hardcore (the minimum amount of circuitry required to initiate the first micro-diagnostic test) is activated. This operability microdiagnostic 180 builds on the hard core by testing additional circuits until all necessary tests are completed. That is, these micro-diagnoses are
This is carried out under the control of a foreground microzologram counter 24. After the readiness microdiagnostics are completed, an assembly language macro readiness test is performed.

Background microdiagnostics 181 are performed during periods of processor idle machine time. The control sequencer 76 of the microprogram control unit 62 includes two microprogram counters 24 and 26, as previously described, which operate simultaneously during execution of an assembly language program. Because the background microdiagnostic tests are performed using the background microprogram counter 26 during individual machine time, these tests are transparent (in time) to any user program. Background microdiagnostics executes three microinstructions at a time, as shown in FIG. 8, for a more complete test. FIG. 8 shows a control memory 7 containing a foreground microprogram for implementing microinstruction A and microdiagnostic test modules B and C.
It shows 0. During the execution of the microinstruction An at the time Tn, two control signals from the microinstruction An mentioned above switch program control to the background microprogram counter 26, which in the case of this description microdiagnostic test module B executes only three instructions at a time. Upon completion of the third microinstruction (B3), program control switches back to the foreground microprogram counter 24 and microinstruction A
The implementation of n is completed. Background microdiagnostics 181, by the nature of their implementation, do not change the state of computer system or information handling system 60. The intent of the background microdiagnosis 181 is to continuously practice functions not tested by the online BIT and to alert the bit retention controller 72 upon detection of a fault, as shown in FIG. . Item 9 time when background microdiagnostics 181 is being performed is the period during which memory accesses do not overlap with microcode execution or during which the processor must wait for another operation to perform. Contains. Also, certain instructions have periods of inactivity (wait state), and in addition, background microdiagnostic fail-safe operations can use periodic timeouts every millisecond to ensure safe operation. can.

1 and 2 will be explained. The method for conducting microdiagnosis is as follows.

That is, machine microinstructions or instruction set architectures (I
SA) Assume that the foreground microprogram counter 24 is used to implement the chain of microinstructions that perform the ration.

This memory fetch is initiated and the processors, including control unit 62 and computing unit 64, begin waiting for system specific data bus 87 to issue valid data. Upon initiation of the memory fetch, the ISA transfers control to the background microprogram counter 26 by means of the ration microinstruction control switch 161.

The control sequencer 76 is thereby switched to background mode and the background microdiagnostic test controlled by the microdiagnostic microprogram counter 26 is executed from one of the test modules shown in FIG. , three microinstructions B1. Execute B2 and B3.

Upon completion of execution of the third microinstruction, this microdiagnostic test transfers control to foreground microprogram counter 2.
A control signal (SWITCH16) is used to cause the swap microprogram counter operation to transfer back to
3 and INHIBIT164). This procedure continues until all test modules that make up the microdiagnostic test are completed.

The micro-diagnostic tests in background mote 9 do not change the operating state of the processor and detect any conditions (general purpose flags, data registers or overflows) that may affect ISA implementation.
prevent doing so. The foreground morte 90 is
I am not aware of the implementation of Background Mote 9 Micro Diagnosis.

FIG. 7 will be explained. Illustrated in this figure is a typical background microdiagnostic program sequence including a control sequencer 187, registered arithmetic logic unit 189, floating point 188 and register 190 test modules. The name of one test module indicates the functional area of the system being tested. Each test module generates short cycle codes (SCCs). When background mode microdiagnostics is enabled and a new functional test module enters, the short cycle codes generated by the previous test module are sent as one parameter to the next module in the sequence,
be inspected. If the sent code is determined to be invalid, the BIT hardware is notified of the defect. Short cycle codes are tested with both operability and background microdiagnostic tests. This short cycle code ensures that a complete micro-diagnostic sequence of the test module is performed and that this sequence is not just a subset of the test module due to latency failures. Background The primary reason for performing microdiagnostics is to reduce fault latency, ie, reduce the time it takes to discover a fault condition.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a microprogram control unit having a control sequencer including two microprogram counters according to the present invention. FIG. 2 is a block diagram of an information processing system showing the control sequencer of FIG. 1 as part of a microprogram control unit. FIG. 3 is a diagram of the hardware structure for implementing two microprogram counters. FIG. 4 is a functional block diagram illustrating fault detection circuitry within the control sequencer for detecting microinstruction address and data errors. 5 is a logic diagram of the control switch shown in FIG. 1 for controlling switching of the two microprogram counters shown in FIG. 1; FIG. Figure 6 shows the operability micro-diagnosis and the background micro-diagnosis? 1 is a hierarchical chart showing a microprogram-test module and a microphone protrusion diagnostic test module formed by JLLT. FIG. 7 is a diagram illustrating the module sequence of tests for a background microdiagnostic test and further illustrating the short cycle codes generated by each test module and examined by subsequent test modules. FIG. 8 is a diagram illustrating switching from a foreground microprogram to a background microdiagnostic microprogram to execute three microinstructions before returning to the foreground microprogram. FIG. 9 is a diagram illustrating one microinstruction address and the field diagram of the microinstruction word stored at the microinstruction address. 10 is a diagram showing a parity tree for generating expected/remaining codes used in the failure detection circuit shown in FIG. 4; FIG. 24...Foreground micro program counter 26...
Background micro diagnosis micro program counter 28...
・Multiplexer 62...Control unit 64...
Arithmetic unit 66...Memory unit 70...Control storage device 76...Control sequencer 90...Input/output unitContinued from page 1 0 Inventor: Steken C.A.・Be Go Amed Tsuji 0 Inventor: Jack G. A. 94 Souf Street, Concord, Massachusetts, United States
Turn Bike 490 34 Rayshore Drive, Hobkinton, Massachusetts, United States

Claims (1)

Claims: 1) A processing system for executing a stored main program, the processing system comprising: memory means for storing a second program; and responsive to selected instructions of at least one of said main program. means for enabling the processing system to execute the stored second program during execution of the selected main program instructions. 2) The processing system according to claim 1, wherein the second stored program includes a microprogram/microdiagnosis. 3) The enabling means comprises a microprogrammed control unit having a control sequencer (1) Processing system according to claim 1. 4) The processing system of claim 3, wherein said selected instructions of said main program are implemented by at least one microinstruction in said microprogram control unit. 5) The processing system of claim 3, wherein said control sequencer includes at least two microprogram counters. 6) The first of said two microprogram counters controls the addressing of microinstructions to implement said main program and the second of said two microprogram counters controls the addressing of said second microprogram counters. 6. A processing system according to claim 5, which controls addressing of microinstructions to execute a program. 7) An information processing system having a microprogram control unit that executes a background microprogram during overlay of a foreground program, the information processing system comprising a plurality of microprogram control units for executing the background microprogram and the foreground program. and control sequencer means for independently controlling said foreground program operation and said background microprogram, comprising at least two microprogram spring counters, a first Control sequencer means comprising two microprogram counters, a microprogram counter participating in the execution of said foreground program and a second microprogram counter controlling said background microprogram. 8) The information processing system according to claim 7, wherein the background microprogram includes a plurality of microinstructions for executing microdiagnosis. 9) The control sequencer means executes one of the microinstructions.
Claim 7, further comprising means for controlling switching between said first microprogram counter and said second microprogram counter in accordance with a plurality of signals from said first microprogram counter and said second microprogram counter.
The information processing system described in Section. 10) said background microprogram comprises a plurality of test modules stored in said memory means, each comprising means for generating and testing short cycle actions to prove the performance of said test module; The information processing system according to claim 7, comprising a test module. 11) An information processing system having a microprogram control unit for executing a background microprogram during oscillations of a foreground program, the information processing system having a microprogram control unit for storing a plurality of microinstructions for executing the background microprogram and the foreground program. memory means for independently controlling said foreground program oscillation and said background microprogram; at least two microprogram counters, a first microprogram counter for controlling said foreground program oscillation; control sequencer means comprising two microprogram counters involved in the execution of the background microprogram, a second microprogram counter controlling said background microprogram, and coding means within said control sequencer means,
An information handling system comprising: microinstruction addressing and coding means for detecting data errors. 12) The encoding means includes a first address for proving the address in the memory means and the contents of the addresses 1 to 1.
12. An information handling system as claimed in claim 11 providing a second code for proof of code and expected next microinstruction address. 13) The second encoding means comprises detection means for comparing said first code with said second code and generating a fault signal when an error is detected.
The information processing system described in Section 2. 14) An information processing system having a microprogram control unit, comprising memory means for storing a plurality of microinstructions for executing a background microdiagnostic microprogram during the operation of the foreground program; a first microprogram counter for generating the address of the next microinstruction during execution; a second microprogram counter for generating the address of the next microinstruction of the background microdiagnostic microprogram; multiplexer means connected to one microprogram counter and said second microprogram counter;
An information processing system comprising multiplexer means for selecting the address of the next microinstruction from either the microprogram counter or the second microprogram counter. 15) Claim wherein said microprogram control unit includes means for controlling switching between said first microprogram counter and said second microprogram counter in accordance with a plurality of switching control signals from one of said microinstructions. The information processing system according to item 11. 16) An information processing system having a microprogram control unit, comprising: memory means for storing a plurality of microinstructions for executing a background microdiagnosis microprogram during an operation of the foreground program; a first microprogram counter for generating the address of the next microinstruction during program execution; a second microprogram counter for generating the address of the next microinstruction of the background microdiagnostic microprogram; multiplexer means connected to a first microprogram counter and said second microprogram counter, said multiplexer means being connected to said first microprogram counter or said second microprogram counter in accordance with an at9less selection signal from said memory means; multiplexer means for selecting said next microinstruction abilis from either of the counters; microprogram Φ stack means connected to said first microprogram counter for executing a microprogram interrupt subroutine; branch status multiplexer means connected to the microprogram stack means, the first microprogram counter, the second microprogram counter and the output address multiplexer, the address of the next microinstruction according to the branch status signal; branch state multiplexer means for generating an address jam input signal, said output multiplexer means receiving said address jam input signal and selecting said source of said next microinstruction address; and branch state multiplexer means coupled to the output signal of said branch state multiplexer means, control switch means connected to said memory means, comprising:
control switch means for switching control of said first microprogram φ counter and said second microprogram counter, and controller means connected to said branch state multiplexer means and said microprogram stack means, said An information processing system comprising: controller means for decoding a function code from the memory means. 17) An information handling system having a microprogram control unit, comprising memory means for storing a plurality of microinstructions for executing microdiagnostic tests and microinstructions; A first microprogram exposure counter for generating the address of the next microinstruction to execute the instruction; The operation of the foreground microinstruction generates the address of the next microinstruction of the background microdiagnostic test being executed during the execution of the foreground microinstruction; a second microprogram counter for generating the foreground macro instructions, the second microprogram counter being under control of an independent program counter. 18) memory means for storing a plurality of microinstructions for executing a background micro-diagnosis microprogram during the foreground program operation; independently controlling the foreground program operation and the background micro-diagnosis microprogram; control sequencer means for at least two microprogram counters, a first microprogram counter participating in the execution of said foreground program;
A microprogram control unit comprising control sequencer means comprising two microprogram counters, the microprogram counters controlling the background microdiagnostic microprogram. 19) The control sequencer means includes means for controlling switching between the first microprogram counter and the second microprogram counter in accordance with a plurality of signals from one of the microinstructions. 19. The microprogram control unit according to item 18. 20) The background microdiagnostic microprogram comprises a plurality of test modules stored in the memory means, each for generating and testing a short cycle code for verifying the execution of the test module. Claim 1 comprising a plurality of test modules comprising means.
9. The microprogram control unit according to item 8. 21. A method for executing a stored main program in a processing system, the method comprising: storing a second program; during execution of selected instructions of the main program by the processing system; 2. A method comprising the steps of implementing a program. 22) O of the foreground program is background during ration. A method in an information processing system having a microprogram control unit for executing a microprogram, comprising: storing a plurality of microinstructions for executing the background microprogram and the foreground program; and at least two microprograms. two microprogram counters, a first of said microprogram counters participating in the execution of said foreground program and a second of said microprogram counters controlling said background microprogram; The method comprises the steps of independently controlling the foreground microprogram and the background microprogram. 23) independently controlling said foreground program oscillation and said background microprogram according to a plurality of signals from said one of said microinstructions;
23. The method of claim 22, including controlling switching between a microprogram counter and the second microprogram counter. 24) executing the background microprogram, executing a plurality of test modules, and in each of the test modules, generating and testing short cycle code to prove execution of the test module; 23. The method of claim 22, comprising the steps. 25) A method for performing fault detection in an information processing system having a microprogram control unit that executes a background microprogram during operation of a foreground program, comprising: a plurality of microprograms for executing the background microprogram and the foreground program; A command, each of which
storing a plurality of microinstructions having one address 9 for each of said microinstructions and a first code 9 for proving the content of said address; a step of controlling with a 0 counter; a step of generating a residual code indicating a code for the current microinstruction address from the first code; A method comprising the steps of: generating and storing a second code for a 9 response; and comparing the remaining code with the second code to detect a fault.