JPS6025375A - Data communication equipment - Google Patents

Abstract

PURPOSE:To reduce a time required for pre-processing of transmission by analyzing statistically a transmission rate used before and deciding the transmission rate to be used on the basis of the result. CONSTITUTION:A transmission rate storage circuit 31 and counted value storage circuits 32, 33 are connected to a controller 39 of a facsimile transmitter. The transmission rate to be tried by the transmitter at first is stored in the count value storage circuit 32. The data how many times the picture transmission is executed continuously actually with the transmission rate tried at first by the transmitter is stored in the counted value storage circuit 32. The data as to how many times the transmission if failed continuously at the transmission rate tried at first is stored in the counted value storage circuit 33. The controller 39 decides the transmission rate to be used on the basis of the stored statistical data.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a data communication device, and more particularly to a data communication device capable of transmitting data at a plurality of transmission rates.

Prior Art Conventional data communication devices, particularly G3 (Group 3) facsimile devices specified by CGITT Recommendation T4, etc., have a so-called fall pack function, that is, in a pre-transmission procedure, a function is used that responds to the line status or the transmission rate of the other party's machine. A known method is to try each rate in order from the highest to lowest, and to perform image transmission at a rate that can be transmitted and received by both sides.

Here, FIG. 1 shows the transmission rate determiner 11 "l" in the pre-transmission procedure of a conventional facsimile machine. However, here, a facsimile machine having the 03 function that complies with CCITT Recommendation T Recommendation is used as an example. explain.

Figure 1 shows the exchange of signals between the transmitter and the receiver during the pre-transmission procedure of a conventional 03 facsimile machine. In response to the CHD signal (called station identification signal) ■, NS
The F signal (non-standard bag 71 signal) 2 and the DIS signal (digital identification signal) 3 are sent out. However, NSF signal 2
Optionally, CS I 4M as shown
A signal (receiving station identification signal) 2' may be added. This C3I signal is used to confirm the identity of the receiving station using a telephone number or the like.

These NSF signal 2 and DIS signal 3 are both known HDT signals.
, C (High Level Transmitter 11 [1)] is a binary signal having a frame format, and the 11.12 bits of the FIF (Facsimile Information Field) of the DIS signal 3 contain the instructions of the receiver to set the predetermined format. The highest transmission rate, for example 9800 bPS, is set.

Next, the transmitter sends out an NS3 signal (non-standard device setting signal) 4 and a DC3 signal (digital command signal) 5 in response to the above-mentioned NSF signal and DIS signal, respectively. These also have the HDLC frame format, and the highest transmission rate on the transmitter side is similarly placed on the FIF of the DC5 signal. Here, it is assumed that data indicating 9E100 bps is set in the 11th and 12th bits in the DIS signal 3 and the DC3C16. Further, a TSI signal (transmitting station identification signal) 4' may be optionally coupled to the NSS signal 4. This signal is used to confirm the identification of the transmitting station in the same way as the C3I signal 2'.

At this stage, both the transmitter and the receiver were able to transmit at 9θ (11) bps, so the transmitter
Training signal 6 is sent out following C3C16. The data rate of this signal is 9800 b'ps, and the called side (
Carrier detection, AG'C in the modem on the image receiving side)
(automatic gain 1) adjustment), timing period, equalizer convergence, and descrambler synchronization. Furthermore, this l-laning signal %6 uses TCP to check whether this speed channel can be used.
A signal (training check signal) 7 is added.

The criteria for determining the speed channel on the receiving side is determined by the reception state of the TCP signal 11 from the transmitting side device. T.C.
The P signal 11 is “0” at level 1.5s (hereinafter referred to as rOJ
Since it is a continuous transmission of ``2 TCF'' after a predetermined period of time
Many devices are designed to transmit a CFR signal when a signal can be received.

If the receiving device is successful in training, the receiving device sends out a CFR signal (reception readiness confirmation signal) 8.
In response to this, a message (image signal) 10 to which the training signal 6 has been added is transmitted from the transmitting side.

The second example below is for a case where the transmission rate is determined by one training session without fall-packing, but if the line condition is poor, a fall-packing operation as shown in fJr 2 diagram is performed.

FIG. 2 is a diagram in the same format as FIG. 1, and it is assumed that the same procedure as in FIG. 1 is followed until the TCP signal 7 is sent from the transmitting side, and that a rate of, for example, 9600 bPS has been confirmed on both sides.

If the receiving device cannot receive the training signal from Data Ray I mentioned above due to line conditions, etc.
The receiver sends out an FTT signal (train failure even) 10. This signal requests retraining from the transmitter.

In response to this FTT signal 8, the transmitting side device again performs training consisting of NSS signals 4 to TCF signals 7, but at this time, the rate set in the FIF of DC5 signal 5 and the data rate of training signal 310 are Something lower than the 9600bps mentioned earlier, for example? 200 bps
is selected.

If the receiving device fails in this retraining, the receiving device sends out the FTT signal 10 again.

When the transmitting device receives the F
A signal block consisting of signals 4 to TCF signals 7 is sent out.

If the receiving side device succeeds in I-learning using this rate I, the above-mentioned CFR signal 8 is transmitted, and in response, the transmitting side device transmits the training signal 6 and the message 10 based on the final rate. Send.

In the pre-transmission procedure of the conventional facsimile machine shown below, the transmission rate indicated by the DIS signal or the DC3 signal is declared unique depending on the capability of the facsimile machine. Therefore, if the device is installed in a place with poor line conditions, the rate is determined after trying out rates that are not possible to communicate with, which means that the pre-steps take a lot of time and are not efficient in terms of time and economy. There is a drawback that it is bad. In view of this, devices are known that allow you to switch and set the fastest transmission rate, but if you lower the maximum rate using this method, you will only be able to communicate at that rate even if the line condition is good. , there is an inconvenience.

Purpose The present invention has been made in order to eliminate the above-mentioned conventional drawbacks, and provides an efficient data communication device that can quickly determine a transmission rate and shorten the time required for pre-transmission procedures. It is intended to.

EXAMPLES Hereinafter, the present invention will be explained in detail based on examples shown in the drawings.

In the following example, G3 which conforms to CCITT Recommendation T4 is used.
This will be explained using a facsimile transmitter as an example.

An uninvented facsimile machine statistically analyzes the transmission rates used so far, and determines the transmission rate to be used based on the results.

Figure 3 shows a facsimile transmitter adopting the present invention.
Control device 3 composed of a microcomputer, etc.
It is assumed that each block shown on the right side of the figure and the subsequent circuit (not shown) are constructed in the same manner as in the conventional case.

On the other hand, each circuit block shown on the left side of the figure is a memory circuit, which is a random access memory or a control device 3.
It is composed of arithmetic registers in 9, etc.

Reference numeral 31 indicates a transmission rate storage circuit, which is connected to the control device 39 through signal lines 31a and 31b. This transmission rate I storage circuit 31 stores the transmission rate that this transmitter should try first.For example, if the transmission rate is 9,600 bps, then "3" is selected. 20
In the case of 0 bps, "2" is cented, in the case of 4800 bps, "1" is cented, and in the case of 2400 bps, "0" is cented.

Further, a count value storage circuit 32 is connected to the control device 639 via signal lines 32a and 32b, and this count value storage circuit 32 stores the actual transmission rate at the transmission rate initially attempted by the transmitter. Data regarding how many times image transmission has been performed consecutively is stored.

The count value storage circuit 33 is a circuit similar to the count value storage circuit 32, but on the contrary, data regarding the number of times the transmission at the first attempted transmission rate has failed is stored here.

The training ΦTCF signal sending circuit 34 on the right side of the figure is
9600.9600, respectively, in response to pulses 50-53 generated by controller 39 on signal lines 34a-d, respectively.
A training signal set at 7200.4800 bps or 2400 bps and a TCP signal are sent to a subsequent modem via an adder or the like.

The NSS, TSI, and DC3 signal sending circuits 35 respond to pulses 54 to 57 generated by the control device 39 on the signal lines 35a-d, respectively, to generate 9600.72.
The NSS, TSI, and DC3 signal sent at 00.4800 or 2400 bps are sent to the subsequent modem at a predetermined timing via a q adder or the like.

On the other hand, NSF, C5I, DIS Shinkyu trust detection circuit 36
NSF and C sent from the receiving side at predetermined timing.
3I, and DIS signals, and generates pulses according to the rate sent to those signals. That is, each of the above signals is 8600.72
00.4800 or 2400 bps, the control unit 4 is connected via the signal lines 36a-d, respectively.
39, pulses 58-61 are sent.

Furthermore, the CFR signal detection circuit 37 detects the CFR signal from the other party.
When a signal is detected, a pulse 62 is generated on the signal line 37a. Similarly, when the FTT signal detection circuit 38 detects an FTT signal from the other party, it outputs a pulse 6 to the signal line 38a.
Generates 3.

As described above, the data rate and each signal on the receiving side are detected and notified to the control device 39.

The transmission rate control of the control device fii 39 is performed as follows. The control device 39 controls the transmission rate stored in the count value storage circuit 32 or 33, and if the transmitter succeeds or fails in three consecutive image transmissions at a certain transmission rate that the transmitter first tries, The rate is increased by one level, but each part is controlled so that a pre-procedure is performed to lower the rate.

In other words, if image transmission is performed three or more times using the transmission rate I (i.e., the rate specified by the data in the transmission rate record 70 circuit, hereinafter referred to as the initial test rate) that the transmitter first attempts, In the next pre-step, testing is performed by falling back in order from the rate one higher than the transmission rate a. On the other hand, if image transmission using (a) is not carried out three times in a row (initial test), 1
Start the procedure at the lowest rate. At this time, the value of a is the highest or lowest rate of the device, and if the rate cannot be increased or decreased any further, the procedure is started at that rate.

Next, the above control will be explained in detail with reference to FIGS. 4(A) to 4(F).

FIGS. 4(A) to 4(F) are flowcharts for explaining the control procedure of the above-mentioned control device 39, and in each figure, the parts given the same number are connected there.

When the device is powered on, the control device 39 performs the transmission rate storage circuit 31 to count value storage circuit 32.3 in steps 5ioo to 3102 in FIG. 4(A).
In other words, in step 3100, the control device 39 first writes "3" indicating 91,300 bps into the transmission rate storage circuit 31 via the transmission line 31b.

Furthermore, in steps 5101 and 102, "0" is written into the count value storage circuit 32 and the count value storage circuit 33 through the signal lines 32b and 33b, respectively. As a result, image transmission was successful at the initial test rate.
and the number of consecutive failures is reset.

Subsequently, in the determination loop from step 3103 to step 3106, the following determination is made.

First, in step 5103, it is determined whether or not the pulse 50 has occurred on the signal line 36a, so that the received NSF, CSI, or DIS signal is 8E100bp.
Determine whether it is set to s.

In step 5104, by checking the state of the signal line 36b, the received NSF, C5I or D
Determine whether the IS signal is set to 7200 bps.

In step 5105, the state of the signal line 36c is checked in the same way, and the received NSF, C3I, or DIS signal is 4
Determine whether it is set to 800 bps.

In step 310B, the state of the signal line 36d is checked in the same manner, and the received NSF, C3I, or DIS signal is 2.
It is determined whether or not it is set to 400 bps.

The above determination loop is repeated in order until any rate is detected, but if the rate is detected in the above steps, the process moves to the following steps.

If the transmission rate on the receiving side is 8800 bps, step 5191 (FIG. 4 (F)) is executed.4
．． If it is 800 bps, step 5195 (
In FIG. 4(F)), if it is 2aOobps, the process moves to step 3199 (FIG. 4(F)).

Receiving side NSF, C3I, no LDIS signal [1]8
In the case of 00 bps, in step 5107, the control device 39 inputs the signal on the signal line 31a, that is, the output of data indicating the initial test rate stored in the transmission rate storage circuit 31, and then in steps 3108 to 3107.
The signal is determined by the determination routine of 5Lio.

First, in step 5108, the signal input from the signal line 31a is "3", that is, the initial test rate is 98.
In step 3109, it is determined whether the signal is "2", that is, the initial test i rate is 720 bps.
In step 5110, it is determined whether the input signal is "1", that is, the initial test rate.

If any of the above steps St 08 to 3110 is affirmed, step 3122 (Fig. 4 (B
)), the process moves to step S i 5 1 (FIG. 4(D)) or step 3171 (FIG. 4(E)). Further, if all of the above steps are negative, it is determined that the initial test rate is 2400 bps, and the process moves to step Sill. Here, it is assumed that "0", that is, data indicating the initial test rate of 240 Qbps, has been stored in the transmission rate storage circuit 31 according to a procedure to be described in detail later, and the process moves to step Sill to continue the explanation.

In step Slit, a pulse 57 is output to the signal line 35d, and the NSS, TSI, or DCS signal sending circuit 35 sends an NSS, TSI, or DCS signal set at 2400 bps to the other party via the line.

Further, in step S112, the signal line 3 4
Output pulse 53 to d, transmission rate 2400bpS
Send the TCP and training signal set to the other party.

When the above training is completed, steps 3113~
In the determination loop of 3114, a CFR signal or FTT signal from the other party is waited for.

First, in step 3113, in order to check whether a CFR signal from the other party is detected, it is checked whether a pulse 62 is generated from the CFR signal detection circuit 37 on the signal line 37a.

If the CFR signal is received, the process moves to step S117; otherwise, the signal line 38 is connected to the signal line 38 in step S114.
Check whether pulse 63 has occurred at a, and send F from the other side.
Check whether a TT signal has been transmitted. Step 311
4 is denied, the process returns to step S113 and the above determination is repeated. However, if the FTT signal is received, that is, step S114 is affirmed, the process proceeds to step S115, and the count value is recorded via the signal line 32b. Seventy circuits 3
After writing "0" to 2, the process ends in step 3116 with an error, and returns to step S103 to prepare for the next communication.

This is because training at the minimum rate of 2400 bps of this device failed.

If we summarize the state when step S11.7 is reached in the above order, the opponent's first test lay-1 is HOObps.
, and the initial test rate indicated by the data in the transmission rate storage circuit 31 on this side is 2400 bps,
With this rate, training was successful in one attempt, that is, image transmission could be performed at the first attempted rate of 2400bl)S.

Therefore, in step 3117, the signal line 33b
rOJ is written into the count value storage circuit 33 via the.

That is, the number of consecutive times that image transmission could not be performed at the initial test rate is reset to O.

Subsequently, in steps 3118 to S120, the count value storage circuit 32 indicating the number of consecutive image transmissions by the first test rate 1 is incremented, and the first test rate transmission for the next communication is performed according to the contents of the count value storage circuit 32. Write to rate storage circuit 31.

First, in step S118, the number 4M of the signal line 32a is input, and the number of consecutive image transmissions at the initial test rate in the count value storage circuit 32 is taken out.

Subsequently, in step Sl 18a, it is determined whether the extracted signal is "2", that is, the first test trace 1.
・Check whether the number of consecutive image transmissions has already reached 2 times.

If step 3118a is negative, the number of continuous image transmissions K at the initial test rate including the current transmission is less than 3, so the process moves to step S119, and after adding 1 to the input signal, step 3120 Then, the value is written into the count value storage circuit 32.

In addition, if step 5118a is set to 11, the number of consecutive image transmissions K by the initial test ray 1 is performed three times in a row this time, so the next initial test ray I In order to set the speed to 4800 bps, "1" is written in the transmission rate storage circuit 31 via the signal line 31b in step 5118b.

Subsequently, in step S118c, rOJ is written via the signal line 32b in order to cause the count I/value storage circuit 32 to start a new count.

When the above counter control is completed, the process moves to step 5121 and the control unit 39 controls each part according to a known procedure to perform image transmission at 2400 bps, and then returns to step 5103 to start the next communication. Prepare for.

- In step 5103, the other side's transmission rate is 9600 bps, and in step 5108, the first test rate of this side is indicated by the transmission rate storage circuit 31, and the process moves to step 3122.

In steps 3122 to S123 in FIG. 4B, a pulse 54 is generated on the signal line 35a, and a pulse 50 is generated on the signal line 34a.

This will do the same thing as above! [N by 00 bps
S.S. A TSI or DCS signal, a TCF signal, and a training signal are sent to the line, and training is performed at 8600 bps.

Subsequently, in the 'r1 constant loop of steps S124 and S127, the training result is determined by detecting the CFR signal or the FTT signal. This operation is performed by checking the states of signal lines 37a8 and 38a, as described above.

If the CFR signal is received in step S124, the process moves to step 5125, and the i! J! After writing "0" indicating the number of consecutive image non-transmissions θ times, the process moves to step S126, where the image is transmitted at 9800 bps, and then returns to step S103 to prepare for the next communication. Here, the reason why the count value storage circuit 32 is not incremented is because the rate cannot be increased any further at the next initial test rate indicated by the contents of the transmission rate storage circuit 31.

On the other hand, if the F'r T signal is received in step S127, the process moves to step 3128, and "0" indicating the number of consecutive image transmissions KO by the first test tray 1 is stored in the count 4N storage circuit 32 via the signal line 32b. Write. This is because since image transmission cannot be performed at the initial test rate this time, the counter control is used to control the number of consecutive image transmissions at the initial test rate from the next communication.

If you have come this far, you have already reached 1 by 9600 bps.
Since the previous training failed, in the following steps, the rate will fall to 7200 bps or less and the training will be performed again, but before that, the contents of the transmission rate storage circuit 31 and the count value storage circuit 33 will be changed as follows. control.

First, in step S129, the contents of the count value storage circuit 33 are input via the signal line 33a, and in step SL
At step 3.0, r1 determines whether the signal is "2", that is, whether the number of continuous image non-electronic transmissions by the first test tray I. has already reached two.

If step S130 is affirmative, the number of continuous image non-transmissions by the first test rate 1 will be three times, so the first test rate of the next communication will be lowered by one? 2
00 bps, the signal line 31 is connected in step S131.
7200b to the 0 circuit 31 via the wire I/recording b.
Write “2” without indicating ps, then step S132
“0” is sent to the count memory circuit 33 via the signal line 33b.
”. This is to set the number of continuous image non-transmissions at the initial test rate anew from the next communication.

On the other hand, if it is determined in step S130 that the number of continuous image non-transmissions based on the initial test rate is not 2, step S130
133 and S134, the contents of the count value storage circuit 33 are incremented by 1 via the signal line 33b in the same manner as in the case of increasing the current storage circuit 32.

When the above control of the count value storage circuit 33 and the transmission rate storage circuit 31 is completed, steps 5135 and 513
6 routine, NSS, TSI, DC3
A pulse 55 and a pulse 51 are given to the signal sending circuit 35 and the training and TCF signal sending circuit 34 in order, respectively, and ? Perform retraining with 200bPS.

Subsequently, in steps 5137 and 5139, it is determined whether the signal from the other party is a CFR signal or an FTT signal in the same manner as in steps 5124 and 3127.

If a CFR signal is received in step 5137, the process moves to step 5138, and a known procedure is performed. After performing image transmission at 200 bps, return to step 5103,
Prepare for the next communication. As mentioned above, the count value storage circuit 32 or count value storage circuit 33 is operated depending on whether the image transmission at the initial test rate is performed continuously (I-) or not continuously. In fallback operations below this, the count value storage circuit 32 or count value storage circuit 33 is not controlled.

On the other hand, when the F'I''r signal is received in step 5139, the process moves to steps 3140 and 5141, and pulses 56 and 52 are generated in sequence to the signal lines 35c and 34c, respectively, and a fall puncture occurs at 4800 bPS. After training, Figure 4 (C
), the process moves to the decision loop of steps 5142 and 5144, and waits for a CFH or FTT signal from the other party.

If a CFR signal is received in step 5142, the process proceeds to step 5143 in the same manner as described above, and
After performing the image transmission using PS, the process returns to step 5103 and prepares for the next communication.

Alternatively, if the FTT signal is received in step 5144, the routine moves to steps S145 and 5146, and pulses 57 and 53 are sequentially generated on the signal lines 35d and 34d, respectively, in the same manner as described above.
Fall back to s and train again.

Furthermore, after this, in the determination loop of steps 5147 and 5149, a CFH or FTT signal is waited for in the same manner as described above, and if a CFR signal is received here, step 5
After performing image transmission at 2400 bps in step 148, the process returns to step 5103. On the other hand, if an FTT signal is received, since no further fallback is possible, the line is disconnected νj as a pre-procedure error, and the process returns to step 5103.
Prepare for the next communication.

On the other hand, in step 5103, the transmission rate of the other side is 9800 bps, and in step 5109, what is the initial test rate of this side indicated by the 11i transmission rate storage circuit 31? If the speed is 200 bps, then Fig. 4 (
The process moves to step 5151 of D).

In the routine of steps 5151 and 5152 in FIG. 4(D), pulses 55 and 51 are sequentially generated on signal lines 35b and 34b, respectively, and the same procedure as described above is performed. Training is performed at 200 bps.

Next, in the determination routines of steps 5153 and 5163, the CFH or FTT from the other party is determined in the same manner as described above.
Wait for the signal. If a CFR signal is received, step 5
The process moves to step 154, and if an FTT signal is received, the process moves to step 5164.

If a CFR signal is received here, image transmission can be performed at the initial test rate, so Stella: 7'315
4 to 5158, the same count value storage circuit 32 and transmission rate record 1. The α circuit 31 is operated.

That is, after clearing the count (If memory circuit 33) in step 5154, the data in the count value memory circuit 32 is entered manually in step 5155, and it is checked whether it is "2" or not in step 5156. If it is the third consecutive transmission, "3" is written in the transmission 1/- rate storage circuit 31 in order to step up the next initial test rate 1 to 9G00 bps in step 5157, and then counting is performed in step 3158. Clear the value storage circuit 32.

On the other hand, if the data in the count value storage circuit 32 is not 2 in step 5156, steps 5160 and 5
At step 161, the contents of the count value storage circuit 32 are incremented by one.

The above routine of steps 3154 to 5161 is executed in step 5157 in order to determine the next initial test rate.
Steps 3117 to 5120 above except for writing “
is equivalent to a routine consisting of Therefore, the above equivalent routine may be a subroutine that is called after setting parameters related to the initial test I rate to be set in the transmission rate storage circuit 31.

When the above operations are completed, the process moves to step 3159, where the image is transmitted at 7200 bps, and then step 5
Return to 103.

If the FTT signal is received in step 5163, the first image cannot be transmitted at the initial test rate, so the routine proceeds to steps 5164 to 5170, and the same steps as described above are carried out to transmit the transmission signal, memory circuit 31, and cursor. The above routine of steps 5164 to 5170 also operates the transmission rate storage circuit 31 L: 4800 bps in step 5167 to determine the next initial test rate.
I J Woni: f! Step 51 above except for
Since the routines consisting of 28 to 3134 are equivalent, please refer to that part for the operation of this part. Therefore, the above equivalent routine can also be made into a subroutine.

When the operations of the transmission rate symbol, 0 circuit 31 and count value storage circuit 33 are completed, the routine proceeds to step 3140 and subsequent steps in FIG. 4(B), and step 4800b
Training and image transmission are performed in order from ps to fall puncture.

Furthermore, if "1" indicating 4800 bps is stored in the transmission rate storage circuit 31 in step 5ito, the process moves to step 5171 in FIG. 4(E).

Each step from step 5171 to step 5190 in FIG. 4(E) is equivalent to each step from step 5L51 to step 5170 in FIG. . Therefore, although a detailed explanation will be omitted, these routines can be made into subroutines like the aforementioned routines.

The difference is 480 in steps 3171-3172.
Sending 0 bps NSS, TSI, DIS signals, training signals and TCP signals, step 51
In step 77, "2" indicating 7200 bps is written in the transmission rate storage circuit 31, and in step 5187, "0" indicating 2400 bps is written in the transmission rate storage circuit 3.
1, and image transmission in step 3179 is performed at 4800 bps.

Basically, if the training at 4800bps is successful, the count value storage circuit 33 is cleared and the state of the circuit 32 is checked, and if it is 2, then the Write "2" indicating 7200 bps to the rate storage circuit 31, and if it is not 2, increment the count value storage circuit 32 by l, and
Image transmission is performed at 0 bps.

Furthermore, if the 4800 bps training fails, the count value memory circuit 32 is cleared and then the state of the count value memory circuit 33 is checked, and if it is 2, "0" indicating 2400 bps is written in the transmission rate memory circuit 31.
is written, and if it is not 2, the count (tri memory circuit 3
2 is incremented by 1, and then the process moves to step 5145 in FIG. 4(C) to fall/header to 2400 bps.

With the above, the transmission rate I declared by the other party is 9eOObps.
I have explained all the routines that can be followed by a fall pack in that case. Step 31 in Figure 4(A)
04-5106-111-The other party? If any rate below 200 bps is declared, see Figure 4 (F).
By proceeding to the routine shown in Figure 1 and jumping from there to a predetermined location in the routine described above, fallback and integrated control of Ray i is performed.

First, step 3104 is affirmed, that is, is the other party? If you declare 200bps, the 4th IQ(F)
The process moves to step 5191. In step 3191, the data in the transmission rate storage circuit 31 is inputted via the signal line 31a, and in steps 5192 to 5194, it is determined whether the data is "3", "2", or rlJ, that is, the transmission rate storage circuit 31. It is determined whether the initial test rate on this side specified by the circuit 31 is 9600, 7200, or 4800 bps.

If step 5192 is affirmative, the process moves to step 5135 in FIG. 4(B). Perform training by falling back from 200 bps. In this case, the first test rate is determined by the highest rate of the other device, so in this case only, the transmission rate storage circuit 31, count ifi storage circuit 32, and count value storage circuit 33 are not operated, and the statistical data is frozen. .

7200bpS if step 5193 is set to 0
Since it is possible to fallback from , proceed to step 3151 in FIG. 4(D). Fallback from 200 bps to Ill &(3.

If step 5194 is affirmative, the process moves to step S'171 in FIG. 4(E) and falls back from 4800 bps.

If each of the following steps is negative, the process moves to the initial test rate step stit specified by the transmission rate storage circuit 31, and training is performed at 2400 bps.

・On the other hand, step S105 in FIG. 4(A) is affirmed.
That is, if the other party declares 4800 bps, the process moves to step S195. Steps S195 to S1
98 is equivalent to steps S191 to S194 described in [2], and here, the same determination as described above is performed.

If steps S196 and S197 are determined, communication is possible only at a speed of 4800 bps or less, so here step 314 in FIG.
0 and falls from 4800 bps. In this case as well, the tool 1 data is frozen.

If step S198 is affirmed, 4800 bps
Since it is possible to fall back from 4800 bps, we move to Fig. 4 (E) and fall back from 4800 bps.

If steps SL96 to SL8198 are negative, the process moves to step Slit in FIG. 4(A), and 2400bp
Perform training with s.

Further, step S106 in FIG. 4(A) is affirmed.
That is, if the other device declares 2400 bps, the process moves to step S199, and steps 8199 to S20
In step 2, the same determination as described above is made.

Here, the contents of the transmission rate storage circuit 31 are 8600 to 4.
Even if 800 bps is indicated, communication is only possible at 2400 bps, so if any of steps S200 to S202 is affirmative, step 3145 in FIG. 4(C)
, and perform training at 2400bps. In this case as well, statistical data will be frozen.

In addition, here, 'double feed relay; tQ circuit 31 is 2400.
bps, step S in FIG. 4(A)
1ll and perform training at 2400bps.

As described above, the number of transmissions at the first attempted li transmission rate is statistically analyzed and I-learning is started from an appropriate rate. training can be started immediately, reducing the time required for pre-transmission procedures.

In the above embodiment, the initial test rate or the number of consecutive non-electronic transmissions for changing the initial test rate 1 is set to three times, but other times may be used. Furthermore, the method of statistical analysis is not limited to the method described in 1-1 above, but may be determined by considering the average number of IL fallbacks or the maximum usage rate.

Various methods are possible.

Furthermore, the present invention can be applied to receiving side devices, etc., and instead of starting training from a statistically determined rate as described in -, the same result can be achieved by declaring that rate in an initial identification signal etc. You can get the effect.

Further, although the embodiment described below is a facsimile machine, it goes without saying that the present invention can be applied to other data communication devices.

Effects As is clear from the above description, according to the present invention, in a data communication device that performs data communication at a transmission rate determined according to a predetermined pre-communication procedure, predetermined statistics regarding the transmission rate used for communication are calculated. Since it has a configuration that includes a means for storing data and a control means for determining the transmission rate to be used based on the statistical data stored in this storage means, the time required for pre-communication procedures is shortened and line acquisition is possible. It is possible to provide an efficient data communication device that can save time.

[Brief explanation of the drawing]

FIGS. 1 and 2 are explanatory diagrams showing the procedure for determining the transmission rate in a conventional facsimile machine, FIG. 3 is a block diagram showing the configuration of a facsimile machine adopting the present invention, and FIGS. ) is a flowchart 1 diagram explaining the operation of the apparatus shown in FIG. 3. 31... Transmission rate storage circuit 32... Count value storage circuit 33... Count value storage circuit 39... Control device Fig. 1 Fig. 2

Claims (1)

[Claims] In a data communication device that performs data communication at a transmission rate determined according to a predetermined pre-communication procedure, means for storing predetermined statistical data regarding the transmission rate used for communication, and a method for storing statistical data stored in the storage means. 1. A data communication device comprising: control means for determining a transmission rate to be used based on the data transmission rate.