JPS60247960A - General mos integrated circuit and method of producing same - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates generally to the construction and fabrication of complex MO8 integrated circuits, and more particularly to the construction and fabrication of complex MO8 integrated circuits, including both N-channel and P-channel MOS transistors and large value transistors. resistance and
The present invention relates to a method and structure for forming an MO8 pre-circuit with a very thin gate insulator and which can be used as a charge injection device or a capacitive storage device.

Prior Art MO8 integrated circuits have become increasingly complex in both their structure and circuit function. For this reason, specific manufacturing methods are generally developed for specific types of circuits. For example, dynamic random access memory (D
(RAM) requires N-channel MOS transistors with very low leakage self-aligned gates and small, high value storage capacitors. Static random access memory (SRAM) requires gigaohm resistors with tightly controlled values. In complementary MO8 (CMO8) integrated circuits, it is necessary to add an N-type or P-type trench to separate the N-channel transistor from the P-channel transistor. Since N-channel and P-channel transistors are formed by separate alignment steps, when contacting both sets of transistors with one set of contact openings,
Very tight margins are required. Yet another type of MO8
Integrated circuits, electrically erasable programmable read-only memories (E E P ROMs), require extremely thin oxides through which electrons must pass to form the changeable active storage elements. requires precise control.

Another problem with many existing MO8 integrated circuits is that they tend to produce so-called soft errors due to background radiation consisting of alpha particles. This rough 1~
A number of techniques have been used to reduce error problems, including shielding directly on integrated circuits;
The only thing that can completely eliminate this soft error problem is DR.
Only when AM and EEPROM are implemented with low sensitivity CMO5 circuits.

Yet another problem with very dense MOS memory arrays is the problem of so-called hard errors caused by defective elements in the array itself. In this case, the memory cells will have a rate of random defects that will permanently lock them into one logic state. Even if the amount is less than 1 percent of the cells in the circuit, the cells cannot be repaired and the circuit itself must be scrapped, which increases costs. . One way to reduce this failure rate is to provide extra cells and use fused link or laser techniques to separate the defective cells from the array and cut the defective elements from the array 1'. However, these techniques have significant drawbacks. The fused link method, for example, requires a large number of transistors to reliably cut the desired fused link. The laser method is
Unusable after covering the array. Accordingly, it would be desirable to provide an array component that overcomes these and other drawbacks. Additionally, a general purpose MQS fabrication method for forming high resistance polysilicon load resistors for low power single channel logic circuits and SRAMs;
It would be very convenient if there was a CMO8 that could be used for DRAM and EEPROM.

Accordingly, it would be desirable to provide a method for manufacturing a general-purpose MO8 integrated circuit that forms CMO3, EEPROM, and large value load resistive elements on a monolithic substrate. Even if all of these elements are not needed in a single circuit, to save significant development costs and capital associated with the manufacturing process,
It is highly desirable to provide a manufacturing method for various types of MO3 integrated circuits. This facilitates production rationalization and scheduling.

OBJECT OF THE INVENTION An object of the present invention is to provide an MO3 system that realizes various MO8 technologies.
An object of the present invention is to provide a method for manufacturing an integrated circuit and a structure thereof.

Another object of the present invention is to fabricate EEPROM devices with single channel transistors in a memory array, providing redundancy at both the wafer and package level to enable defective cells to become inoperable. An object of the present invention is to provide a method and a structure thereof.

Still another object of the present invention is to provide E-EPROM and CMO
An object of the present invention is to provide a method for manufacturing an MO8 integrated circuit and a structure thereof, which allows eight devices to be bonded to a monolithic substrate.

Yet another object of the present invention is to combine EEPROM, CMO8, and large value polycrystalline resistors into a monolithic substrate.
An object of the present invention is to provide a method for manufacturing an MO8 integrated circuit and four structures thereof.

SUMMARY OF THE INVENTION In accordance with a preferred embodiment of the present invention, a fabrication method for an MO5 integrated circuit is provided that forms thin oxide regions suitable for CMOS transistors, large value thin film load resistors, and EEPROM cells. In this new method and the structure made thereby, polycrystalline silicon insulated from the substrate is provided at two levels. The second level polycrystalline silicon is used as the floating gate of E E I) ROM, and the second level polycrystalline silicon is used as all regular enhancement and depletion gates and as a large value thin film resistor. used. A buried layer is provided as a separate interconnect.

According to another embodiment of the invention, the source and train contacts of the complementary transistors are opened separately and the reflow step is performed after the contacts to the N-channel device are opened.

In accordance with yet another embodiment of the present invention, defective portions of a redundant memory array are cut using new seed-formed EEPROM elements.

These and other objects, features, and advantages will become apparent from the following detailed description of the preferred embodiments, taken in conjunction with the accompanying drawings.

The accompanying drawings show the sequence of manufacturing steps, with the final structure shown in FIG.

Referring first to FIG. 1, the starting substrate of the present invention is a P-type monocrystalline silicon substrate 1, preferably in the form of a thin circular wafer, only a portion of which is shown in FIG. There is. growing or depositing an oxide layer 20 on the substrate;
A thin layer 30 of photo-etch resist is deposited over this oxide layer 20. Photoresist layer 30 is patterned using a suitable mask using techniques well known in the microelectronic art.

This layer is then used as a mask of oxide 20 to an etchant, preferably a fluoride-based etchant. Patterned oxide layer 20 and photoresist layer 30 as described above
Using the combination as a mask for N-type ion implantation, an N-type region 2 is formed. The implanted species are preferably arsenic or phosphorous, and in order to form the N-type grooves or depressions 2 in the P-type substrate 1, the total amount of the implanted species is between 1012 and 1013 It is square am.

This ultimately results in one or more P-channel MO8
be suitable for the device. N-type ion implantation may be performed into region 2 through oxide 20 to reduce surface damage. In this case, the photoresist layer 3
0 becomes the main mask defining the N-type region 2 and the oxide layer 20 is etched after completion of the implantation step.

Then, the photoresist layer is stripped off and N-type implantation is performed by long-term high temperature operation to form a 3X
An N-type surface density on the order of IO'' atoms/cm3 is obtained.

Referring to FIG. 2, an oxide layer 21 is regrown in the window above N- region 2 to form a step for aligning the next mask. This regrowth occurs during the initial portion of the drive-in when an oxidizing atmosphere is used.

After growing the oxide layer portion 21, a layer 25 of silicon nitride is deposited over the entire surface of the substrate 1 and another layer of photoresist is patterned to provide photoresist regions 31 that serve as a mask for the P-type implantation. Try to leave it behind. This P-type implant serves as an N-channel field implant, eliminating unwanted electrical interactions between closely spaced N-channel devices.

Referring to FIG. 3, yet another photoresist layer 32 is
The photoresist is patterned to leave one or more openings over N-region 2 and is used as a mask for N-type ion implantation to form region 4.

This region acts as a P-channel field region, with closely spaced P-channels forming substantially into region 2.
Eliminate interaction between channel devices. N-type implants use arsenic or phosphorus in amounts of 1
01 to 1013 atoms/cm2.

This amount must be sufficient to overdope that part of the P-type region 3 formed in the previous step.

Referring to FIG. 4, photoresist layers 31 and 32 are stripped and field oxide regions 22 are provided over P- regions 3 by masking with nitride layer 25 and selective thermal oxidation. After etching a portion of this field oxide, a pattern of photoresist layer 33 is formed.
is provided as a mask for the implantation of a large amount of phosphorous, which forms the heavily doped N0 region 5. After this implantation, the same photoresist layer 33 acts as a mask for a plasma etch which removes a portion of the nitride layer 25 above the N+ region 5 and overlays it by a second high temperature oxidation process. Grow field oxide. After this oxidation, the remaining portions of nitride layer 25 and oxide layer 20 are removed by plasma etching.

Referring to FIG. 5, a first gate oxide layer 23 is applied to the surface of the substrate 1 in the regions between the field oxide portions 22.
is grown.

FIG. 6 shows a patterned photoresist layer 34 that is used to form localized holes in the first gate oxide layer 23 suitable for tunnel oxide. The tunnel oxide is grown to a thickness of approximately 1'OOO.

To explain FIG. 7, the pattern of photoresist [3
5 is provided as a mask for a heavy phosphorus implantation which forms a heavily doped N+ region 6 beneath the tunnel oxide 24. The purpose of this region is to form a thin tunnel oxide 24
The objective is to be able to establish a high electric field across the entire range.

Next, as shown in FIG. 8, a first polycrystalline silicon layer 40 is deposited over the entire surface of the substrate 1. Preferably, the polycrystalline silicon layer is deposited undoped to a thickness of about 0.5 microns and then doped with phosphorous to increase electrical conductivity.

Referring to FIG. 9, a first polycrystalline layer 40 is contoured by reactive ion etching to form a floating polysilicon gate region on the second side of tunnel oxide 24 and tunnel implant 6. It will be done. A brief exposure to a moist fluoride etch removes all of the first gate oxide layer 23 except for the portions protected by the first polycrystalline silicon region 40.

In FIG. 10, a second gate oxide 27 is grown by high temperature thermal oxidation. This second gate oxide is
Above the monocrystalline silicon substrate and the first polycrystalline gate region 4
grown on o. An N-type implantation is performed through the second gate oxide 27 to form a single dip region suitable as a location for a MOS transistor with the desired limiting voltage. Approximately 1011 atoms/sq.c.
The same implantation of m is used for both N-channel and P-channel Mos transistors.

A second polycrystalline silicon layer 41 is then deposited over the entire surface, as shown in FIG. This second polycrystalline layer 41
A full oxide layer is deposited over one or more regions 28 as a mask for a subsequent heavy phosphorus doping step.
patterned to form a This doping step tops polysilicon layer 41 except in the regions under mask oxide 28. The undoped region of layer 41 then acts as a high value resistor to the static RAM portion of the integrated circuit.

Referring to FIG. 12, a patterned layer of photoresist 36 is provided as a mask for patterning the second polycrystalline layer 41. Referring to FIG. This layer requires a tolerance of about 0.1 microns, so the patterning is done by reactive ion etching.

In FIG. 13, a patterned photoresist layer 37 is formed and used to locate a bulk N-type ion implantation and a heavily doped N-type ion implant for an N-channel MO5)-lancisor. A source-drain region 8 is formed. This source-drain region has a sheet resistivity on the order of 20 ohms/square.

Referring to FIG. 14, the N+ source-drain mask is stripped and replaced with a new patterned photoresist layer 38, which acts as a mask for the P- type ion implantation. This implantation forms a P+ source-drain region 9 for a P-channel transistor. After this implantation, a short oxidation cycle is performed to anneal both front implants.

In FIG. 15, a layer 29 of phosphorous-doped low-temperature deposited oxide (LTO) is deposited over the surface, which is etched through the 660 holes formed by reactive ion etching using the photoresist layer 39 as a mask. , are patterned to contact one or more predetermined N0 regions 8.

The high temperature treatment after etching reflows the phosphorous-doped glass and flattens the edges of the steps resulting from the multiple layers of material on the substrate 1.

In FIG. 16, a further patterned photoresist layer 49 is provided which acts as an etch mask for providing one or more holes 70 by which the desired P regions are contacted. be able to. In a common photoresist masking step, the N0 and P00 contact holes can be provided, but the separate steps shown allow for looser tolerances and automatically dope the P00 contacts during the reflow heat treatment. prevent the

FIG. 17 shows the integrated circuit produced in accordance with the preferred embodiment. After removing the photoresist layer 49,
Aluminum containing about 1% silicon is deposited and etched using a reactive ion etch using a photoresist mask (not shown) to form conductive regions 80.

The various regions formed by the above steps are used for the EEPROM, SRAM, N
Combined to form the MO8 and PMO8 parts.

Although the invention has been described in terms of preferred embodiments thereof, those skilled in the art will recognize that various modifications may be made without departing from the spirit and scope of the invention.

[Brief explanation of the drawing]

1 is a diagram illustrating the starting substrate used in the method of the invention and some of the treatments carried out on it; FIG. 2 shows another oxide layer, a silicon nitride layer and FIG. 3 is a diagram showing how a photoresist layer is formed and ion implantation is performed; FIG. 3 is a diagram showing how another layer of photoresist 1 is patterned and ion implantation is performed; 5 shows the stripping of the photoresist layer to provide a field oxide layer, FIG. 5 shows the provision of a first gate oxide layer, and FIG. FIG. 7 is a diagram showing the growth of a tunnel oxide; FIG. 7 is a diagram showing phosphorus ion implantation to form a strongly toped N+ region; FIG. FIG. 9 is a diagram illustrating the deposition of a first polycrystalline silicon layer by reactive ion etching to form a floating polycrystalline gate region; FIG. 10 shows the growth of the second gate oxide, FIG. 11 shows the formation of the second gate oxide region, and FIG. 12 shows the growth of the second gate oxide region. Figure 13 illustrates the use of yet another photoresist; Figure 13 illustrates the formation of a heavily doped source-train region; Figure 14 illustrates the use of yet another photoresist to pattern P;
- type ion implantation to form a P source-drain region; FIG. This is a diagram showing what is done. FIG. 16 is a diagram showing the formation of a hole for contacting the desired P1 region, and FIG. 17 is a diagram showing the completed integrated circuit. DESCRIPTION OF SYMBOLS 1...Substrate 2...N-region 12...Buried contact area 20...Oxide layer 30...Photoresist 1 layer 21
...Oxide layer 22...Field oxide layer 23...Gate oxide 25...Silicon nitride layer 26...Tunnel oxide 27...Second gate oxide region 28... Mask oxide 29...Low temperature deposited oxide layer 32 doped with phosphorus...
Resist layer 40...First polycrystalline layer 41...Second polycrystalline silicon layer 80...Continued from page 1 ■Int, C1,' Identification code Internal reference number H01L
29/78 7514-5F @ inventor Richard
Mba United States of America Setsuki West 9 0 Inventor Richard Digi United States of America West Heart Oregon 97005 Beaverton Saradowind 15285 Oregon 97007 Aloha South Road 1
8680 Commissioner of the Patent Office 1, Indication of the case Patent Application No. 32551 of 1985? 1
Title of the invention General-purpose MO3 integrated circuit and its manufacturing method 3
, Relationship with the case of the person making the amendment Applicant 4 agent

Claims (11)

[Claims] (1) A first patterned polycrystalline silicon layer constituting the floating gate of the EEPROM device, with a portion overlying the first polycrystalline silicon layer;
A CMO8 integrated circuit comprising, in combination, a second patterned layer of polycrystalline silicon such as to constitute the gate of a MOS transistor. (2) The CM according to claim (1), wherein the second polycrystalline layer further includes a large resistance element.
O8 integrated circuit. (3) A CMO8 integrated circuit comprising at least one EEPROM element, at least one pair of CMOS transistors, and at least one large value polycrystalline silicon resistive load element. (4) A plurality of DR'AM elements consisting of CMO3I-transistors forming a memory array and the selected DR'AM elements;
A CMO8 integrated circuit comprising a plurality of EEPROM element means used to selectively disconnect AM elements from said array. (5) Floating gate I of the above EEPROM element
and a second patterned polycrystalline silicon layer partially overlying the first patterned polycrystalline silicon layer. , this second layer is ``1 DRAM
A CMO8 integrated circuit according to claim 4, which constitutes a gate of an element. (6) A method for forming a CMO5 integrated circuit comprising an EEPROM element and a CMOi transistor on a substrate, comprising depositing a first polycrystalline silicon layer on the substrate. patterning the first layer to define a floating gate of the EEPROM device; depositing a second polysilicon layer over the substrate and the first polysilicon layer; A method comprising patterning the second layer so as to constitute the second layer. (7) The method according to claim (6), wherein an embedded N1 layer is formed in the substrate for use as a connector passing underneath. (8) depositing a doped glass layer over the first and second polycrystalline layers, forming holes in the glass layer for contacting some, but not all, of the CMOS transistors; 7. A method as claimed in claim 6, in which the glass layer is poured again and then another hole is formed in the glass layer. (9) In a method for forming a CMO8 integrated circuit on a silicon substrate, a first region of P- type conductivity is formed on the substrate, and the P-
A first region of N-type conductivity type adjacent to the first region of P-type conductivity type is formed on the substrate, and a second region of N-type conductivity type adjacent to the first region of P-type conductivity type is formed on the substrate. formed in the substrate, the second region being more heavily doped than the first region of N-type conductivity, and further doped with the first region of P-type conductivity and the first and second regions of N-type conductivity. A method comprising growing a common field oxide layer over the second region. (10) The second region of N-type conductivity type is formed after growing a field oxide layer on the first region of p-type conductivity type and the first region of N-type conductivity type. A method according to claim (9). (11) forming a first polycrystalline layer on a substrate, patterning the polycrystalline layer to form a floating gate, and forming a second polycrystalline layer on the first polycrystalline layer; , and patterning the second layer to form a CMO8I transistor gate and a large value resistor.