JPS6024735A - Receiver - Google Patents

Receiver

Info

Publication number
JPS6024735A
JPS6024735A JP13086383A JP13086383A JPS6024735A JP S6024735 A JPS6024735 A JP S6024735A JP 13086383 A JP13086383 A JP 13086383A JP 13086383 A JP13086383 A JP 13086383A JP S6024735 A JPS6024735 A JP S6024735A
Authority
JP
Japan
Prior art keywords
frequency
digital filter
memory
receiver
pass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13086383A
Other languages
Japanese (ja)
Inventor
Shigeharu Takamatsu
高松 重治
Masaomi Suzuki
鈴木 雅臣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AKIYUFUEEZU KK
Original Assignee
AKIYUFUEEZU KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AKIYUFUEEZU KK filed Critical AKIYUFUEEZU KK
Priority to JP13086383A priority Critical patent/JPS6024735A/en
Publication of JPS6024735A publication Critical patent/JPS6024735A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/10Means associated with receiver for limiting or suppressing noise or interference

Abstract

PURPOSE:To enable multi-pass distortion suppression process at the time of channel selection by storing beforehand multi-pass retaining information correspond to a received frequency in a memory. CONSTITUTION:The memory 6 stores information on multi-pass distortion components through the receiving portion 2 and a frequency designing signals through a central operation processor 4. According to this information, the central operation processor 4 calculates filtering characteristics which are to cancel multi-pass distortion components, and controls the digital filter 3. Since this information is handled depending upon the frequency of the frequency designating signal, this receiver can control the digital filter 3 so that multi-pass can be reduced as much as possible depending upon the received frequency.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は受け機に係シ、特に、マルチノにス歪を自動的
に低減させるようにしたものに関する。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to receivers, and particularly to receivers that automatically reduce Martino distortion.

(従来技術) 近年、オーディオ用FM受1g機においてはデジタルフ
ィルタ?用いたものが提案さt)、ている。
(Prior art) In recent years, digital filters have been used in audio FM receivers. The one used is proposed t).

この型式の受信機においてはデジタルフィルタの特注(
周波数特性1位相特注)を変化させることにニジマルチ
、oス歪を抑圧させることができるが、マイクロコンピ
ュータ−等によるリアルタイム処理で上記抑圧制御を行
なわせる場合には受信波の変調状態、 A/Dコンバー
ターの処理速度、マイクロコンピュータ−の処理速度等
に限界があるために、選局後直ちにはマルチAス歪を抑
制することができず、正常な受信状態になるまでにタイ
ムラグが生ずるという欠点があった。
This type of receiver requires a custom-made digital filter (
Rainbow multi and OS distortion can be suppressed by changing the frequency characteristics (1 phase (custom-made)), but when performing the above suppression control using real-time processing using a microcomputer, etc., the modulation state of the received wave, the A/D Due to limitations in converter processing speed, microcomputer processing speed, etc., multi-A distortion cannot be suppressed immediately after tuning, and there is a time lag before normal reception is achieved. there were.

(発明の目的) 本発明の目的は、上記した従来のものの欠点を解消し1
選局と同時に適確なマルチAス歪抑制処理ができるよう
にした受信機を提供することにある。
(Object of the invention) The object of the present invention is to solve the above-mentioned drawbacks of the conventional ones.
It is an object of the present invention to provide a receiver capable of performing accurate multi-A distortion suppression processing at the same time as channel selection.

(発明の構成) 本発唱に係る受信機はフロントエンドとIP段との間に
介挿されたデジタルフィルタと、上記IF段及びその後
段の回路からのマルチパス歪成分を除去するLうに上記
デジタルフィルタの周波数特性及び位相特性を制御する
ための中央演算部と、制御データを収納するためのメモ
リーとを備え、上記中央演算部は、受信周波数制御部か
らの周波数指定は号に応じて上記デジタルフィルタを上
記マルチノぞス歪が最低となるようなフィルタ特性に制
御できるように構成されている。
(Structure of the Invention) The receiver according to the present invention includes a digital filter inserted between the front end and the IP stage, and a digital filter that removes multipath distortion components from the IF stage and the subsequent circuit. The central processing section is equipped with a central processing section for controlling the frequency characteristics and phase characteristics of the digital filter, and a memory for storing control data, and the central processing section receives the frequency specification from the reception frequency control section according to the The digital filter is configured to be able to control the filter characteristics such that the multi-noise distortion is minimized.

(実施例) 本発明の実施例を図面に基づいて説明する。(Example) Embodiments of the present invention will be described based on the drawings.

図中、1はフロントエンド、2はIF増幅器。In the figure, 1 is a front end and 2 is an IF amplifier.

FM検波器等の受信部、3は該受は部と上記フロントエ
ンド1との間に介挿されたデジタルフィルタ、4は該デ
ジタルフィルタ3を制御するための中央演算部、5は周
波数制御部であって。
A receiving section such as an FM detector, 3 a digital filter inserted between the receiving section and the front end 1, 4 a central processing section for controlling the digital filter 3, and 5 a frequency control section. And.

フロントエンド1の同調周波数?制御部゛ると共に上記
中央演算部4へ周波数指示信号を送出する工うになって
いる。6はメモリーであって。
Tuning frequency of front end 1? It is designed to send a frequency instruction signal to the central processing section 4 as well as a control section. 6 is memory.

書き込み、読み出しができるRAM(ランダムアクセス
メモリー)が用いられている。
A RAM (random access memory) that can be written to and read from is used.

上記メモリー6には受IS部2からのマルチ・ξス歪成
分に関する情報と周波数指示信号に関する情報とが夫々
中央演算部4?介して入力されるようになっている。中
央演算部4においてはこれらの情報に基づいてマルチパ
ス歪成分を相殺すべきフィルタリング特性を算出し、上
記デジタルフィルタ3を制御する。また、この情報は周
波数指示信号の周波数に対応して処理されるようになっ
ているため、受信周波数に応じて最もマルチパスが少な
くなるLうにデジタルフィルタ3が制御されるようにな
っている。デジタルフィルタ3?制御すべきシーケンス
はメモリー6に収容されるようになっており、受信周波
数に応じて自動的に読み出されてマルチ・ξス歪が直ち
に低減されるよう機能する。
The memory 6 stores information regarding the multi-ξ distortion components from the receiving IS section 2 and information regarding the frequency instruction signal from the central processing section 4, respectively. It is now entered via the The central processing unit 4 calculates filtering characteristics for canceling multipath distortion components based on this information, and controls the digital filter 3. Further, since this information is processed in accordance with the frequency of the frequency instruction signal, the digital filter 3 is controlled in accordance with the reception frequency to minimize the number of multipaths. Digital filter 3? The sequence to be controlled is stored in the memory 6, and is automatically read out depending on the receiving frequency, so that the multi-ξ-s distortion can be immediately reduced.

実施例においては、上記メモリー6は記憶された制i哩
データが選局後の受け状態に対応して自動的に新たなデ
ータに更新されるようになっていると共に記憶された制
御データが選局後の受信状態に対応しけなくなった際に
は自動的にクリヤ状態となる工うVこなっている。
In the embodiment, the memory 6 is configured such that the stored control data is automatically updated to new data in accordance with the reception state after tuning, and the stored control data is When it is no longer possible to cope with the reception state after a station, the clear state is automatically established.

(発明の効果) 本発明に係る受1g機によれば、メモリーに。(Effect of the invention) According to the receiver 1g machine according to the present invention, in the memory.

受信周波数に対応させたマルチ/々ス抑制情報を予め記
憶させるようにしたから1選局後直ちにマルチ/ミスを
抑制することができ、タイムラグを・生ずることはない
。したがって、従来のものの工うに選局毎に不快な歪が
発生したりする虞はなく、常に快適な受信2行うことが
できる。
Since the multi/pass suppression information corresponding to the receiving frequency is stored in advance, multi/mistakes can be suppressed immediately after selecting one station, and no time lag occurs. Therefore, there is no possibility that unpleasant distortion will occur every time a channel is selected, unlike the conventional method, and comfortable reception 2 can always be performed.

【図面の簡単な説明】[Brief explanation of drawings]

図面は本発明に係る受[8機の実施例を示すブロック図
である。 1:フロントエンド、2:受信部、3、デジタルフィル
タ、4:中央演算部、5:周波数制御部 特許出願人 アキュフエーズ株式会社
The drawing is a block diagram showing an embodiment of the receiver according to the present invention. 1: Front end, 2: Receiving section, 3: Digital filter, 4: Central processing section, 5: Frequency control section Patent applicant Accuphase Co., Ltd.

Claims (1)

【特許請求の範囲】 1、 フロントエンドとIP段との間に介挿されたデジ
タルフィルタと、上記IP段及びその後段の回路からの
マルチ/ぐス歪成分を除去するように上記デジタルフィ
ルタの周波数特性及び位相特性を制御するための中央演
算部と。 制御データを収納するためのメモリーとを備え、上記中
央演算部は、受信周波数制御部〃)らの周波数指定1言
号に応じて上記デジタルフィルタを上記マルチAス歪が
最低となるようなフィルタ特注に制御するように構成さ
れていることを特徴とする受信機 2、 上記メモリーは、記憶された制御データが選局後
の受信状態に対応して自動的に新たなデータに更新され
るようになっていることを特徴とする特許請求の範囲第
1項記載の受信機 3、 上記メモリーは、記憶された制御データが実際の
受信状態に対応し寿なくなった際には自動的にクリヤ状
態に設定される工うKなっていることを特徴とする特許
請求の範囲第1項記載の受信機
[Claims] 1. A digital filter interposed between the front end and the IP stage, and a digital filter configured to remove multi-signal distortion components from the IP stage and the subsequent circuit. and a central processing unit for controlling frequency characteristics and phase characteristics. and a memory for storing control data, and the central processing unit controls the digital filter in accordance with one frequency designation word from the reception frequency control unit () so that the multi-A distortion is minimized. The receiver 2 is characterized in that it is configured to perform custom control, and the memory is configured such that the stored control data is automatically updated to new data in accordance with the reception state after tuning. The receiver 3 according to claim 1, characterized in that the memory is configured to automatically clear the stored control data when it corresponds to the actual reception state and reaches the end of its life. The receiver according to claim 1, wherein the receiver is set to K.
JP13086383A 1983-07-20 1983-07-20 Receiver Pending JPS6024735A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13086383A JPS6024735A (en) 1983-07-20 1983-07-20 Receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13086383A JPS6024735A (en) 1983-07-20 1983-07-20 Receiver

Publications (1)

Publication Number Publication Date
JPS6024735A true JPS6024735A (en) 1985-02-07

Family

ID=15044458

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13086383A Pending JPS6024735A (en) 1983-07-20 1983-07-20 Receiver

Country Status (1)

Country Link
JP (1) JPS6024735A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62203629A (en) * 1986-02-24 1987-09-08 シーエムビー フ―ドキャン ピーエルシー Method for molding integral molded can body having reinforcing radius and/or stacking pleat
JPS6432329U (en) * 1987-08-19 1989-02-28
JPH0198326A (en) * 1987-10-09 1989-04-17 Alpine Electron Inc Am radio receiver

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55147883A (en) * 1979-05-08 1980-11-18 Sony Corp Disturbing wave elimination unit
JPS55162635A (en) * 1979-06-05 1980-12-18 Toshiba Corp Rejector for multiplex propagation distortion

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55147883A (en) * 1979-05-08 1980-11-18 Sony Corp Disturbing wave elimination unit
JPS55162635A (en) * 1979-06-05 1980-12-18 Toshiba Corp Rejector for multiplex propagation distortion

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62203629A (en) * 1986-02-24 1987-09-08 シーエムビー フ―ドキャン ピーエルシー Method for molding integral molded can body having reinforcing radius and/or stacking pleat
JPH0378167B2 (en) * 1986-02-24 1991-12-12 Cmb Foodcan Plc
JPS6432329U (en) * 1987-08-19 1989-02-28
JPH0511136Y2 (en) * 1987-08-19 1993-03-18
JPH0198326A (en) * 1987-10-09 1989-04-17 Alpine Electron Inc Am radio receiver

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