JPS60247211A - Focus detector - Google Patents

Abstract

PURPOSE:To permit detection with good accuracy in a fine unit below the pitch of the cells in two photodetecting means by using the prescribed values determined from the output signals corresponding to the respective cells to determine an inter-image spacing. CONSTITUTION:The output signals corresponding to the respective cells of a standard part L for one line sensor are successively designated as l1-lk and the output signals corresponding to the respective cells of a reference part R for the other sensor are successively designated as r1-rm (k<m). The values A, B and C are determined by using the equation 1 when the output signal trains of the reference part R having the highest degree of coincidence with the signal trains l1-lk are designated as rq+1-rq+k. The spacing between the images on both photodetecting means is determined by using the values A-C.

Description

TECHNICAL FIELD The present invention relates to a focus detection device for a camera that detects the focus state of a photographic lens by receiving object light that has passed through a photographic lens.

Prior Art The first lens of the photographic lens is symmetrical to the optical axis.
The object light beams that have passed through the first and second regions are respectively re-imaged to create two images, and the mutual positional relationship of these two images is determined to determine the amount of deviation of the image forming position from the expected focal position and its deviation. A focus detection device has already been proposed that determines the direction (whether the imaging position is in front of or behind the intended focus position, that is, whether the focus is in front or behind). The optical system of such a focus detection device has a configuration as shown in FIG.
This optical system has a planned focal plane (4) behind the photographic lens (2).
) or a condenser lens (6) further rearward from this surface, and a reimaging lens (8) further rearward thereof.
> , (lo), and on the imaging surface of each re-imaging lens there is a line sensor (1
2) and (14) are arranged. Each line sensor (12)
, (14) As shown in Fig. 2, in the case of so-called front focusing, in which the image of the object to be focused is formed in front of the intended focal plane, the images above are close to the optical axis (18) and are reciprocal. On the other hand, in the case of rear focus, they become far from the optical axis (18). When the focus I is aligned, the distance between two corresponding points of the two images is a specific distance defined by the configuration of the optical system of the focus detection device. Therefore, in principle, the focus state can be determined by detecting the distance between the two images.

However, even if the correlation between both sensors (12) and (14) is simply calculated for each cell, for example, the pisochi of the cell is 30
If μ, an error of about 30 μ will occur in detecting the image interval. If this error is converted into a defocus amount, for example, 1
The amount is about mm, which is an amount that poses a practical problem for an eye-catching camera.

Purpose The present invention has been made in view of the above-mentioned drawbacks,
The purpose is to provide a focus detection device that is capable of accurately detecting the image interval in units of cells (below cell resolution).

(Margin below) dog Jift FIG. 3 is a front view of a sensor according to an embodiment of the present invention.

In this embodiment, the two line sensors are replaced by using two different areas of one line sensor. In FIG. 3, (X) indicates the position through which the optical axis of the photographic lens passes. Outputs of pixels near the optical axis passing position (X) are not used.

(1,) to (+23) indicate pixels in the reference part (L) corresponding to one line sensor, and the reference part (L) is the first block (1) of pixels (11) to (Ls). , pixel (1)
The second block (II) of ~(1□3) and the pixel (18
) to (+23), the third block (III). 1st and 3rd block (1) (II
[) have 16 pixels each, and the second block (I
I) has 23 pixels. A monitoring light receiving element for monitoring the illuminance on the pixel is provided above the reference part (L).

(r,) to (r3.) indicate pixels in the reference section (R) corresponding to the other line sensor. The number of pixels in the reference part (R) is 31, and the number of pixels in the reference part (L) is 23.
more than Then, the pixel (11) located at the farthest position from the optical axis passing position (X) of the reference part (L) and the reference part (
The pixel (R) located closest to the optical axis passing position (X)
Let the distance from rI) be ri. Furthermore, when the photographic lens is in focus on the planned focal plane, the outside is the pixel (l I )-(12
3) The image above shows pixels (r5)-(r27) of the reference part (R).
) corresponds to the image above. This pixel (r5) ~ (
r2. ) is the focused block (F) in the reference part (R), and the pixel (++□) at the center of the second block (II) in the reference part (L) and the focused block (F) in the reference part (R) )
Let L2 be the separation from the pixel (r3.) at the center of the image, that is, the image interval at the time of focus detection.

FIG. 4 shows a part of the circuit of this embodiment. In particular, data is read from the sensor shown in FIG.
The circuit block (A) in which the correlation between the block (II) and the reference part (R) is detected is mainly shown. In Figure 4, (
Se) indicates the ICCD line sensor as shown in Fig. 3,
The integral data of each pixel is sequentially converted into a digital quantity by an AD conversion circuit (20).

This situation is shown in the 70-chart in Figure 5. First,
When the AF switch is closed in step S1, the photocurrent flowing through each pixel of the sensor (S e) is integrated in step S2, and the integral data of each pixel is summarized in step S3. The integral data of the pixels are sequentially digitized by the AD conversion circuit (20). Letting this integral data be Si in order, the comparison circuit in Fig. 4 (
22), each integral data Si is set to a predetermined constant a
It is detected whether the value is greater than 1 or not. If any one of the total integral data Si is larger than the constant a1, a flag (Fl) is set and its output becomes "1". Conversely, the flag (F +) is not set only when all the integral data Si are smaller than the constant a,
The output remains O''. (Ijl & 5 Figure Stage Step S5) In other words, the comparison circuit (22) and the flag (F,) are a brightness level detection means for determining whether the subject brightness level is equal to or higher than a predetermined value. If even one of all pixels has a luminance level equal to or higher than a predetermined value, it is determined that there is sufficient luminance for focus detection, and a flag (F,) is set.

Furthermore, the integral data Si is stored in a memory circuit (RAM) (
24) and each pixel (11) to (+23)(r
, ) to (r3.), respectively. (Step S in Fig. 5?) After that, the integral data corresponding to each pixel (1) to (I2a)b, ) to (r,) are sequentially 1.1□, . . .
+23, r3, r2, ..., r31. The arithmetic circuit (26) performs the following calculation using each data.

(Figure 5 Step 5a) H2 (N) = Month 1 l L -rHl 10 l L3-r
H+22 l 1 However, here, the subscript H2 (N) indicates that the second block (n) of the reference part (L) is used, and N = 1.2, ..., 9. . To explain the above calculation in more detail using Vl, first, when N=1, 7
- H2(1)=+I l+-r+ l +l 12-r2
1 1113-r+ l +・=+I l□2-r2□
l +FI h:+-r231 (2). In other words, this is the absolute value of the output difference between pixels (11) and (r,), the absolute value of the output difference between (1□) and (r2), ..., the absolute value of the output difference between pixels (+2-) and This means that the absolute value of the output difference with (r23) is calculated, the values at both ends are each halved, and the total sum is calculated.

Next, when N=2, H2(2)=+l II-r21 + I l□-rs
I +l 1+-r4 I +・=+l I2□-r
z* l +FI 12a-r2n I・・・・・・(
3) is calculated. This is (11), (r2), (12)
From the case of H2(1), the pixels of the second block (
11) to (lz*) are shifted to the right by one pixel with respect to the reference portion (R), the correlation between each pixel is calculated, only both ends are halved, and the total sum is calculated. Below, N=3
．． 4.5, . . . 8- . . . , and 9, the pixel columns of the second block (II) are moved 2.
3.4,..., this means that the correlation has been established by shifting by 8 pixels. Here, if H2(N) is called the comparison data and N is called the shift amount, the above calculation shows that when the amount to shift the second block (II) is 0 pixels (N=1) to 8 pixels ( Nine types of comparison data (up to N = 9) can be viewed. This comparison data becomes zero when the images on both pixel columns to be compared are completely equal to each other, and increases in value as the image shift increases.

The reason why the absolute value of the output difference at both ends of the pixel row is halved in the calculation of equation (1) is that the term is the comparison data H2 (N
) is to reduce the influence on the other terms to half that of other terms. This will be explained in detail later.

The comparison data H2(N) calculated by the calculation circuit (26) is stored in the memory circuit (28) together with the shift amount N. (N=1.2,...,9) Then, the minimum value detection circuit (30) collects nine comparison data H2(N
) that takes the minimum value is detected.

The comparison data that takes this minimum value is defined as H2(n), and N at that time is defined as the minimum shift amount n. (n is 1.2,
..., any of 9) This minimum comparison data H2 (
n) is stored in the memory circuit (32) together with the minimum shift amount n. (Step S9 in FIG. 5) Next, the memory circuit (24) stores integral data 11.12, "・"' + 23, rtq r2, . . . corresponding to each memorized pixel.
..., r3. Based on the minimum comparison data H2(n) and the minimum shift amount n stored in the memory circuit (32), the calculation circuit (34) performs the following calculation. (Step S5 in FIG. 5.) Q This is a calculation to further improve the detection accuracy of the image interval. For example, now, the shift amount N and the comparison data H2 (N
) are in the light-weight relationship shown in Figure 6.

Then, the minimum comparison data Hz(n) is H2(3), and the minimum shift amount n is 3. However, the actual comparison data H2(N) may change and become 1 as shown by the dotted line in the figure. In that case, if the image interval is detected using n"3 (1), an error will occur. In other words, if the minimum shift amount n is used as is to detect the image interval, the unit will be the pitch between pixels, and Finer precision cannot be obtained.The precision can be improved by reducing the pitch between the S systems, but there is a limit to this in terms of CCD manufacturing.

Therefore, in this embodiment, we found a case where the comparison data becomes even smaller than the minimum comparison data Hz(n) between n-1 and n and between n and n+1.
The image interval can be detected in units finer than the pixel pitch.

The calculations of equations (4) and (5) will be explained in more detail below. now. As an example, when N=3, the comparison data H
Suppose that 2(N) is the minimum. Therefore, the minimum comparison data is H2(3) and n=3.

Based on equation (1), H2(3) is: H2(3)=+I L-r3I +12-r<l
++ 13-rz 1 +・=+ I 122-r2
41 + F l hs r2s l... (6
) 11- becomes. On the other hand, when calculating equation (4), h2(2)=
112-r+ I + 113-r4 + +...
++ 123- r24I ...... (7) is calculated and formula (5) is calculated, h2 (4)" I II-r41 + 112-rz
1 +”・+112□−r2,1 ・・・・・・(8)
I get criticized. Comparing each term in equation (6) and equations (7) and (8), we find that if we ignore the terms at both ends of equation (6), (
7) According to equation (8), the shift amount is n-1 (i.e. 2)
Comparison data 112(2) in case of and shift amount is n+1(
In other words, it can be seen that the comparison data h2(4) in case 4) was condemned. However, in equations (7) and (8), the values of the terms at both ends are not halved, but the number of terms is reduced by one compared to equation (6).

Therefore, h2 (3) and (7) (8
h2(2) and h2(4) calculated by the formula ') are on the same scale, and their magnitudes can be directly compared without multiplying them by coefficients.

12- Next, we will explain the reason for using h2(n 1), h, , (n+1) to obtain a value of comparison data that is even smaller than H2(n), based on the graph in Figure 7. do. In the graph, the horizontal axis indicates the pixel number k, and the vertical axis indicates the output signal of that pixel. The line (al) is the pixel (It
)-(+23)+7) output signal, and line (a2) represents pixels (11) to 12. ) shows the output signal t t+22 of the pixels (r ) to b ) which receive the image having the highest correlation with the image above. (t=1.2,...,9) On the other hand, line (a3) shows the output signal of pixels "t+1) to (rt+1+22)", and line (a,) shows the output signal of pixel "t+1) to (rt+1+22)" ~(rt
-1+22) output signal is shown. Now, as an example, images on pixels (11) to (123) and pixels (rz) to (r27)
) has the highest correlation with the image above, t=5, and the broken line (a2) indicates the output signal of the pixel (rz) to b=, ).

Here, the output signals of pixels (1,) to (+23) and the pixel (
The correlation degree ■(1) with the output signal of rl) to (r2=) is
I (1)=I It-r+ l ++ I□-rz
I +-+3 I 123-r2a I = Σ11 to -rk1...
...(9)k=1. Next, when the pixel row of the reference part (R) is shifted by one pixel, the correlation degree I(2) is as follows. Similarly, (3) to (9) can be considered. As described above, it is assumed that the correlation degree ■(5) between pixels (1) to (1□3) and pixels (r5) to (rz.) is the highest. This (5) corresponds to the area surrounded by lines (α1) and (α2) in the section of k=1 to 23.

Next, considering ■(4), we have the following, which means that the line ((Z
, ) and (a,) correspond to the area 81 surrounded by.

On the other hand, ■(6) is, which means that the line (a,
) and (a,).

By the way, it is clear from the graph that the areas S1 and 82
are not equal. In addition, in the interval k=1 to 23, #! Icc
If I , )(ff 2)(ff , )(04) are all straight lines, areas 81 and 82 will be equal to each other. but,
Generally, it is considered that such a straight image is rarely received. Therefore, it is generally considered that the areas 81 and 82 are not equal in most cases. Incidentally, the areas of Sl and 82 are generally not equal because the relationship between the image on the reference part that can be correlated with the standard part is k (9) and I (10).
This is because it is different in the interval from =1 to 3 and the interval from =21 to 23.

Therefore, from the area 81, remove the surface *S 3 of the part sandwiched between the lines (al) and (a3) in the section = 1 to 2, and from the area 82, in the section = 22-23, line (a , ) and (a4) excluding the area 84, it can be seen from the graph that 8l-83=S2-84 (13) holds true. Here, S + -8
3 is 15-3 S + '-S a =ΣIIk-r, 31 town-(1
4) k=2 2 S 2-84 = kZ, +5f to 1' ・Old ・-(
15).

When the lines (α, ) and (α2) overlap, equation (13) holds true as discussed above, but does not hold when they do not overlap. However, in the case where lines (a,) and (a2) do not overlap, the difference between equations (14) and (15) There is a tendency that the discrepancy between the two values shown by the formula is weaker. In other words, the consistency of the latter is stronger.

When the image of one block of the standard part is compared with the image of the reference part, and the correlation between the two is highest at a certain contrast number, the contrast results of the contrasts before and after that pixel by one pitch agree with each other. If one expects this to be true, it is preferable to use the values of equations (14) and (15) in place of the values of equations (11) and (12) as information for detecting the focal position.

From this consideration, in the final 16-step process of detecting the focus position, the correlation is the worst and the contrast pixel 1
As the comparison results before and after by the pitch, (14), (15
) Adopt a value with the content shown in the formula.

Regarding the second block, if the minimum comparison data H2(n) is obtained with the minimum shift amount n, then the n-1st and n+1st comparison results are h2(n-1), h2(n+
1), then h2(n+1)=
1+2 r l + 112 'n+1' ten...+
11□3-r 1 n+21 3 = Σ"k' + n-2' ...... (16) k
=2 L(n+1)= l It -rn+1' +112
r , +21 +''+1122-r 1 n+22 , and these are used as information for determining the focus detection position.

Here, looking at the comparison shown in equations (9) and (10), the right-hand side of each equation consists of 23 terms. On the other hand, looking at equations (16) and (17), the right side of each equation consists of 22 terms. In other words, there is a difference of one term in the number of terms between the former and the latter.

Showing equation (9) again, ! (1) = l I, -rl l +112-r2
l +-...+1123 r231 However, considering the formula I' (1) in which the weight of the first and last term on the right side of this formula is halved relative to other terms, I' (1) “F I L rl l + + +2
r21 +-+ l Its rlsl ++l 12
3 r2:+l −”・(18) In this way, (
On the right side of equation 18), the combined weight of the first term and the last term is 1, which can be calculated by considering that there are a total of 22 terms with a weight of 1. Therefore, the information with the highest degree of coincidence is shown as information for determining the focal position. As a method of calculating the comparison result, we will use the calculation method shown in equation (18) instead of the calculation method shown in equation (9).

In this way, calculations shown by the following equations are performed for the first, second, and third procs, respectively.

H+(N)=' (l It-rN+8' + I
1.5-rN+23' )5 +Σ''k-rk+n+7'=2...(19) However, N=1.2,...8, H2(N)=
'(I l+ rHl + 1123-rN+22'
12 +Σ"k-rk+N+1'=2...(20) However, N=1.2,...,919-2+Σ"k-rk+N-8'=9 ......(21) However, N=1.2, ..., 8.

Various cases can be considered regarding the magnitude relationship between the minimum comparison data H2(n) and hz(n-1) and hz(n+1) determined by equations (4) and (5). However, hz(n-1), hz(
n+1)≧H2(n). These various cases are shown in FIG. 8 as (a), (b), (e), and (d). In Figure 8,
The horizontal axis shows the shift amount (N), and the vertical axis shows the values of H2(N), hz(n-1), and hz(n+1). FIG. 8(a) shows the case where hz(n-1)=h2(n+1), and in this case, it is recognized that H2(n) is truly the minimum. FIG. 8(b) shows hz(n −1)
The case of <h□(n+1) is shown, in which case the true minimum comparison data is between n-1 and n.

FIG. 8(e) shows hz(n 1 )> H2(n)=h
2(n+1), in which the true minimum comparison data exists between n and n+1. In Fig. 8(d), hz(n 1 )>hz(n+1
), in which the true minimum comparison data is between n and n+1. However, although FIG. 8 shows an ideal state and the true minimum comparison data is shown to be zero, in reality it does not become zero due to lens aberrations and the like. Further, when two minimum values of comparison data are detected as shown in FIG. 8(C), the comparison data with smaller n is always determined as the minimum comparison data. Therefore, Hz(n
) = hz(n 1 ) does not exist.

Returning to FIG. 4, the arithmetic circuit (34) calculates, (
The data of n-1) and hz(n+1) are input to the memory circuit (36) and stored in memory. Memory circuit (32
), and hz(n-1) and hz(
The data of n+1) is input to the arithmetic circuit (38), and the following arithmetic operation is performed. (Step S in Figure 5) Y2=H2(n) l'"" l ......(22) This formula calculates the comparison data H2(N ) is calculated by adding the value Y2. This value Y2 is called the minimum peak value. The subscript indicates detection using the second block (II).

How to calculate the minimum peak value Y2 will be explained using FIG. 9.

As shown in FIG. 9, when the horizontal axis is the shift amount n and the vertical axis is the comparison data value, the point D1 corresponding to the minimum comparison data
The coordinates of are denoted by (n, H2(n)) and F2(n i
) The coordinates of point D2 corresponding to (n-1, F2(n 1
>) and corresponds to F2(n+1).

The coordinates of are indicated as (n+1, F2(n+1)). A straight line connecting points D1 and D2 is calculated using the coordinates of both points, and it is assumed that there is a peak P that lies on this straight line F1. On the other hand, it is assumed that a straight line L2 connecting point P and point D3 has a slope equal to and opposite in sign to the straight line L2.

Then, the minimum peak value Y2 is determined as the coordinate of the intersection of these two straight lines L1 and F2. Returning to FIG. 4, the minimum peak value Y2 thus determined is stored in the memory circuit (40). This minimum peak value Y2 is
This is used to determine whether the minimum comparison data H2(n) detected using the second block (n) is reliable.

Furthermore, in this embodiment, in order to determine whether the minimum comparison data (n) detected using the second block (II) is reliable, the contrast of the image on the second block (U) is Detected. (42) indicates a contrast detection circuit, in which a contrast value C2 is calculated as the sum of output differences between two adjacent pixels in the second block (II) of the reference section (L). (Figure 5 Step 81
2) That is, 2 C2=ΣNk'+1'...(23)k=
It is 1. The subscript indicates a value related to the second block (II). The calculated contrast value C223- is stored in the memory circuit (44). Memory circuit (
The contrast value C2 stored in step 44) is also used to determine whether the contrast of the subject is appropriate for focus detection. In other words, if the contrast of the object is too low, the image on the second block (II) and the image on the reference part (R) to be compared will not match.
It may happen that the minimum peak value Y2 is detected and the image interval is detected.

Therefore, the contrast value C2 detected by the contrast detection circuit (44) is input to the comparison circuit (46), and
It is determined whether or not it is greater than a constant a5.

(Step 814 in FIG. 5) Here, the constant a5 is determined so that the detected contrast value C2 becomes larger than C5 when the subject image has a contrast suitable for focus detection. Contrast value C2 is constant 85
(i.e. C2≧as), the comparator circuit (
7 lag (F, ) is set by the output of 46), and its output becomes 1". In other words, when the contrast of the subject image is suitable for focus detection 24-, the output of the flag (F5) becomes " It becomes "1", and becomes "0" if it is inappropriate.

On the other hand, the contrast value C2 stored in the memory circuit (44) is also input to the arithmetic circuit (48), and the constant a2,
C3 and C4 are multiplied respectively, C2C2, a 3
C2, a 4 C2 are determined and these are stored in memory.

Here, the constants a2, C3, and a are determined to vary the level at which it is determined whether the minimum comparison data H2(n) is reliable or not according to various conditions, and C
The relationship 2<as<a< holds true. This arithmetic circuit (
C2C2, C3C2, C4C calculated by 48)
2, in order, the first determination level, the second determination level, and #
31! ! This is called a fixed level. Each judgment level a2C2, a
, , C3, C4C4 are respectively input to the comparator circuit (50), and the minimum peak value Y2 from the memory circuit (40)
The size relationship between the two is compared. And the minimum peak value Y2
When is smaller than the first judgment level C2C2, 7 lag (F2) is set by the output of the comparator circuit (50),
Its output becomes "1". Furthermore, when the minimum peak value Y2 is smaller than the second judgment level C3C2, the comparison circuit (
7 lag (F3) is set by the output of 50), and its output becomes "1".
When the judgment level is lower than a4C2, the comparison circuit (5
7lag (F4) is set by the output of 0), and its output becomes "1".

That is, since a2 < a3 <a<, Y2≦
When a2C2, three 7 lags (F2) (F, ) (F
, ) are all set, and when a2C2<Y2≦a3C2, flags (F2) (F3) are set, and flag (
F,) are not set. Also, a3C2<Y2≦a,
At C2, only the flag (F,) is set, and a,
When C2<Y2, none of the 7 lags is set. As described above, it is determined which determination level the minimum peak value Y2 is below.

The logic circuit at the bottom right of Fig. 4 determines whether the subject brightness is appropriate for focus detection (whether the flag (F,) is set or not), and whether the contrast of the subject image is appropriate for focus detection. Condition (whether flag (F5) is set or not)
, and the condition as to whether or not the previous focus detection was performed under appropriate conditions (7 lags (F + s
) is set or not), the determination level for determining whether or not the minimum comparison data H2(n) detected using the second block is reliable is selected. This logic circuit will be explained below along with the chart 70 in FIG.

First, in the 70-chart of FIG.
3 and S, it is determined whether the flag (Fl) is set and whether the flag (F5) is set. And this flag (Fl)
If either (F5) is not set,
A progress flag (F6) is set in step SI5. This means that in Fig. 4, if the output of any one of the flags (F, ) (F5) is "0", the output of ANDI becomes "θ"', and NANDI) The output of is “1” and 7 lags (F6
) is set. And Nando Day)
When the output of (NAND+) becomes "1", the output 27- of (AND2) corresponds to the 7 lag (F2). Therefore, Nando date (N
The output of A N D +) becomes “1” and 7 lags (F
6) is set, if Y2≦a2C2 and 7 lag (F2) is set, ANDD) (A N
The output of D2) becomes 1” and the output is 1”.
The output of is “1”, and Y 2 > a 2 C2 makes 7
If the lag (F2) is not set, the anime game)
The output of AND2) remains O''. That is, the operation of step S16 in FIG. 5 is performed.

In a state where both flags (F,) (F5) are set and the output of Antogame) (AND,) is "1", the output of AND date (A N D 3) is the flag (F's
) according to the output. As will be described later, the flag (F+s) is set when no reliable minimum comparison data is obtained using any of the first to third blocks. That is, the fact that the flag (Fls) is set indicates that the previous focus detection was performed under inappropriate conditions. As mentioned above, Antogame) (A
Outside of the state where the output of ND,) is 1'', the flag (
If Fl5) is set 28-, the output of AND date (A N D3) is "1"'
If the flag (F's) is not set, the output of the game (AND3) will be "0". That is, AND3) is the step 81 in FIG.
7 is performed.

Returning to Figure 4, the output of &D)(AND,) is “
1", if the flag (F, 5) is set and its output is "1", then
The output of A N D 3) becomes “1” and the inverter (I
The output of NV, ) becomes "0". Therefore, andday)
(AND,) closes. On the other hand, ANDa
) becomes “1”, ANDday) (ANDs)
The output of is responsive to the flag (F,). And the flag (F
, ) is set, the output of AND,) will be 1", and the output of OR,) (OR+) will also be "1".
''.If the flag (F, ) is not set, the output of AND5 is 0''. That is, the game) (AND5) is executed in step S18 in FIG.
Perform the following actions.

Returning to FIG. 4 again, if the output of ANDI is "1" and 7lag (F15) is not set, the output of AND3 is "0" and the inverter (INV , ) is "1".

Therefore, if the flag (F,) is set, the output of ANDD)(AND,) will be 1", and ORD)(
The output of OR+) also becomes "1". Meanwhile, flag (F4)
is not set, and date (A N D
, ) is "0". i.e. andday)
(AND4) performs the operation of step S19 in FIG.

To summarize the above operations using the 70-chart in FIG. (F6) is set, and the minimum peak value Y2 is determined based on the most severe first determination level a2C2. If this judgment passes, this minimum comparison data H2(n) calculated in block (A) is used to detect the defocus amount; if it does not pass, the next first block is used for focus detection 70- to go into. Furthermore, if it is determined in steps 813 and S14 that both the subject brightness and the subject image contrast are appropriate, the process proceeds to step S17, where it is determined whether or not the previous focus detection was appropriate. If the previous focus detection was appropriate, proceed to step srs, and proceed to the third judgment level a where the minimum peak value Y2 is the loosest.
, C2. If the previous focus detection is not appropriate, proceed to step S16 and minimum peak value Y2
is determined based on the intermediate second determination level a3C2. In either case, if it is determined to pass, the minimum comparison data H2(n) calculated in this circuit block (A) is used to detect the defocus amount, and if it is determined to be rejected, the next Step 70- of focus detection using one block is entered.

Step 820 is a predetermined time t. This is the step of counting. In this embodiment, focus detection is first performed using the second block, and when reliable focus detection is not possible, the first block is used, and when reliable focus detection is still not possible. The third block is used for 31- Then, there are cases in which reliable focus detection is achieved using only the second block, cases in which reliable focus detection is achieved using up to the first block, and cases in which reliable in-focus detection is achieved using up to the third block. A time count in step S2° is provided in order to keep the computation time constant depending on when focus detection is performed. The meaning of this will be explained later. In Figure 4, output terminal (T1)
teeth,#! 10 The focus detection circuit block (B) using the first block (I) shown in FIG. 10 and the focus detection circuit block (C) using the third block (■) shown in FIG. Necessary pixel signals are transmitted. The output terminals (T2) and (T3), together with the output terminal (T5), are connected to an instruction circuit (CPU) as shown in Figure @14. The output terminal (T4) is connected to the circuit block (
B) and (C), and is used to determine the minimum peak value Y detected in each circuit, or the determination level of Y.

Next, the focus detection circuit block (B) using the first block (1) shown in FIG. 10 will be explained with reference to the flowchart shown in FIG. 11. As mentioned in 32- above, the operation of this circuit block (B) can yield reliable minimum comparison data H2(n) by the operation using the second block (II) of the circuit block (A) in FIG. It is only done when it is not possible. In other words, the fourth
Only when the output of (OR+) shown in the figure remains "O" and the detected minimum peak value Y2 is judged as failure, the signal from the instruction circuit (CPU) shown in FIG. Circuit block (B) of FIG. 10 is activated.

In FIG. 10, the arithmetic circuit (126) corresponds to the arithmetic circuit (26) of the circuit block (A), and performs the calculation of =2 (24) on 5 Σ"k-rk+N+7'. (Step S2 in Figure 10) However, here, the subscripts H and (N) indicate that the first block (1) is used, and N = 1.2, . . . , 8. It is.

That is, the circuit block (B) detects the correlation between the first block (1) of the reference part (L) shown in FIG. 3 and the pixel column to the right of the pixel element (r9) of the reference part (R). . In other words, focus detection using the first block (I) is performed when the image interval is wider than when the image is in focus on a predetermined image formation screen, In other words, it is for detecting the rear pin state.

Each comparison data H calculated in the calculation circuit (126)
1 (N) is stored in the memory circuit (128) together with the shift amount N, as in the case of the circuit block (A), and the one that takes the minimum value among the eight comparison data is sent to the minimum value detection circuit (130). ), and the minimum comparison data H1(n) is stored in the memory circuit (132) together with the minimum shift amount n. (Figure 11 Step S2□
) After that, the arithmetic circuit (134) detects the image interval finer than the pixel pitch by 6 h, (n-1)=ΣI 1k-rk+N+81 --(
25) k=2 h, (n+1)=Σ"k-rk 1N+8'"""
(26) The values hl(n i) and hl(n+1) where k=1 are calculated,
It is stored in the memory circuit (136). Using this, the minimum peak value Y1 when using the first block (I) is calculated by the calculation circuit (138).

This minimum peak value Y, is stored in the memory circuit (140). (Steps 823 and S2 in FIG. 11) The configuration of (126) to (140) in FIG.
They correspond to steps (26) to (40) shown in the figure, and steps 521-324 in FIG. 11 showing the operation thereof also correspond to steps S, -S, . . . in FIG.

Furthermore, in FIG. 10, the contrast detection circuit (14
2) is similar to the contrast detection circuit (42) in FIG. 4, and calculates the contrast value C1 by performing the following calculation: 5 (27) . (
(Step 525 in FIG. 11) This contrast value is the sum of the absolute values of the output differences between two adjacent pixels in the first block (I). The calculated contrast value C1 is stored in a memory circuit (144). This contrast value C1 is input to the arithmetic circuit (148), and similarly to the arithmetic circuit (48) in FIG. 4, it is multiplied by constants a2, a3, a, respectively, and the minimum comparison data Y + I) ＞
Judgment levels a2C1, a, , C1, a4c1 are determined. These judgment levels a2CI, a, c1, a4CI are input to a comparison circuit (150) and compared with the minimum peak value Y1, and if Y1≧a2C1, a flag (F7
) is set, and if Y1≧a3C, then 7-7g (F
8) is set, and if Y1≧a, C, the flag (F
, ) are set.

On the other hand, the contrast value C1 is also input to the comparison circuit (146) and compared with the same constant a5 as the comparison circuit (46) in Figure $4, and if C1≧a5, the flag (F, o) is set. (Step 526 in FIG. 11). Furthermore, here,
In place of a5, the ratio of the number of pixels in the second block (II) to the number of pixels in the first block (1) 36--The logic circuit at the bottom right of FIG.
This is a configuration for executing steps 831 to 831, and since it is similar to the logic circuit at the bottom right of FIG. 4, it will be briefly explained. First, if the flag (F+o) is not set and its output is "0", or even if the flag (F+) is set, it is connected via the terminal (T, ). If the 7 lag (F6) is not set and its output is 0, the output of AND date (A N D a) is “0”.
0'' and Nando Day) (N A N D 2)
The output of is "1". Therefore, if the output of the flag (F7) is "1", the output of AND date (A N D t) will be "1", and the output of OR date (OR2) will be "1".
”.If the output of the flag (F7) is 0, the output of AND is also 0. That is,
ANDD) (AND6) is step S27 in FIG.
The determination operation of step 82B is performed, and the determination operation of step 82B is performed.

The output of both flags (F 6) (F ,,) is 1″
If so, the output of (AND,) is the terminal (
7,3) connected by 7 lags (F +s) described below.
according to the output of If the output of the flag (FI5) is "1", the output of the AND date (AND8) becomes "1", and the AND date (A N D,,) opens,
AND Day) (AND9) closes. In this state, the output of AND, .) follows the output of the flag (F8). That is, ANDIO) is shown in step S of FIG. Make a judgment. On the other hand, flag (F
If the output of AND date (AN
The output of De) becomes “0” and the inverter (INVz)
opens "(7"l'?-)(ANDs). Therefore, the output of the flag (F
, ), ANDs performs the operation of step S31 in FIG. 11.

In addition, and date (A N D a) is a flag (F15
) according to the output of both AND date (A N D 5)
The operation of step S29 in FIG. 11 is performed to alternatively open (A N D +o).

Three and dates (A N D?) (A N D
5) When the output of either (AND,,) becomes 1, the output of (OR2) also becomes 1, and the first
Proceeding to step S3□ in FIG. 1, a predetermined period of time t elapses.

is counted. Here, the current opening t1 is the time t shown in step S20 in Figure #5. shorter than In the case where reliable minimum comparison data H2(n) is obtained through steps 88 to 819 in FIG. 5, and when step S
If reliable minimum comparison data H+(n) is obtained by step S31 after proceeding to step 821 in FIG. The time t is set so that the computation time is kept constant depending on when H,(n) is obtained. , F are defined.

The terminal (TV) (T8) in FIG. 10 is connected to the instruction circuit (c p u ) in FIG. 14, and H, (n), n, h
Each data of l(n 1)h+(n+12 ) is transmitted. The terminal (T9) is also connected to the instruction circuit (CPU), and if the output of the terminal (T9) is "1", the data sent from the terminal (TV) ('re) is used for the image interval calculation described later. If the output of terminal 39- (T9) is “0”, the third block (II
Activate the focus detection circuit block (C) using I).

Next, the focus detection circuit block (C) using the third block (II) shown in FIG. 12 will be explained with reference to its flowchart in FIG. As mentioned above, the operation of this circuit block (C) is performed by the circuit block (C) of FIG.
A) using the second block (n) and the tenth
Depending on the calculation using the first block of circuit block (B) in the figure, the minimum comparison data H2(n), H
It is only done when l(n) is not available. In other words, the output of OR2 shown in FIG.
0", and only when the detected minimum peak value Y is judged to be rejected, the instruction circuit (CP
The circuit block (C) shown in FIG.
) is activated.

In FIG. 12, the arithmetic circuit (226) corresponds to the arithmetic circuit (26) of the circuit block (A), and is 40-2 +Σ11k-rk+N-81...(28)k
Perform the calculation =9. (Step 533 in Figure 13) Here,
The subscript of H3(N) indicates that the third block (II[) is used, and N=1.2, . . . , 8.

That is, the circuit block (C) detects the correlation between the third block (III) of the reference part (L) shown in FIG. 3 and the pixel column to the left of the pixel (r23) of the reference part (R). In other words, focus detection using the third block (III) is
This is done when the image interval is narrower than when the images are in focus on a predetermined image formation plane, that is, to detect the front bin state.

Each comparison data H calculated in the calculation circuit (126)
3(N) are each stored in the memory circuit (22B) together with the shift amount N as in the case of the circuit block (A), and the one that takes the minimum value among the eight comparison data is sent to the minimum value detection circuit ( 230), and the minimum comparison data i+5(n) is stored in the memory circuit (232) together with the minimum shift amount n. (Figure 13 Step S
3. ) After that, the arithmetic circuit (234) converts q 2 t++ (n+ 1 ) = Σ"k-' to +n-7' - · in order to detect an image interval finer than the pixel pitch.
---・<30) k=8 The values h3(n-1) and ha(n+1) are calculated, and using this, the minimum peak value Y3 when using the third block (I[I) is calculated. It is calculated by the calculation circuit (238).

This minimum peak value Y3 is stored in the memory circuit (240). (Steps S35 and 536 in FIG. 13) The configurations (226) to (240) in FIG.
They correspond to steps (26) to (40) shown in the figure, and steps 833 to 836 in FIG. 13 showing the operation thereof also correspond to steps 88 to S in FIG. 5.

Furthermore, in FIG. 12, a contrast detection circuit (24
2), similar to the contrast detection circuit (42) in FIG. 4, performs the following calculation to detect the contrast value C3.

(Step 537 in Figure 13) This contrast value is
This is the sum of absolute values of output differences between two adjacent pixels in the third block (I[l). Calculated contrast value C8
is stored in the memory circuit (244).

This contrast value C3 is input to the arithmetic circuit (248), and like the arithmetic circuit (48) in Figure #4, the constant a2,
a3, a, are respectively terminated, and the minimum peak value Y, 3
Three determination levels a2C3, a, C3, and a4C3 are defined. This judgment level a2C,,,a3C3,a,C3
is input to the comparison circuit (250) and the minimum peak value Y3
If Y3≦a2C3, the flag (
Fl, ) is set, if Y3≦a3C3, the flag (F12) is set, and if Y3≦a4C3, 7
43- Lag (F,,) is set. On the other hand, the contrast value C3 is also input to the comparison circuit (246), and is compared with the same constant a5 as the comparison circuit (46) in FIG. 4, so that C3≧a
If it is 5, a flag (Fl4) is set. (13th
(Step 838) Here, a5' may be used instead of 85 as described above.

The logic circuit at the bottom right of FIG. 12 is the step 838 in FIG. 13.
This is a configuration for executing steps S44 to S44, and since it is similar to the logic circuit at the bottom right of FIG. 4, it will be briefly explained. First, if the flag (F, 4) is not set and its output is "0", or even if the flag (F,,) is set, it is connected via the terminal (T,). 7 in Figure 4
If lag (F6) is not set and its output is “0”, the output of Antogame) (AND,,) is “0”.
0”, and the output of NAND,) is “1”.
Therefore, if the output of the flag (Fl) is "1", the output of AND date (A N D +2) will be "1", and the output of OR date (OR3) will be "1".

Output of flag (F1+) 44- If the force is “0”, it is an anime game) (A N D +2
) is also “θ”. That is, andday) (A
N.D.

I) performs the determination operation of step S2° in FIG.
(AND, 2) performs the determination operation in step S40.

If the output of both flags (F6) (Fl, ) is "1", the output of AND+3 is the terminal (
In response to the output of the flag (F, 5) connected by TI3). If the output of the flag (F's) is "1", the output of AND date (A N D, 3) is "1", and as AND date (AND, S) opens, Anto game) (A N D+4) closes. In this state, the output of AND date (A N D +s) is the flag (
Follow the output of F+□). i.e., andday) (A
N D +5) performs the determination in step S42 in FIG. On the other hand, if the output of the flag (F's) is "0", the output of AND+3 becomes "0", and the AND gate (AN
D,, ) is opened. Therefore, Antogame) (AND+
Since the output of 4) follows the output of the flag (Fl3), AND date (A N D+4) is executed at step 843 in FIG.
Perform the following actions. In addition, and date (A N D +3
) is both AND and D according to the output of the flag (F15)
The operation of step S41 in FIG. 13 is performed to alternatively open (AND, 4) (AND, 5).

3 and dates (A N D +2) (A N D
, , )(A N D +s) is “1”.
”, the output of OR3 also becomes “1” and the process proceeds to step S4S in FIG.

On the other hand, three AND dates (A N D +2) (A
All outputs of N D +4) (A N D +s) are “0”
”, the output of ORDATE (OR3) also becomes “0”, and the flag (F, 5) is output via the inverter (INV, ).
is set. That is, the flag (F's) is set when reliable minimum comparison data cannot be obtained using any of the circuit blocks (A), (B), and (C), and its output becomes "1". In the next calculation operation,
It is used to make the minimum peak value judgment level stricter than usual. In addition, in steps 833 to 70- of FIG. 13 showing the operation of this focus detection circuit block (C), time counting is performed corresponding to step 820 of FIG. 5 and step S3□ of FIG. There are no steps. This is done in step S1 as described above.
If the minimum comparison data that ends in confidence is detected by 70- from 820 to 820, 70- from step 832 is also detected.
Whether the reliable minimum comparison data is detected by 70- up to step S43 or the reliable minimum comparison data is detected by 70- up to step S43, furthermore, step S4
Even if reliable minimum comparison data is not detected after proceeding to Step 4, in order to keep the calculation time constant for all cases, the calculation time for other cases will be adjusted to the flow of performing up to the longest step S43 or S44. It is.

Here, if this computation time is made constant, the timing at which the next CCD integration is to be completed can be determined according to the time point at which this computation is completed.

The terminals (Tz) (T+□) in FIG. 12 are connected to the instruction circuit (c p u ) in FIG. 14, and Hen, ns
Each data of h3(n-1) and h3(n+1) is transmitted. Terminal 47- (TI4) is also connected to the instruction circuit (CPU), and if the output of the terminal (TI) is "1", the signal is sent from the image interval calculation terminal (T, , ) (T, □), which will be described later. If the data is adopted and the output of the terminal (TI, ) is "0", another operation to be described later is performed.

FIG. 14 shows the focus detection circuit blocks (A) (,B).
In addition to controlling the operation of (C), the detected minimum comparison data H2(n), H, (n) or H
3(n) and its minimum shift amount n is used to calculate the direction and amount of defocus (D). In FIG. 14, the instruction circuit (CPU) connects terminals (T2) (T,
), the minimum comparison data H2(n) and its minimum shift amount n are inputted, and data indicating whether this data H2(n) is reliable or not is inputted through the terminal (T5). Ru. The instruction circuit (CPU) is connected to this terminal (T5)
If the output of is “1” and it is determined that the minimum comparison data H2(n) is reliable, this data H2(n) is set to Hi(
n) to the arithmetic circuit (300). Furthermore, in this case, the input from the memory circuit (36) 48- in FIG. 4 via the terminal (T,) or (n
1), h2(n+1) data is sent to the instruction circuit (CP
U) to the arithmetic circuit (300) and comparison circuit (302)
is input. Further, if the output of the terminal (T5) is "1", the instruction circuit (CPU) operates the counter (CO) to count the time t0. That is,
The counter (CO) performs the operation of step S20 in FIG.

Similarly, the terminal (T) of circuit block (B) or (C)
If the output of 9) or (Tz) is "1", it indicates that the minimum comparison data H, (n) or H3 (n) calculated in that block is determined to be reliable.

Therefore, if the output of either the terminal (T, ) or (TI4) is "1", the minimum comparison data H1(n) or H*(n) from the circuit block that outputs it is used as the minimum comparison data H1(n) or H*(n) from the instruction circuit (CP). ) is input to the arithmetic circuit (300). If the output of the terminal (T, ) is 1'', the instruction circuit (CPU) operates the counter (CO) to count the time t1. That is, the counter (CO) The operation of step S32 in FIG. 11 is also performed.

As described above, the instruction circuit (CP[, J) inputs the minimum comparison data l-1i(n) determined to be reliable to the arithmetic circuit (300). Furthermore, hi(n-1), hi(
n+1) (here, i is either 1.2.3) is input to the arithmetic circuit (300) and the comparison circuit (302).

The comparison circuit (302) receives two input data hi(
n-1) and old (n+1), and send the comparison result to the arithmetic circuit (300) (step S in Fig. 13,
5). The arithmetic circuit (300) performs one of the following depending on the comparison result. That is, bi(n 1)≧hi(
In the case of n+ 1), □ X = n+ -F FFEJIII-IM bitsujiri,
,..., The interpolation minimum shift amount X determined by (32) is calculated, and if 1+i (n - 1) < hi (n+1), then X = n
......The interpolation minimum shift amount X given in (33)
is calculated.

(Steps S, 6, S, 7 in Figure 13) This arithmetic circuit (
300) calculates the minimum shift amount in units finer than the minimum shift amount n in pixel pitch units using the above equations (32) and (33), and the requested shift amount is defined as the interpolation minimum shift amount X. do. How to determine this interpolation minimum shift amount X will be explained below using FIGS. 15(a) and 15(b).

First, Fig. 15(a) is a graph in which the horizontal axis shows the shift amount and the vertical axis shows the comparison data, and as shown in Fig. 8(c), h
The case where i(n-1)≧hi(n+1) is shown. To find the shift amount with the highest degree of agreement between the shift amounts n-1 and n, or between n and n+1, first, calculate the slope of line numerator 1 at the midpoint Q1 between n-1 and n. think of. This line molecule 1 is defined as connecting point hi(n-1) and point Hi(n), and the area outside this area is Hi(n)-hi(n
1). On the other hand, the slope at the midpoint Q2 of the line molecule 2 connecting point Hi(n) and point h i (n 11) is hi
(n+1) −H1(n). Figure 15(b) shows the two slopes determined in this way at points (■
1) Plotted as 51-(■2). Next, this point (
Consider a line molecule 3 connecting Vl) (V2), the point where this line molecule 3 intersects with the horizontal axis is (V,), and the shift amount up to this point (v3) is the interpolation minimum shift amount X.

This interpolation minimum shift amount X is hi(n-1) and hi(n
(32) (33
) is determined by one of the following formulas. The interpolation minimum shift amount X calculated in this way is the memory circuit (30
4) is stored in memory.

Further, using this interpolation minimum shift amount X, the amount of deviation P between the image on the reference portion (L) and the image on the corresponding reference portion (R) is calculated by the calculation circuit (306).

(Step S, 8 in Fig. 13) This calculation is performed as follows: P=Z, -Z
2-Z3+X-1 (34). however,
Here, Z is the value corresponding to the distance between pixels (11) and (rl) in Figure 3, and Z2 is the image distance when in focus, that is, the distance between pixels (1, 2) and pixels (r, , ). This value corresponds to the interval L2. Z3 is a constant determined depending on which of the first to third blocks the minimum comparison data detected is used in the calculation of the calculation circuit (300). Then, Z, = 4, Z2 = 8, and Z3 is -8 when the minimum comparison data of the first block is used, and 0 when the second block is used.
For the third block, it is set as +7. When determined in this way, P=0 when in focus, and p<o when in focus.

In the rear bin state, P>0.

In this way, the interpolation minimum shift amount X is determined to be the deviation amount P. Here, the relationship between the interpolation minimum shift amount X and the deviation amount P is shown in FIG. In FIG. 16, the number line in the upper row shows the interpolation minimum shift amount X in each block, and the number line in the lower row shows the shift amount P in units of pixel pitch. for example,
When X=5 in the second block, P=4-8-0+5-1=0, and it is detected that P=0, that is, in-focus state. Also, if X=6 in the first block, then P=4-8+8+6-1=9, and if X=4 in the third block, then P=4-8-7+4. -1=-8, and the rear bin state and front bin state are respectively detected.

(308) is a memory circuit that stores the above-mentioned constants 71, Z2, and Z3, and depending on the signal from the instruction circuit (CPU), which block has the minimum comparison data Hi(
The value of constant 73 is selected depending on whether n) is detected and sent to the arithmetic circuit (306) together with constants Z1 and Z2.

The calculated deviation amount P is input to the comparison circuit (310), and the positive and negative signs are detected (step S1 in FIG. 12).
．． ), if P≦0, a flag (F +y) is set and its output becomes “1”. (Figure 12 Step 55o
) If P>0, the output of the flag (F, , ) remains "0". That is, the flag (F.

The output of 7) indicates the direction of defocus of the lens with respect to the planned imaging plane, and when the front bin or in-focus state is detected, the output of 7 lag (FI7) becomes "1", and the rear bin state is detected. Then, the output of 7 pufferfish (F17) becomes "0". The output of the flag (F17) is input as a defocus direction signal indicating the defocus direction to a lens drive motor control circuit (430), which will be described later, and is used to control the lens drive direction.

Furthermore, the calculated deviation amount P is also input to the defocus amount calculation circuit (312), and is multiplied by a constant a6 stored in advance in the memory circuit (314) to obtain the defocus amount DF.
I get criticized. This constant a6 is used to convert the amount of deviation P of two corresponding images on the line sensor arranged to extend in the direction perpendicular to the optical axis into the amount of defocus DF in the optical axis direction of the image plane with respect to the planned focal plane. It is determined. That is, the constant a6 is determined depending on the distance from the planned focal plane to the line sensor, the magnification of the condenser lens and the re-imaging lens, and the like. The calculated defocus amount DF is stored in the memory circuit (316), and the defocus amount DF is stored in the memory circuit (316).
) is input as a defocus amount signal to a lens drive motor control circuit (430), which will be described later, and is used to control the lens drive amount.

In this embodiment, the reference part (R) has three professional 755
- The second block is used to perform focus detection near the focus position, and focus detection is performed preferentially;
The other blocks are used only when focus detection using the second block is inappropriate or impossible. Therefore, compared to a system in which each block has its own focus detection result and the final result is determined after determining which one is correct, the circuit configuration can be simplified and the subject can be Rapid focus detection is also possible in the case of a repeating pattern that has a predetermined relationship with the pitch. The first block is used only when focus detection by the second block is impossible or inappropriate, and if it is still impossible or inappropriate, the third block is used. There is no need for a means to determine whether the results are correct.

FIG. 17 is a circuit diagram showing an embodiment in which a microcomputer is used in the signal processing circuit of the focus detection device of the present invention. This circuit will be explained below along with its operation.

56- When the microcomputer (μm00M) detects that the AF switch is turned on by pressing the release button once, the microcomputer (μm00M) starts the focus adjustment operation.

First, from the microcomputer (μm00M) to the CCD
(404) outputs a pulsed integral clear signal ICG, which resets each pixel of the CCD (404) to its initial state, and outputs A from the brightness monitor circuit MC.
GCO8 recovers to the power supply voltage level. At the same time, the microcomputer (μm00M) outputs an H-level shift pulse generation enable signal 5HEN. Then, at the same time as the integral clear signal ICG disappears, the CCD (4
04) starts integrating the photocurrent, and at the same time, the output AGCO8 of the brightness monitor circuit MC starts to decrease at a speed corresponding to the subject brightness, but the reference signal output DO3 from the reference signal generating circuit R3 is based on a fixed standard. maintained at the level.

The AGC controller (406) compares AGCO8 with DO8 and calculates a predetermined time (100 + osec when detecting focus).
, A within 50 m5ec, ) when measuring dark output data.
The gain of the variable gain differential amplifier (408) is controlled depending on how much GCO8 decreases relative to DO8.

Further, when the AGC controller 7 (406) detects that AGCO8 has decreased by a predetermined level or more with respect to DO8 within a predetermined time after the integral clear signal ICG disappears, it outputs an H level signal TINT at that time. This signal TINT
is input to a shift pulse signal output circuit (410) through an AND circuit (AN) and an OR circuit (OR), and in response, a shift pulse SH is output from this circuit (410). When this shift pulse SH is input to the CCD (404), photocurrent integration by each pixel is completed, and charges corresponding to this integrated value are transferred in parallel to corresponding cells of the CCD shift register. On the other hand, microcombination
Based on the clock pulse CL from the sensor drive pulse generation circuit (412), the phase is 18.
Two sensor drive pulses φ1. shifted by 0°. φ2 is output and input to CCD(4(14).CCD(
404) among these sensor drive pulses, in synchronization with the rising edge of φ1, the charges of each cell of the COD shift register are discharged one by one from the end in series, and the voltage O8 that forms the video signal is sequentially output. . This voltage O8 becomes higher as the intensity of light incident on the corresponding pixel is lower, and a subtraction circuit (414) subtracts this from the above-mentioned reference signal DO8 and outputs (DO8-O8) as a pixel signal. . Furthermore, if a predetermined time elapses without TINT being output after the disappearance of the integral clear signal ICG, the microcomputer (
μmCOM) is the H level shift pulse generation command signal S
Output HM. Therefore, the AGC controller (406
) if the H level TINT signal is not output from
In response to this shift pulse generation command signal SHM, a shift pulse generation circuit (410) generates a shift pulse SH.

On the other hand, in the above operation, a microcomputer (μ
mCOM) outputs a sample hold signal S/H when pixel signals corresponding to the seventh to tenth photosensors are output.

As a result, the peak hold circuit (416) outputs O8 and D corresponding to the aluminum mask portion of the photosensor array.
The difference with O8 is held, and thereafter this difference output and the pixel signal are input to the variable gain amplifier (40B). Then, the variable gain amplifier (408) converts the difference between the pixel signal and the difference output into an AG
The amplified output is further amplified with a gain controlled by a C controller (406), and the amplified output is A/D converted by an A/D converter (418). ).

(420) is a dark output data memory that holds correction dark output data obtained based on the dark output measurement data measured while the shutter of the photosensor array is closed, and (422) is a microcomputer during focus detection operation. A dark output correction circuit (424) subtracts correction dark output data of the memory from pixel signal data supplied through (μmCOM), and (424) is a focus detection calculation circuit. Further, SW is an opening/closing switch that works in conjunction with the mirror drive of the single-lens camera, and the operating mode of the microcomputer (μ-〇〇M) changes depending on the opening/closing of this switch.

Now, when the release button is pressed one step as described above, the mirror is in the lowered position, the switch SW is open, and the dark output data memory (420) has already stored the data obtained from the previous shooting. Dark output data for correction is saved.

By pressing the release button one step, the above-mentioned integration clear signal is generated, and at the same time as this signal disappears, photocurrent integration starts at each pixel of the CCD (404), but when the switch (SW)
Microcomputer (μmCO
Since M) sets the above-mentioned predetermined time to 100 m5ec, its integral time is at most 100IIlsec. That is,
If the object is constant and brighter than the bell, after the ICG disappears, AGCO8 drops to a predetermined level of 2.8■ with respect to DO8 before 100111see elapses, and the AGC:I controller (4,06) outputs the TINT signal and the variable gain amplifier ( 40
A gain control signal that sets the gain of B) to 1 is output. On the other hand, if the object is darker than the certain level described in 1.
8 does not drop to the specified level 2.8V with respect to DO8, and the microcomputer (#-COM) has a voltage of 100 m5ec.
An SHM signal is generated at the elapsed time point, and in response to this SHM signal, a shift pulse SH is generated and a gain control signal is output from the AGC controller (406). That is, in this case, the AGC controller (406) performs 100 to 200 seconds, 200-4 seconds depending on the degree of decrease in AGCO8 within the predetermined time of 100 m5ec.
00 m5ec, 400-800 m5ec.

It determines whether 800+n5ecm5ec minutes are required and generates a gain control signal to set the gain of the amplifier (40B) to 1x, 2x, 4x, or 8x, respectively. , while the TINT signal is not output.

In this way, when the maximum photocurrent integration of 100 In5ec is completed, the microcomputer (μmC0M)
It is sequentially determined whether the gain control data indicated by the gain control signal input from the GC controller (406) is 8 times, 4 times, or 2 times, and if it is 8 times, the dark output data memory (420
) is outputted to double the correction dark output data stored in ), and the double correction dark output data is input to the dark output correction circuit (422) as correction data. Also, if it is 4 times, the dark output data for correction in the memory (420) is directly inputted to the correction circuit (422) as correction data (the dark output measurement data is multiplied by 1), and if it is 2 times, the dark output data for correction in the memory (420) is input as correction data to the correction circuit (422). ) is outputted to 1/2 times the correction dark output data, and inputs the 1/2 times the correction dark output data as correction data to the correction circuit (422). If the gain control data is 1x, not 8x, 4x, or 2x, the microcomputer (μmC0M) similarly outputs a signal that multiplies the dark output data for correction in the memory (420) by 174, and /4 times the dark output data for correction circuit (
422).

On the other hand, due to the generation of the shift pulse SH, the CCD (404
) is completed, and pixel signal data 63 = from the A/D converter (418) is input to the microcomputer (μmC0M).

The microcomputer (μmC0M) sequentially outputs this pixel signal data to the correction circuit (422), but at this time, the integration time varies depending on whether or not the TINT signal is input.
+n5ec or less is determined. If it is less than 100m5ec, the TINT signal is output), 100 m5
If it is greater than ec, the correction circuit (422) subtracts the above correction data from each pixel signal data and outputs the difference data. On the other hand, if it is less than 100 m5ee, the pixel signal data is output as is without causing the correction circuit (422) to perform this subtraction. After this focus detection calculation circuit (
424) sequentially stores this difference data or pixel signal data in the internal memory, but once the data corresponding to all pixels of the image sensor has been stored, it is used to calculate the amount of focus shift and its value according to a predetermined program. Calculating the directions and displaying them on the display circuit (426),
On the other hand, the level drive device (428) is driven according to the amount and direction of focus shift to perform automatic focus adjustment of the photographic lens (430).

64. In this embodiment, CCD integration, data dump, and focus detection calculations are repeated to improve accuracy.

In the above embodiment, each pixel output 1. ~1□3
, rl-r31, but the present invention is not limited to this. For example, from the output signal 11 of pixel (11) to pixel (15) in FIG.
The output signal L3 corresponding to the position of pixel (13) is obtained by subtracting the output signal 15 of , and the output signal L3 corresponding to the position of pixel (1) is obtained by subtracting 16 from 1□. By performing the above calculation using the difference between several pixels as an output signal at the center position, the image frequency component of the image can be cut.

(hereinafter referred to as margin) Effects As described above, the present invention provides a first light beam created from the subject light flux that passes through the first part and the second part of the photographic lens, which sandwich the optical axis of the photographic lens. In a focus detection device that detects the relative distance between the first and second images and the amount of deviation of the photographing lens from the in-focus position, a large number of photodiodes are arranged to receive each subject's light flux. It has first and second light receiving means each consisting of a photodiode array in which cells are arranged in a row, and the output signal corresponding to each cell in the first light receiving means is set as tINtk, and the second light receiving means is
The output signals corresponding to each cell in the light receiving means of
m (k × m), and when the output signal sequence of the second light receiving means with the highest degree of coincidence with the output signal 41+t1 to tk of the first light receiving means is r9+1 to r90, (19), 20) and (21) can be generalized.

This feature is characterized in that the image interval between the two images is determined by using the above, and by configuring in this way, the image interval can be determined at a pitch even finer than the pitch of the cells. Then, the difference between the output signals → used in the calculation of each value A, B, and C can be reduced to improve accuracy.

[Brief explanation of the drawing]

FIG. 1 is a sectional view schematically showing a conventional focus detection device and a focus detection device of the present invention, FIG. 2 is a schematic diagram without showing its principle, and FIG. 4.10,12.
FIG. 14 is a block diagram showing an embodiment of the present invention, Section 5.11.
Figure 13 is a flowchart, Figure 6 is a graph showing the necessity of interpolation, Figure 7 is a graph showing an example of the output of the light receiving means, and Figures 8 (a) to (d) are graphs showing the shift amount and correlation value, respectively. FIG. 9 is a graph showing how to determine the minimum comparison data Y2 by the interpolation method of this embodiment.
Figures (a) and (b) are graphs showing how to determine the minimum shift amount n by the interpolation method of this embodiment, Figure 16 is a number line showing the relationship between interpolation minimum shift (IIX) and deviation amount P, and Figure 17 is a graph showing how to calculate the minimum shift amount n by the interpolation method of this embodiment. The figure is a block diagram showing an embodiment in which a microcomputer is used for the arithmetic processing of the above embodiment. (2); Taking lens; (g); First light receiving means; however);
Second light receiving means. Applicant: Minolta Camera Co., Ltd. Figure 7 (A)

Claims (1)

[Claims] A relative relationship between two images, a first and a second image, which are formed from a subject light flux that passes through a first part and a second part of a photographic lens, which are sandwiched by the optical axis of the photographic lens. In a focus detection device that detects the amount of deviation of the photographing lens from the in-focus position by detecting the distance between the photographic lens and the focal point, a photodiode array consisting of a large number of photodiode cells arranged in a row is used to The output signal corresponding to each cell in the first light receiving means is sequentially t1 to tk, and the output signal corresponding to each cell in the second light receiving means is 11 to 1m (k<m) in order, and the output signal sequence of the second light receiving means that has the highest degree of coincidence with the output signals tt to tk of the first light receiving means is r9+1 to 7''
A focus detection device characterized in that, when q-1-k, the distance between the images on both light receiving means is determined using values A, B, and C determined by.