JPS60246636A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60246636A JPS60246636A JP10174484A JP10174484A JPS60246636A JP S60246636 A JPS60246636 A JP S60246636A JP 10174484 A JP10174484 A JP 10174484A JP 10174484 A JP10174484 A JP 10174484A JP S60246636 A JPS60246636 A JP S60246636A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- silicon
- silicon nitride
- semiconductor device
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 33
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 30
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 24
- 238000001020 plasma etching Methods 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 13
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 13
- 239000011347 resin Substances 0.000 claims abstract description 10
- 229920005989 resin Polymers 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 claims 2
- 229910002092 carbon dioxide Inorganic materials 0.000 claims 1
- 239000001569 carbon dioxide Substances 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 43
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 20
- 239000007789 gas Substances 0.000 abstract description 13
- 238000006243 chemical reaction Methods 0.000 abstract description 12
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 9
- 230000000694 effects Effects 0.000 abstract description 7
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 abstract description 2
- 239000000203 mixture Substances 0.000 abstract 4
- 239000012495 reaction gas Substances 0.000 description 5
- 238000003486 chemical etching Methods 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は半導体装置の製造方法に係わり、特に窒化シ
リコンを反ｋ［ｌ、性イオンエツチングする方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of etching silicon nitride with anti-k[l, ions.
従来エツチングは弗酸等の化学薬品を用いたケミカルエ
ツチングが一般的であった。しかしながら、このような
ケミカルエツチングでは、マスク材料の下がエツチング
されるという、いわゆるサイドエツチングが現象が発生
する。このようなケミカルエッチングにおけるサイドエ
ッチ量は、ジャストエツチングでエツチング膜厚とほぼ
等しくなる。例えば、半導体装置の製造プロセスで用い
られる一般的なエツチング膜厚である０、５〜１．０〔
師〕をエツチングした場合、サイドエツチング量も０．
５〜１．０（μｍ〕となり、サイドエツチング量の２倍
であるパターン変換差は１０〜２０〔μｍ〕となる。Conventionally, chemical etching using chemicals such as hydrofluoric acid has been common. However, in such chemical etching, a so-called side etching phenomenon occurs in which the bottom of the mask material is etched. The amount of side etching in such chemical etching becomes approximately equal to the etching film thickness in just etching. For example, the typical etching film thickness used in the manufacturing process of semiconductor devices is 0.5 to 1.0 [
When the side etching is performed, the amount of side etching is also 0.
5 to 1.0 (μm), and the pattern conversion difference, which is twice the side etching amount, is 10 to 20 [μm].
一方、半導体装置の高集積化に伴い、ノ＜ターン寸法が
２〔μｍ）、１．５Ｃμｍ〕と小さくなってきており、
このケミカルエツチングによるサイドエツチングは、半
導体装置の製造プロセス上、大きな問題となってきてい
る。On the other hand, with the increasing integration of semiconductor devices, the turn dimensions have become smaller to 2 [μm] and 1.5Cμm.
Side etching caused by chemical etching has become a major problem in the manufacturing process of semiconductor devices.
このような問題から、サイドエツチングのほとんどない
エツチング方法として反応性イオンエツチング（Ｒｅａ
ｃｔｉｖｅ Ｉｏｎ Ｅｔｃｈｉｎｇ １以下ＲＩＥと
略す）法が開発され、実用化されつつある。Due to these problems, reactive ion etching (Reactive ion etching) is an etching method with almost no side etching.
A method of active ion etching (hereinafter abbreviated as RIE) has been developed and is being put into practical use.
このＲＩＥ法を、半導体基板上に堆積した窒化シリコン
のエツチング除去に適用する場合、一般に次のように行
なわれている。When this RIE method is applied to etching and removing silicon nitride deposited on a semiconductor substrate, it is generally performed as follows.
＋１＋先ず、反応室内に設けられた平行平板形電極の陰
極に、半導体基板を、半導体基板上に堆積した窒化シリ
コンが陽極に対向するよつに載置する。+1+ First, a semiconductor substrate is placed on the cathode of a parallel plate electrode provided in a reaction chamber so that the silicon nitride deposited on the semiconductor substrate faces the anode.
（２）反応室内をロータリーポンプ等の真空ポンプで排
気した後、反応室内に反応ガスを１０〜１０ ’ （Ｔ
ｏｒｒ）になるまで導入する。反応ガスとしてはＣ１（
Ｆ′３と０２の混合ガス、又はＮＦ３とＳＦ６の混合ガ
ス等が現在使われている。(2) After evacuating the reaction chamber with a vacuum pump such as a rotary pump, the reaction gas is pumped into the reaction chamber for 10 to 10' (T
orr). As a reaction gas, C1 (
A mixed gas of F'3 and 02 or a mixed gas of NF3 and SF6 is currently used.
（３）平行平板電極間に高周波（１３，５６（ＭＨｚ）
’）電圧を印加する。(3) High frequency (13,56 (MHz)) between parallel plate electrodes
') Apply voltage.
以上の工程により、半導体基板上の窒化シリコン近辺で
プラズマが発生し、このプラズマ中で反応ガスと窒化シ
リコンが反応し、♀化／リコンがエツチングされていた
。Through the above steps, plasma is generated in the vicinity of silicon nitride on the semiconductor substrate, and the reactive gas and silicon nitride react in this plasma, thereby etching the fertilized/reconned silicon.
しかしながら、上述したようなＲＩＥ法では、パターン
変換差が無視できるほど小ざいというメリットがあるも
のの、９化シリコンのエツチングレートが小さいという
欠点があった。However, although the above-mentioned RIE method has the advantage that the difference in pattern conversion is negligibly small, it has the disadvantage that the etching rate of silicon 9ide is low.
また、このエツチングレートが小さいがゆえに、窒化シ
リコンの下に、半導体基板や、二酸化シリコン、多結晶
シリコン等の下地膜が有る場合、又は窒化シリコンが部
分的に二酸化シリコン、多結晶シリコン、感光性樹脂等
のマスク材料で神われている場合には、前述したような
半導体基板、下地膜、マスク材料と窒化シリコンとの間
のエツチング選択比が少さいという欠点もあった。Also, because this etching rate is low, if there is a semiconductor substrate, silicon dioxide, polycrystalline silicon, etc. under the silicon nitride, or if the silicon nitride is partially exposed to silicon dioxide, polycrystalline silicon, photosensitive material, etc. When a mask material such as resin is used, there is also the drawback that the etching selectivity between the semiconductor substrate, base film, mask material and silicon nitride is low as described above.
この発明の目的は、 ＲＩＥ法を利用し、且つ窒化シリ
コンのエツチングレートを増すよう改善された半導体装
置の１１′！竜方法を提供することにある。An object of the present invention is to provide a semiconductor device 11' that utilizes the RIE method and is improved to increase the etching rate of silicon nitride. Our goal is to provide the best way.
この発明は、窒素の添加された雰囲気中において、窒化
シリコンを反応性イオンエツチングする工程を具備した
半導体装置の製造方法であって。The present invention is a method of manufacturing a semiconductor device, which includes a step of reactive ion etching of silicon nitride in an atmosphere added with nitrogen.
これにより窒化シリコンのエラチングレートラ増すよう
にしたものである。This increases the erating rate of silicon nitride.
本発明者は、 ＲＩＥ法において、反応ガス中ＶＣ窒素
を添加したとき、望化／リコンのエツチングレートが気
化することを見出し、実験的にも確認した。この発明は
１本発明者自身による、このような実験結果にもとずく
ものである。The inventors of the present invention have found that the etching rate of recon/recon is vaporized when VC nitrogen is added to the reaction gas in the RIE method, and this has also been confirmed experimentally. This invention is based on the results of such experiments conducted by the inventor himself.
以下、本発明を実施例により図面を用いながら説明する
。Hereinafter, the present invention will be explained using examples and drawings.
先ずＲＩＥの反応ガスとして、 ＣＩ（Ｆ３と０２の混
合ガスを用いた場合を例にとって説明する。First, an example will be explained in which a mixed gas of CI (F3 and 02) is used as the RIE reaction gas.
（１）先ず、ＲＩＥ装置の反応室（容１Ｌ８０リットル
）内に設けられた平行平板形電極の陰極に、エツチング
される物か堆積している半導体基板を載置する。(1) First, a semiconductor substrate on which the material to be etched has been deposited is placed on the cathode of a parallel plate electrode provided in a reaction chamber (volume: 80 liters) of an RIE apparatus.
（２）反応室内を、ロータリーポンプ等の真空ポンプで
約１０−５（Ｔｏｒｒ）になるまで排気する。続いて。(2) The inside of the reaction chamber is evacuated to about 10-5 (Torr) using a vacuum pump such as a rotary pump. continue.
ＣＨＦ ３と０２の混合ガス（混合比１０：Ｉ）を毎分
８０ （ｃｃ ／ｍｉｎ ）％ ’Ｊ素を０〜１００
（ｃｃ／ｍｉｎ ）導入し、排気量を調整することによ
り、反応室内を５０〔ｍＴｏｒｒ）にする。Mixed gas of CHF 3 and 02 (mixing ratio 10:I) at 80 (cc/min)% 'J element 0 to 100 per minute
(cc/min) and adjust the exhaust volume to bring the inside of the reaction chamber to 50 mTorr.
（３）平行平板電極間に１２００Ｗの畠周波（１３，５
６（ＭＥ（ｚ））を印加する。(3) 1200W Hatake frequency (13,5
6 (ME(z)) is applied.
以上の工程によりエツチングしだ場合について、エツチ
ングされる物が、９化シリコン、二酸化シリコン、多結
晶シリコン（単結晶シリコンでも結果は同じ）、感光性
樹脂のそれぞれの場合について、窒素ガスの添加量とエ
ツチングレートの関係を第１図に示す。When the etching process starts using the above process, the amount of nitrogen gas added is determined for each case where the material to be etched is silicon 9ide, silicon dioxide, polycrystalline silicon (the result is the same even with single crystal silicon), or photosensitive resin. The relationship between etching rate and etching rate is shown in Figure 1.
第１図から明らかなように、窒素を添加しなかっｒｔ
＋Ｍ合、窒化シリコンのエツチングレートケ、毎分４０
０〔χ〕で、選択比は、対二酸化シリコンが１、対多結
晶シリコンが４、対感光性樹脂が３であったのに対し、
反応室内に窒素を適当量、例えば２０ （ｃｃ ／ｍｉ
ｎ ）添加することにより、窒化シリコンのエツチング
レートが、毎分７００（Ｘ）に増え。As is clear from Fig. 1, rt without adding nitrogen
+M combination, silicon nitride etching rate, 40 per minute
At 0 [χ], the selectivity ratio was 1 for silicon dioxide, 4 for polycrystalline silicon, and 3 for photosensitive resin.
A suitable amount of nitrogen is added into the reaction chamber, for example 20 (cc/mi
By adding n), the etching rate of silicon nitride increases to 700 (X) per minute.
選択比もこれによって、対二酸化シリコンが１．８、対
多結晶シリコンが７、対感光性樹脂膜が５と、それぞれ
増す口した。As a result, the selectivity increased to 1.8 for silicon dioxide, 7 for polycrystalline silicon, and 5 for photosensitive resin film.
ところで、 ＲＩＥの反応ガスとして、ＮＦ３とＳＦ６
の混合ガスを用いたｊｊ４合についても、以下に示すよ
うに同種の効果がみられた。By the way, NF3 and SF6 are used as reactive gases in RIE.
The same type of effect was observed in the jj4 case using a mixed gas as shown below.
＋１＋先ず、 ＲＩＥ装置の反応室（容量８０１Ｊツト
ル）内に設けられた平行平板形′４．極の陰極に、エツ
チングされる物が堆積している半導体基板を載置する、
（２）反応室内を、ロータリーポンプ等の真空ポンプ等
の真空ポンプで約１０− ’ （Ｔｏｒｒ） Ｋなる寸
で排気する。続いて、 ＮＦ：３とＳＦ６の混合ガス（
混合比１：１）を毎分４０ （ｃｃ／ｍｉｎ 〕、屋素
をＯ〜１００（ｃｃ／ｍｉｎ ）導入し、排気量を調整
することによζ反応室内を５０（ｍＴｏｒｒ）にする。+1+ First, a parallel plate type '4. Place the semiconductor substrate on which the material to be etched has been deposited on the cathode. (2) Heat the inside of the reaction chamber to approximately 10-' (Torr) K using a vacuum pump such as a rotary pump. Exhaust. Next, a mixed gas of NF:3 and SF6 (
A mixing ratio of 1:1) was introduced at a rate of 40 (cc/min) per minute, and oxygen was introduced at a rate of 0 to 100 (cc/min), and the inside of the ζ reaction chamber was adjusted to 50 (mTorr) by adjusting the exhaust volume.
（３）平行平板１ど、極間に１．２００Ｗの高周波（１
３，５６（ＭＨｚ））を印加する。(3) Parallel plate 1, 1.200W high frequency (1
3,56 (MHz)) is applied.
以上の工程によりエツチングした場合について、エツチ
ングされる物が、窒化シリコン、二酸化シリコン、多結
晶シリコン（単結晶シリコンでも結果は同じ）、感光性
樹脂のそれぞれの場合について、窒素ガスの添加量とエ
ツチングレートの関係を第２図に示す。When etching is performed using the above process, the amount of nitrogen gas added and etching are determined depending on whether the material to be etched is silicon nitride, silicon dioxide, polycrystalline silicon (single crystal silicon results in the same result), or photosensitive resin. The rate relationship is shown in Figure 2.
第２図から明らかなように、窒素を添加しなかった場合
、窒化シリコンのエツチングレートは、毎分２００ （
Ｘ）で、選択比は、対二酸化シリコンが２．３、対多結
晶シリコンが１．３、対感光性樹脂が１．５であったの
に対し、反応室内に窒素を適当量、例えば２０ （ｃｃ
／ｍｉｎ ）添加することにより、窒化シリコンのエ
ツチングレートが、毎分４５０ （Ａ）に増え、選択比
もこれによって、対二酸化シリコンが６、対多結晶シリ
コンが３、対感光性樹脂膜が４と、それぞれ増加した。As is clear from Figure 2, when no nitrogen is added, the etching rate of silicon nitride is 200 m/min (
X), the selectivity ratio was 2.3 for silicon dioxide, 1.3 for polycrystalline silicon, and 1.5 for photosensitive resin. (cc
/min), the etching rate of silicon nitride increases to 450 (A) per minute, and the selectivity increases to 6 for silicon dioxide, 3 for polycrystalline silicon, and 4 for photosensitive resin film. and each increased.
本発明は＃４１図及び第２図に示したこの新たな現象を
半導体装置の製造に適用したものである。The present invention applies this new phenomenon shown in FIG. 41 and FIG. 2 to the manufacture of semiconductor devices.
本発明は窒化シリコンをエツチング除去する工程を有す
る半導体装置の製造方法であれば、どのようなものに対
しても適用でき、窒化シリコンのエツチングレートが増
し、これにより、エツチング時間を短縮することができ
るという効果が得られる。The present invention can be applied to any semiconductor device manufacturing method that includes a step of etching away silicon nitride, increasing the etching rate of silicon nitride, thereby shortening the etching time. You can get the effect that you can.
オた、特にエツチング除去する窒化シリコンが、７リコ
ン、ガリウム砒素等の半導体基板上に設けられている場
合、二酸化シリコン上に設けられている場合、多結晶シ
リコン上に設けられている場合等、エツチング除去する
窒化シリコンの下に半導体基板や下地膜となるものがあ
る場合は、窒化シリコンをオーバエツチングした場合で
も、半導体基板や下地膜の膜減りを小袋＜シ、これによ
り、本発明による半導体装置の製造方法により得られた
半導体装置の緒特性を向上きせることかできるというさ
らに顕著な効果が得られる。これは、本発明が窒化シリ
コンのエツチングレートだけを増し、半導体基板や下地
膜のエツチングレートは変化しないか、逆に減少すると
いう第１図及び第２図に示した特性をもった工程を有す
るところからくるものである。In addition, especially when the silicon nitride to be removed by etching is provided on a semiconductor substrate such as 7 silicon or gallium arsenide, when it is provided on silicon dioxide, when it is provided on polycrystalline silicon, etc. If there is a semiconductor substrate or underlying film under the silicon nitride to be removed by etching, even if the silicon nitride is over-etched, the film loss of the semiconductor substrate or underlying film can be reduced by using a sachet. A further remarkable effect is obtained in that the mechanical characteristics of the semiconductor device obtained by the device manufacturing method can be improved. This process has the characteristics shown in FIGS. 1 and 2, in which the present invention increases only the etching rate of silicon nitride, while the etching rate of the semiconductor substrate and underlying film remains unchanged or decreases. It comes from somewhere.
さらに、本発明は、エツチング除去する窒化シリコンが
部分的に二酸化シリコン、多結晶シリコン、感光性樹脂
等のマスク材料で覆われている場合にも、マスク材料の
膜減りが少ないというざらに顕著な効果が同じ理由から
得られる。近年、半ア
このセル７ノラインによるエンチングの際、マスク材料
の膜減りが少ないということは、これによって得られた
半導体装置の諸特性向上に大きく貢献することができる
。Furthermore, even when the silicon nitride to be removed by etching is partially covered with a mask material such as silicon dioxide, polycrystalline silicon, or photosensitive resin, the present invention has a remarkable effect that the film loss of the mask material is small. The effect is obtained for the same reason. In recent years, the fact that the film of the mask material is less reduced during etching using the half-A cell line can greatly contribute to improving various characteristics of the semiconductor device obtained.
この発明によれば、 ＲＩＥ法を利用し、且つ窒化シリ
コンのエツチングレートを増し、これによりエツチング
時間を短縮′することができる半導体装置の製造方法を
提供できる。According to the present invention, it is possible to provide a method for manufacturing a semiconductor device that utilizes the RIE method and increases the etching rate of silicon nitride, thereby shortening the etching time.
第１図は反応ガスとして、 ＣＨＦ３と０２の混合ガス
を用いた場合の、窒素添加量とエツチングレートの関係
を、エツチングされるものが窒化シリコン、二酸比シリ
コン、多結晶シリコン、感光性樹脂の各場合について示
すグラフ、第２図は同じく反応ガスとして、 ＮＦ’３
とＳＦ６の混合ガスを用いた場合のグラフである。Figure 1 shows the relationship between the amount of nitrogen added and the etching rate when a mixed gas of CHF3 and 02 is used as the reaction gas. The graphs shown in Fig. 2 for each case are similar to that of NF'3 as the reactant gas.
It is a graph when a mixed gas of and SF6 is used.
Claims (5)
いて、反応性イオンエツチングする工程を具備した半導
体装置の製造方法。(1) A method for manufacturing a semiconductor device comprising a step of reactive ion etching of nitride/recon in an atmosphere added with elemental elements.
ることを特徴とする特許請求の範囲第１項記載の＃畳体
装置にの製造方法。(2) The method for manufacturing a #tatami body device according to claim 1, wherein the silicon 9ide is provided on a semiconductor substrate.
ていることを特徴とする特許請求の範囲第１項記載の半
導体装置の製造方法。(3) The method of manufacturing a semiconductor device according to claim 1, wherein the silicon 9ide is provided on silicon dioxide.
ていることを特徴とする特許請求の範囲第１項記載の半
導体装置の製造方法。(4) The method of manufacturing a semiconductor device according to claim 1, wherein the silicon nitride is provided on polycrystalline silicon.
ていることを特徴とする特許請求の範囲第１項、第２項
または第；う項記載の半導体装置の製が方法。 １６）前記マスク材料が二酸化／リコンであることを特
徴とする特許請求の範、囲域５項記載の半導体装置の製
造方法。 （力前記マスク材料が多結晶／リコンであることを特徴
とする特許請求の範囲第５項記載の半導体装置の製造方
法。 １８）前記マスク材料が感光性樹、田であることを特徴
とする特許請求の範囲第５項記載の半導体装的の製造方
法。(5) A method for manufacturing a semiconductor device according to claim 1, 2 or 3, wherein the silicon nitride is partially covered with a mask material. 16) The method for manufacturing a semiconductor device according to claim 5, wherein the mask material is carbon dioxide/licon. (The method for manufacturing a semiconductor device according to claim 5, characterized in that the mask material is polycrystalline/licon. 18) The method for manufacturing a semiconductor device, characterized in that the mask material is a photosensitive resin. A method for manufacturing a semiconductor device according to claim 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10174484A JPS60246636A (en) | 1984-05-22 | 1984-05-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10174484A JPS60246636A (en) | 1984-05-22 | 1984-05-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60246636A true JPS60246636A (en) | 1985-12-06 |
Family
ID=14308752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10174484A Pending JPS60246636A (en) | 1984-05-22 | 1984-05-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60246636A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06342769A (en) * | 1992-08-21 | 1994-12-13 | Nissin Electric Co Ltd | Etching method and device |
| JPH06342770A (en) * | 1992-08-21 | 1994-12-13 | Nissin Electric Co Ltd | Etching method and device |
| US5387312A (en) * | 1993-07-09 | 1995-02-07 | Micron Semiconductor, Inc. | High selective nitride etch |
| US5756216A (en) * | 1993-07-09 | 1998-05-26 | Micron Technology, Inc. | Highly selective nitride spacer etch |
| DE10027932A1 (en) * | 2000-05-31 | 2001-12-13 | Infineon Technologies Ag | Etching insulating layer of component involves using catalyst before and/or during etching; catalyst is applied to at least one inner surface of structure to be etched |
-
1984
- 1984-05-22 JP JP10174484A patent/JPS60246636A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06342769A (en) * | 1992-08-21 | 1994-12-13 | Nissin Electric Co Ltd | Etching method and device |
| JPH06342770A (en) * | 1992-08-21 | 1994-12-13 | Nissin Electric Co Ltd | Etching method and device |
| US5387312A (en) * | 1993-07-09 | 1995-02-07 | Micron Semiconductor, Inc. | High selective nitride etch |
| US5756216A (en) * | 1993-07-09 | 1998-05-26 | Micron Technology, Inc. | Highly selective nitride spacer etch |
| DE10027932A1 (en) * | 2000-05-31 | 2001-12-13 | Infineon Technologies Ag | Etching insulating layer of component involves using catalyst before and/or during etching; catalyst is applied to at least one inner surface of structure to be etched |
| DE10027932C2 (en) * | 2000-05-31 | 2003-10-02 | Infineon Technologies Ag | Method for forming a contact hole in an insulating layer of an electronic or microelectronic component |
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