JPS60244870A - Arithmetic measuring method of alternating current signal - Google Patents

Arithmetic measuring method of alternating current signal

Info

Publication number
JPS60244870A
JPS60244870A JP10105284A JP10105284A JPS60244870A JP S60244870 A JPS60244870 A JP S60244870A JP 10105284 A JP10105284 A JP 10105284A JP 10105284 A JP10105284 A JP 10105284A JP S60244870 A JPS60244870 A JP S60244870A
Authority
JP
Japan
Prior art keywords
sampling
period
waveform
arithmetic
converter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10105284A
Other languages
Japanese (ja)
Inventor
Fujio Hori
宝利 冨士夫
Kenshichiro Mishima
健七郎 三島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP10105284A priority Critical patent/JPS60244870A/en
Publication of JPS60244870A publication Critical patent/JPS60244870A/en
Pending legal-status Critical Current

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  • Measurement Of Current Or Voltage (AREA)

Abstract

PURPOSE:To prolong considerably a data processing time and to perform sufficient processing by a general A/D converter and a general operational element by increasing the number of times of sampling in one period for intermittent sampling. CONSTITUTION:Sample holding circuits 14 and 15, an A/D converter 17, an arithmetic processor 18, a multiplexer 16, and a memory part 19 are provided. Each period of an AC signal input waveform is divided into numbers of a sampling sections, and the sample holding circuits 14 and 15 sample all sections in every period intermittently and successively as many times as possible without the repetition of the same sampling period; and the results are measured by the arithmetic processor 18 as a waveform approximate to an AC input signal whose one period corresponds a number obtained by the number of sampling periods in one period of the input waveform through the sampling circuits, and the arithmetic of sampling data, all-sampling-section arithmetic I of the last approximate waveform, totalization arithmetic II of data, and the output are performed divisionally between sampling periods.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、交流信号の演算計測方法に係シ交流信号を簡
単な構成でかつ高精度に測定しようとするものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an arithmetic and measurement method for alternating current signals and is intended to measure alternating current signals with a simple configuration and with high precision.

従来例の構成とその問題点 交流信号の電圧・電流・有効電力・皮相電力等を計測す
る場合について説明する。入力信号の電圧、電流の瞬時
値をそれぞれv’、i、Tとするとき、電気諸量は次の
ように定義される。
The configuration of a conventional example and its problems The case of measuring the voltage, current, active power, apparent power, etc. of an AC signal will be explained. When the instantaneous values of the voltage and current of the input signal are v', i, and T, respectively, the electrical quantities are defined as follows.

(3) 有効電力W−(S′i′・1dt)/T ・・
・・・・(3)ここでまず従来例の構成を第1図により
説明する。図において、1,2はそれぞれ電流、電圧信
号入力端子、3は測定値のデジタル出力端子であり、4
,5,6.7はそれぞれ電流・有効電力・電圧皮相電力
変換器であり、各計測項目毎に上述の(1)〜(4)式
のアナログ演算を行った結果を直流出力に変換し出力す
る。8はマルチプレクサで、演算処理装置10の指令に
より複数個の入力I、W。
(3) Active power W-(S'i'・1dt)/T...
(3) First, the configuration of the conventional example will be explained with reference to FIG. In the figure, 1 and 2 are current and voltage signal input terminals, 3 is a digital output terminal for measured values, and 4 is a digital output terminal for measured values.
, 5, 6.7 are current/active power/voltage apparent power converters, respectively, which convert the results of the analog calculations of equations (1) to (4) above for each measurement item into DC output and output it. do. 8 is a multiplexer which receives a plurality of inputs I and W according to instructions from the arithmetic processing unit 10;

V、 V’Aのうち1つ全選択してA/D変換器9に出
力する。演算処理装置1Qは測定装置全体を統括するも
ので、計測回路の切替え、A/D変換器−2の計測指令
、計測結果の読み取りと出力端子へのデータ出力を行う
。このように各計測項目毎に1ケの変換器を設けるので
計測項目が多い場合には装置が大形となり、高価になる
欠点を有する。
One of V and V'A is fully selected and output to the A/D converter 9. The arithmetic processing unit 1Q supervises the entire measuring device, and performs switching of the measuring circuit, measurement commands to the A/D converter 2, reading of measurement results, and data output to the output terminal. As described above, since one converter is provided for each measurement item, the device becomes large and expensive when there are many measurement items.

発明の目的 本発明は、このような従来の欠点を除去し、簡単な構成
でかつ高精度の交流信号測定を行うものである。
OBJECTS OF THE INVENTION The present invention eliminates these conventional drawbacks and measures alternating current signals with a simple configuration and high accuracy.

発明の構成 そのための構成として本発明は、サンプルホールド回路
、A/D変換器、演算処理装置、メモリ部および出力部
を有し、交流信号入力波形の毎周期を多数のサンプリン
グ区間に区分するとともに、1周期毎に出来る限り多く
間けつ的にサンプリングし、順次同様に同一サンプリン
グ区間とならないように全区間をサンプリングして入力
波形の1周期のサンプリング区間の数をサンプリング回
路で除した数の周期を1周期とする交流入力信号に近似
な波形として計測し、さらに毎サンプリングとサンプリ
ングの間においてサンプリングデータの演算と前回の近
似波形の全サンプリング区間演算■、データの集計演算
■および出力を分割して行うようにしたものである。
Structure of the Invention As a structure for this purpose, the present invention includes a sample and hold circuit, an A/D converter, an arithmetic processing unit, a memory section, and an output section, and divides each period of an AC signal input waveform into a large number of sampling sections. , sample intermittently as many times as possible in each cycle, and sample all intervals in the same way so that they are not the same sampling interval, to obtain a period equal to the number of sampling intervals in one cycle of the input waveform divided by the sampling circuit. is measured as a waveform approximate to the AC input signal with one period, and furthermore, between each sampling, calculation of the sampling data, calculation of the entire sampling period of the previous approximate waveform, data aggregation calculation■, and division of the output are performed. This is how it is done.

実施例の説明 以下本発明の一実施例について第2図により説明する。Description of examples An embodiment of the present invention will be described below with reference to FIG.

図において、11.12はそれぞれ電流、電圧信号入力
端子、13は計測値の出力端子である。
In the figure, 11 and 12 are current and voltage signal input terminals, respectively, and 13 is a measured value output terminal.

14.15は交流信号の瞬時値全サンプリングし、次の
サンプリング1でのサンプリング周期の間その値を保持
するサンプルホールド回路である。16はマルチプレク
サ、17はA/D変換器、18は演算処理装置でこの計
測装置全体の統括を行う機能を有するものである。19
はメモリ部である。
Reference numeral 14 and 15 are sample and hold circuits that sample all instantaneous values of the AC signal and hold the values during the next sampling period of sampling 1. 16 is a multiplexer, 17 is an A/D converter, and 18 is an arithmetic processing unit, which has a function of controlling the entire measuring device. 19
is the memory part.

以下その動作を第3図とともに説明する0まず第3図に
おいて、(a)は電流入力波形、(b)は電圧入力波形
、(C)は演算処理装置からサンプルホールド回路に与
えられるサンプリング指令波形、(d)は1サンプリン
グ周期における各部の動作順序を示すタイミング図であ
る。
The operation will be explained below with reference to Figure 3.0 First, in Figure 3, (a) is a current input waveform, (b) is a voltage input waveform, and (C) is a sampling command waveform given to the sample and hold circuit from the arithmetic processing unit. , (d) are timing diagrams showing the order of operation of each part in one sampling period.

電圧および電流信号入力の毎周期TiNケのサンプリン
グ区間に区分し、入力信号の1周期でX回サンプリング
すると同−周期内のサンプリング周期はτ/Xとなり、
次の周期捷でのサンプリング周期は(τ/X+τ/N)
である。
If each period of voltage and current signal input is divided into TiN sampling periods and sampled X times in one period of the input signal, the sampling period within the same period will be τ/X,
The sampling period for the next cycle is (τ/X+τ/N)
It is.

今n番目の区間をサンプリングしたとすると、図に示す
ようにサンプルホールド回路の出力はそN゛ れぞれin 、 Vnとなり、この値が次の(n 十x
 )番目のサンプリングを行うまでの間保持される。
If we now sample the nth interval, the outputs of the sample and hold circuit will be N in and Vn, respectively, as shown in the figure, and this value will be the next (n + x
) is retained until the second sampling is performed.

サンプリング周期内での各部の動作は(d)に示すよう
にサンプリングデータ処理を行うもので、まずデータの
サンプリング、次に1nの計測(A/D変換)、Vnの
計測、演算1行う0演算■および出力の区間は通常のサ
ンプリン周期では同上結果の動作は不要で計測周期の終
了時、すなわち入力波形のN/X周期の完了以後の次の
N/X周期区間で集計演算とデータ出力を行う。
The operation of each part within the sampling period is to process the sampling data as shown in (d), first sampling the data, then measuring 1n (A/D conversion), measuring Vn, and performing calculation 1 and 0 calculation. ■ and the output interval are the same as above in the normal sampling cycle, and the calculation and data output are performed at the end of the measurement cycle, that is, in the next N/X cycle interval after the completion of the N/X cycle of the input waveform. conduct.

演算Iの内容は次の数値演算を行う。The contents of operation I are as follows.

(3) W’ −1ne vn+ 、X= 1i、・v
、 (積の累計)演算■の内容は次の数値演算を行う。
(3) W' −1ne vn+, X= 1i, ・v
, (Cumulative sum of products) The content of operation ■ is the following numerical operation.

(1) V = J V’ /N (2) I−J工’/N (3) W = W’/N (4)V A= V A’/N 、上記説明のように入力波形の1周期において、X回サ
ンプリングを行うことにより、全サンプリング区間は入
力波形のN/X周期でサンプリングが完了するが、サン
プリングはサンプリング区間の区分の順に順次行っても
任意に行ってもよいものである。
(1) V = J V'/N (2) I-J'/N (3) W = W'/N (4) V A = V A'/N, as explained above, 1 of the input waveform By performing sampling X times in a period, sampling for all sampling sections is completed in N/X cycles of the input waveform, but sampling may be performed sequentially in the order of the divisions of the sampling section or at any time. .

なお演算工は各サンプリングホールド間において行われ
るが、前記の演算式に限定されるものでなく、各サンプ
リング値のvn、1n、1n、vnl 1n+ vn 
jのみを演算し、同演算結果をメモリに記憶し、全サン
プリング区間のサンプリング完了゛後、演算■の前に を演算してから演算してもよく、要はサンプリング結果
の演算および全サンプリング結果の集計、出力の作業゛
時間とサンプリング時間の合計である総作業時間を入力
波形の2N/X周期となるようにして、演算休止時間を
最小限にすることによって、サンプリング回数を出来る
限り多くし、入力波形に忠実な計測が出来るようにする
ことによって計測精度の向上を図ることができる。
Note that the calculation process is performed between each sampling hold, but it is not limited to the above calculation formula, and the calculation process is performed between each sampling value vn, 1n, 1n, vnl 1n+ vn
It is also possible to calculate only j, store the result of the calculation in memory, and then calculate after the completion of sampling for all sampling intervals and before operation ■, in short, calculate the sampling results and store the results of all sampling. The total work time, which is the sum of the output work time and sampling time, is set to be 2N/X cycles of the input waveform, and the number of sampling times is increased as much as possible by minimizing calculation down time. , measurement accuracy can be improved by making it possible to perform measurements that are faithful to the input waveform.

すなわち、上記説明の方法によれば、前記(1)。That is, according to the method described above, the above (1).

(2) 、 (3) 、 (41式ニ近似)V 、 I
 、 W’ 、 VA 請求メルこ屍が出来るものであ
り、分割数Nおよび1周期のサンプリング回数x7多く
することによって高精度のサンプリング計測を実現する
方法を提供するものである。なお上記に説明する演算式
は一実施例を示すものであり、無効電力、有効電力量。
(2), (3), (41 formula 2 approximation) V, I
, W', VA. This method provides a method for realizing highly accurate sampling measurement by increasing the number of divisions N and the number of samplings per period x7. It should be noted that the calculation formula explained above shows one example, and the reactive power and the active power amount.

無効電力量、力率の演算による多電索出力をも可能とす
るものである。また入力を多くすることによって多相回
路の計測も同様に可能とするものである。
It is also possible to output multiple electric cables by calculating reactive power amount and power factor. Furthermore, by increasing the number of inputs, it is possible to measure polyphase circuits as well.

発明の効果 以上詳述したように本発明により間けつサンプリングと
することにより、データ処理時間を大巾に広くし、汎用
のA/D変換器、演算素子でも充分に前述の処理を行う
ことを可能としたものである。さらに下記に記す効果を
有するものである0(1)複数入力の瞬時値の同時サン
プリング方法により、複数入力の演算出力が可能となり
、したがって有効電力や皮相電力は計測回路を必要とせ
ず、演算で有効電力値、皮相電力値がめられるものであ
る。さらに同様に無効電力、有効電力量、無効電力量、
力率の計測も計測回路を必要とせず演算でめられるもの
で多要素演算出力を可能とするものである。
Effects of the Invention As detailed above, by using intermittent sampling according to the present invention, the data processing time can be greatly expanded, and it is possible to sufficiently perform the above-mentioned processing even with general-purpose A/D converters and arithmetic elements. This made it possible. Furthermore, the 0(1) method of simultaneous sampling of instantaneous values of multiple inputs, which has the effects described below, enables the calculation output of multiple inputs.Therefore, active power and apparent power can be calculated without the need for a measurement circuit. The active power value and apparent power value can be measured. Similarly, reactive power, active energy, reactive energy,
The power factor can also be measured by calculation without the need for a measurement circuit, making it possible to output multi-element calculations.

(2)計測に演算処理装置を使用しているため、表示や
記録音する場合にも同一の演算処理装置やメモリ部の共
用化が図れ、装置全体を簡単な構成に出来る。
(2) Since the arithmetic processing unit is used for measurement, the same arithmetic processing unit and memory section can be shared even when displaying and recording sound, making it possible to simplify the overall configuration of the device.

(3)簡単な回路構成により小形、軽量化が出来、経済
効果に優れた方法を提供するものである。
(3) It provides a method that can be made smaller and lighter due to a simple circuit configuration, and has excellent economical effects.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の計測方法に使用する装置のブロック図、
第2図は本発明の計測方法に使用する装置の一実施例の
ブロック図、第3図は各部信号波形図である。 11・・・・・・電流信号入力端子、12・・・・・・
電圧信号入力端子、13・・・・・・出力端子、14.
15・・・・・・サンプルホールド回路、16・・・・
・・マルチプレクサ、17・・・・・・A / D変換
器、18・・・・・・演算処理装置、19・・・・・・
メモリ部。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第3図 エカ
Figure 1 is a block diagram of the equipment used in the conventional measurement method.
FIG. 2 is a block diagram of an embodiment of the apparatus used in the measurement method of the present invention, and FIG. 3 is a signal waveform diagram of each part. 11... Current signal input terminal, 12...
Voltage signal input terminal, 13...output terminal, 14.
15...Sample hold circuit, 16...
...Multiplexer, 17...A/D converter, 18... Arithmetic processing unit, 19...
memory section. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 3 Eka

Claims (1)

【特許請求の範囲】[Claims] サンプルホールド回路、A/D変換器、演算処理装置、
メモリ部および出力部を有し、交流信号入力波形の毎周
期を多数のサンプリング区間に区分するとともに、1周
期毎に出来る限り多く間けつ的にサンプリングし、順次
同様に同一サンプリング区間とならないように全区間を
サンプリングして入力波形の1周期のサンプリング区間
の数をサンプリング回数で除した数の周期を1周期とす
る交流入力信号に近似な波形として計測し、さらに毎サ
ンプリングとサンプリングの間においてサンプリングデ
ータの演算と前回の近似波形の全サンプリング区間演算
I、データの集計演算■および出力を分割して行うこと
を特徴とする交流信号の演算計測方法。
sample hold circuit, A/D converter, arithmetic processing unit,
It has a memory section and an output section, and divides each period of the AC signal input waveform into a large number of sampling sections, and samples as much as possible in each period intermittently, so that the sampling sections are not the same one after another. The entire interval is sampled and measured as a waveform that approximates the AC input signal, where one cycle is the number of sampling intervals in one cycle of the input waveform divided by the number of sampling times, and further sampling is performed between each sampling. A method for calculating and measuring an AC signal, which comprises performing data calculations, calculations for all sampling intervals of the previous approximate waveform (I), data aggregation calculations (2), and dividing the output.
JP10105284A 1984-05-18 1984-05-18 Arithmetic measuring method of alternating current signal Pending JPS60244870A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10105284A JPS60244870A (en) 1984-05-18 1984-05-18 Arithmetic measuring method of alternating current signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10105284A JPS60244870A (en) 1984-05-18 1984-05-18 Arithmetic measuring method of alternating current signal

Publications (1)

Publication Number Publication Date
JPS60244870A true JPS60244870A (en) 1985-12-04

Family

ID=14290345

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10105284A Pending JPS60244870A (en) 1984-05-18 1984-05-18 Arithmetic measuring method of alternating current signal

Country Status (1)

Country Link
JP (1) JPS60244870A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107238750A (en) * 2017-05-31 2017-10-10 沃太能源南通有限公司 A kind of network wave method for detecting based on discharge circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107238750A (en) * 2017-05-31 2017-10-10 沃太能源南通有限公司 A kind of network wave method for detecting based on discharge circuit

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