JPS60243849A - Detecting circuit of tracking error - Google Patents

Abstract

PURPOSE:To obtain a tracking error detecting circuit which can suitably be constituted with monolithic integrated circuits, by digitizing the entire circuit except a low-pass filter section. CONSTITUTION:A low-pass filter 11 which inputs the reproducing head output of a VTR extracts pilot signal components of f1-f4 only and an AD converter circuit 12 converts the signals into digital signals. The output of the pilot signals is calculated at a level of (N) times by a shynchronous adder circuit 26 and an attenuating circuit 22 attenuates the output of the pilot signals to 1/N and supplies the attenuated output to a subtractor circuit 23 as a subtraction input. The subtractor circuit 23 cancels the reproduced output f2 of the pilot signals recorded on track being reproduced only out of the outputs of the AD converter circuit 12 and accurately separates the pilot signals f1 and f3 of the adjacent tracks from each other. Since noise components which are aperiodic or multiples of non-integers can reach N<1/2> times at the highest even when the AD- converted output is added for (N) times, the pilot signal components can accurate be separated from each other.

Description

DETAILED DESCRIPTION OF THE INVENTION 0) Industrial Field of Application The present invention is applicable to a video tape recorder (VTR) called ``8 mm video'' which employs a tracking method called a 4-frequency method, and which prevents mistracking. Pilot signals of different frequencies were sequentially written along with the main signal onto multiple parallel tracks (parallel or concentric), which are recorded at high density in a state where crosstalk between adjacent tracks is unavoidable. The present invention relates to a tracking error detection circuit for a reproducing head (generally refers to a magnetic head, optical, and electrostatic pick amplifier) of an apparatus that reproduces a recording medium.

(b) Conventional technology In high-density recording VTRs such as 8mm video, in order to improve head tracking accuracy and i-axis performance, a one-rotation head is used instead of the conventional fixed control head to record the output along with the main signal. ATF method (automatic track finding system) or piezoelectric collector that controls the rotational phase of the capstan based on the amount of crosstalk of the pilot signal of the adjacent track being reproduced.

The DTF method (dynamic, track, and following method is used in Japanese Patent Laid-Open No. 53-1
It is disclosed in Publication No. 16120, etc., and also 8mm VTR.
As a standard.

For example, it is also explained in "Nikkei Electronics, May 23, 1983 issue, page 117 onwards."

Below, regarding the conventional example of this 8mm VTR, FIG. 5 shows the distribution on the tape pattern of the pilot signal recorded together with the main signal (video signal) on parallel video tracks, and FIG. 6 shows the block diagram of the tracking detection circuit.
This will be explained with reference to the figures. %5 In Figure 5, video tracks TI are provided diagonally in parallel on the magnetic tape (1).
, T2. T3...On Tn, FM brightness signal and FM audio signal.

The low-band conversion signal and the pilot signal are frequency-multiplexed and recorded in this order from the upper frequency band.

In the figure, DT indicates the running direction of the tape, and DI indicates the scanning direction of the rotary head.

The pilot signal is a signal of four different frequencies, and is used for adjacent tracks T1, T2 . T5. 'I' 4 and then f1. f2
．． f3, f4. fl, f2. f3. Like f4...
The frequency of each pilot signal is sequentially assigned in units of four consecutive tracks.

f 1=fo15 s in t 02.54 KHzf 2
==f o150+118.95 KI(Z...
...(11 f5 = 165.21KHz in fo156 f4 = fO/4
The frequency is set as 148.69 KHz.

Here, fO is the frequency expressed as a reference, and in the NTSO system, fO = 578 x fH, 5.947452MHz...
...(2) fM is the horizontal synchronization frequency, which is 15.73 in the case of the NTSC system.
4KHz Also, in the 0OIR system, fOgo575Xfi (3) fa is determined as 15.625KH16D in the 00IR system.

That is, the frequencies of these four pilot signals are:

For example, in the case of the NTSO system, the difference between pilot signals recorded on adjacent tracks is f2-f1=16.41KH1 t5-t5=46.26 KHz ---・--
---<4) fM-f4=-1452KHz f4-f1=46.15KHz And the beat frequency between the track being played and the adjacent track is about 145KH! or 46.2KH
The selection is made so that the direction of tracking deviation can be determined based on the value of z, and the degree of mistracking can be determined based on the level.

A typical example of such a four-frequency type tracking error detection circuit is constructed as shown in the block diagram in FIG.

In this circuit, a low-pass filter (1) with a cutoff frequency of about 200 KI (R) extracts only the pilot signal from the above-mentioned frequency multiplexed signal from the reproduced signal, and the first-stage mixing circuit (2) extracts the pilot signal from the reproduced signal. It is mixed with the pilot signal fPK corresponding to the track to obtain the beats of both tracks.Assuming that the head is currently reproducing the $2 track T2 on the tape pattern shown in FIG. The frequencies of the pilot signals used are fl and f3, respectively.

Due to the crosstalk caused by the mistracking situation, the outputs of the mixing circuit (2) are f2 to f1, respectively.
Medium 16.41KHK% t5-f2 Medium 2, 26KHz.

Each heat output is the first one centered at 1 (5,41KH!)
After being sharply separated by a band pass filter (3) and a second band pass filter (4) centering on 42.26KHK, the following first... Second detection circuit (5) (6)
After the signal is detected and smoothed, it is converted into a DC voltage value proportional to the peak value and applied as a comparison input to the level comparison circuit (7). The level comparison circuit (7) determines the magnitude relationship between both inputs and outputs a signal indicating the direction and amount of tracking correction, and in the case of the ATF method, shifts the driving frequency of the capstan motor to correct its rotational phase. However, in the case of the DTF method, the movement of the head in the track width direction is controlled by correcting the DC voltage applied to the piezoelectric element or bimorph that drives the helad actuator, and the movement is adjusted so that the tracking situation is normal. Modify direction and amount.

This conventional tracking system itself constitutes a good feedback control system and can be praised, but when judged from the viewpoint of reducing the cost of one circuit to zero or requiring no adjustment.

1) In order to perform 10 conversion by replacing a bandpass filter etc. with a digital filter etc., the frequency to be handled is high and it is difficult to perform monolink 10 conversion. Therefore.

Even if hybridization is adopted, the mounting area will become larger and disadvantages in terms of cost cannot be avoided.

2) The signal obtained from the head contains high frequency components such as tH, so it is necessary to increase the Q of the bandpass filter, but the difference between the pilot frequencies during recording and playback is V' It is unavoidable that such problems occur due to reasons such as compatibility of l'R sets, manufacturing defects, aging, and temperature fluctuations, and it is impossible to raise the IQ. For the reasons mentioned above, it is difficult to make a bandpass filter non-adjustable.

(C) Purpose of the Invention The present invention aims to overcome the above-mentioned drawbacks associated with the xO conversion of the tracking error detection circuit of the above-mentioned four-frequency system or a tracking system similar to this system, and
The purpose is to obtain a circuit suitable for

B) Structure of the Invention The tracking error detection circuit of the present invention digitizes the pilot signal component of the analog signal obtained from the head by AD converting it at a reference frequency fO, and generates crosstalk from adjacent tracks by digitel calculation. This extracts the pilot frequency component from multiple parallel tracks that are densely recorded in a state where crosstalk between adjacent tracks is unavoidable due to mistracking, such as in an azimuth recording type VTR. Device for reproducing a recorded recording medium 1 For example, assuming that this is a tracking error detection circuit for a VTR that reproduces a cassette tape of an 8 mm VTR, there is a pilot that is separated from the reproduction output and includes the crosstalk of nine adjacent tracks. A converting a signal into a digital value
-D conversion circuit.

The output of this circuit is added in synchronization with the period of the pilot signal recorded on the track being played.

By attenuating its output and subtracting this pilot signal component from the A-D conversion circuit output, the pilot signal component recorded on the track being played back is extracted from the output of the A-V conversion circuit. A cancellation circuit that cancels out the difference between the two, a two-series synchronization adder circuit that adds the output of this circuit in synchronization with the period of the pilot signal recorded on both adjacent tracks, and a comparison circuit that compares the outputs of each adder circuit. Equipped with.

The tracking error is detected by comparing the cross-digital values of the pilot frequencies of adjacent tracks detected as outputs of the respective adder circuits.

(e) Example Generally, a digital filter with the above configuration is used at 1ooxH.
It is very difficult to apply to a high frequency such as ffi-200KHgO even with conventionally known digital filters, switched filters, gapper voltage filters, filters, etc. However.

For example, what are the filter characteristics required for a four-frequency tracking error detection circuit such as 8 mm video?

It's not about extracting arbitrary frequencies.

The pylon has a certain proportional relationship with the reference frequency fo (it is only necessary to extract the frequency component, and the analog signal obtained from the head is 200KH!Excluding the video signal and audio signal of 200KH or more, the rfX theoretically has the pilot frequency. Contains nothing other than ingredients.

The present invention has been made in consideration of these points.

A basic embodiment in which the present invention is applied to the 8tlJV'l'H will be described below with reference to the main parts of the 151 Namazu Brodzuku M or Yushuukan 1Mh.

The figure number (ill) is a low-pass filter with a cutoff frequency of 200 KH2 that inputs the output of the reproducing head of V'l'H.

This circuit cuts the FM luminance signal, FM audio signal, and low frequency conversion color signal from the frequency multiplexed signal being reproduced and output,
Only pilot signal components f1 to f4 are extracted. The circuit is an A-D (analog-to-digital) conversion circuit that receives the output Ytt) of the low-pass filter as an input and converts the reference signal fo (=379fH) as a sampling signal into a 6- to 10-bit digital signal Aij. .

(4) is a cancellation circuit that removes the pilot signal component recorded in the track being reproduced from the output of the A/D conversion circuit. (110) and (120) respectively indicate the first and second synchronous addition circuits which input the output A1j of the A-D conversion circuit (13), and the former (110) receives the digital signal A1j as input, and this is added synchronously with the cycle of the pilot signal f1 recorded on one of the video tracks ('I'1) K adjacent to the video track (for example, T2) that the head is currently playing back, and the latter (
120) similarly receives the digital signal Aij as input.

Synchronous addition is performed at a cycle of 5 using the pilot signal recorded on the other video track T5, which is adjacent to the video track (T2) during full playback.

(210) (220) are the first. illustrating a second detection circuit;
'@1 detection circuit (210) and a first correlation circuit (211) which performs a digital correlation calculation between the pilot signal component to be extracted by this circuit and the fundamental sine wave signal of the pilot signal.

It consists of a first DC component cancellation circuit (212) that removes the influence of DC components from the output of this circuit, and a '@2 detection circuit (
220) is a '@2 correlation circuit (221) that performs a digital correlation calculation between the pilot signal component to be extracted by this circuit during the period and the fundamental sine wave signal of the pilot signal.
) and a second DC component cancellation circuit (220) that removes the influence of DO acid components from the output of this circuit. (201
) is a comparison circuit which receives the outputs of the first and second detection circuits (210) and (220). When the output level of the low-pass filter is large and the B/N is good, the first filter is input to the comparison circuit (2017). The outputs of the second synchronous adder circuits (110) (120) can be used.

First, the cancellation circuit (2) will be explained with reference to FIG. 2. This cancellation circuit (4) is
A conversion circuit (a synchronous addition circuit that receives the output of 13 as input),
i attenuation circuit that attenuates the output of this circuit, and the A-D
and a subtraction circuit (to) that subtracts the output of the attenuation circuit i from the output of the conversion circuit B.

The synchronous addition circuit receives the output of the A/D conversion circuit az as an input, and adds the difference in synchronization with the period of the pilot signal recorded on the track being reproduced.

In this synchronous addition circuit c2υ, @ is an adder, (c)
indicates a shift register, and (c) indicates an AND gate. The adder receives the output aij (10
output of the shift register (16 to 20 bits) gated by the clear m OLR
is used as another input, and the shift register has the longest register length of 58 (fo/
f1) A parallel register of 16 to 20 bits, and the ratio of each pilot frequency to the reference frequency fo/f2. fO/
f3. It has output terminals (tl) (t5) and (t4) each having a bit length of 50, 56, and 40 bits according to fo/f4, and is driven using the reference signal fO as a clock pulse.

The outputs generated from the output terminals (tl) (12) (15) (14) K of each bit length of this left register (112) are switched and selected by a multiplexer at a cycle of 1/60 seconds according to the pilot signal that becomes the synchronous addition input. and is added as an input to the adder via an AND gate.

Clear signal O applied to the control input of the AND gate
LR is 0 during the first addition period 1 of the pilot signals to be added, for example, each period of 58, 50, 56, 40 of the clock fO corresponding to the pilot signals f1 to f4, and becomes 1 after the s2 addition period. It is a unit function.

Therefore, the input signal Alj is sequentially and synchronously added at the addition period of the pilot signal of the track that is being reproduced and specified by the input signal Alj. The synchronous addition will be explained later in 1. Second synchronous addition circuit (110)
(120) will be explained in detail.

The output of the pilot signal recorded on the track being reproduced by the synchronous addition circuit is calculated at a level N times higher. The subsequent C attenuation circuit attenuates the output of the pilot signal and applies it as a subtraction circuit @bus subtraction input. The subtraction circuit [with] inputs the output of the A-to-DJ conversion circuit a2 and performs an operation using the output of the subtraction circuit (231) as a subtraction input, and calculates the output of the A-to-DJ conversion circuit a2 during playback. Only the reproduced output portion of the pilot signal recorded on the track is canceled.As illustrated on track T2 in FIG. Considering the case where (b) almost completely traces the track T2 to be reproduced and is the head of the household, its output (2) will be at least 10 times larger than the crosstalk component V from the adjacent track.(v>
10v) Therefore, if the output of the A-D converter circuit 0 is synchronously added N (16 times) in the 1st @2 adder circuit (110) (120) at the period of the pilot signal of the adjacent track, the pilot The output of the pilot signal f1 for the signal f2 is the level of the pilot signal f2 of the track being played back -J
W,v Pilot signal f10 level of adjacent track N,? Therefore, if V is approximately equal to VK or about a fraction of that, then N=16, 4V=4v<167, and the pilot signal f1 can be extracted sufficiently, but ■≧
In a case like 107, on the other hand, 4v≧407>167 and it becomes difficult to separate the pilot signal f1 of the adjacent track T1.

However, even in such a case, if the component of the pilot signal f2 of the track being played is always canceled as described above, it is possible to accurately separate the pilot signal f1 or f5 of the adjacent track. It is possible.

4201,) is the above-mentioned s1. This is a comparison circuit that receives the outputs of the second detection circuits (210) and (220). When the output level of the low-pass filter LLD is large and 8/N is good, the 181. Second synchronous addition circuit (110) (
120) can be used.

Next, the above 1. Second synchronous addition circuit (110) (120)
This will be explained with reference to the example of the implementation circuit shown in FIG. In this circuit, (111) (121) are adders, (112) (1
22) is a shift register.

(115) and (123) are AND gates. The adder (111) or (121) is the A-D converter circuit fi.
The shift register (112) is gated with a clear signal OLR, with the output Aij (IQ bit) of 3 being manually operated.
Alternatively, an addition operation is performed using the output (16 to 20 bits) of (122) as another input, and the result is sequentially input to the left register.

The left registers (112) and (122) are parallel registers of 16 to 20 pits with the longest register length of 5B (fo/f1), and the ratio f of each pilot frequency to the reference frequency.
Depending on O/f2, fo/f5, fO/f4,
Output terminal (C2) (C
3) and (C4), and is driven by the reference signal f01 as a clock pulse. This shift register 1t2)(
tz2) of each bit length output terminal (t, 1) (C2) (
``!5) The output generated in (14) is switched and selected by the multiplexer (114) (124) at a cycle of 1760 seconds in accordance with the pilot signal serving as the synchronous addition input, and is passed through the AND gate (115) C12S)'. The above adder (
111) (121) as an input.

The clear signal OLR applied to the control inputs of the AND gates (113) (123) is applied to the first addition period 1 of the pilot signals to be added, for example, 58° 50, 56 . It is a unit function that is 0 during each of the 40 cycles and becomes 1 after the second addition cycle. Therefore, the input signals Aij are sequentially and synchronously added at the addition period of the pilot signals of the designated adjacent trunks. In FIG. 6, Y(t)'t low-pass filter pauo output, Aij(all, al2.al
5-・・-・-*'l 1. a22. h25・-), the above Y(1) is sampled and digitized with a period of τo=convex using the reference signal fO, and the time t, 1j (tll, t1
2...t21. t22...).

T2) While playing the rack, the '@1 addition circuit (110)
In order to detect a pilot signal of one frequency f1, consider the case where the digital data Aij are synchronously added at a period of τ1 = ", (where 1/τo = 58), Ai j (t<j< 58) is the 181 country period (t1
It represents data of 1+(1-1)τ1≦t (period of ti1+1τ1).1 Synchronous addition in the present invention means executing the following equation by digital calculation.

11j= Σ aij ・・・・・・・・・(5) 1=
1 Here, N×τ1 means the period during which synchronous addition is performed. j is an integer satisfying 1≦j≦τ1/τ0. Now, the output Y (t) of the low-pass filter aυ is expressed as Y(t)=P1(t
)+P2(t)+P5(t)+P4+g(t)...
・・・・・・(6) [However, Pl(t)=lI Bin
(2*f 1 t+φ1)P 2(1')=E 28
i n (2πf2t+φ2)B3(t)=E5 El
in(2πf5z+φ3)B4(t)=E45in(2
πf4t+φ4) gl, l1i2. B! 1, B4 is the amplitude a of each pilot signal component, (t) is a noise component, and t is a positive integer. ], P1(t) is a periodic function of τ1, and P1(t)=P 1 (t+('-1)-
τ1] (where 1 is a positive integer), the above low-pass filter ano output y(t)oA-Dff conversion output Ai
When adding N times to j tr 1 a, the P1 pilot component and noise component are:

+(i-1), τ1] ......(7). That is, the pilot signal component P1 of one frequency f1 is multiplied by N, and the noise component, which is non-periodic or a non-integral multiple of the period τ1, is only 700 times larger at most.

The P1 pilot signal component can be accurately separated from the noise component.

Regarding the pilot signal P2 recorded on the video track T2 during scan playback, if τ1×NXf2 is an integer, the detected amplitude will be approximately zero, but if it is a non-integer, the detected amplitude will be at most 2. It will be about I x 2 K 2.

Similarly, for the pilot signal component P3 of the other adjacent track, if the A-D conversion output of Y (t) is added every 73 times N times, (1-1)・τ3] ... (8) becomes. Therefore, even if the head is running approximately in the center of video track 2 and B2 is 81 or several times B3, it is possible to extract minute pilot frequency components of adjacent tracks by synchronous addition when N=16 to 320. I can understand. In the above explanation, to simplify the explanation, τo ==
1 / f o, but there is no need to limit it in particular, and τ
It suffices if it is less than a fraction of 1. Therefore, the sampling frequency of AD conversion does not need to be fO, and may be selected to 1, for example, fO/2.

Next, the above 1. The second detection circuits (210) and (220) will be explained with reference to the circuit diagram in FIG. Both circuits have the same basic circuit configuration. This circuit has the above synchronous addition V
Output of the circuit.

A simple product-sum type correlation circuit is used as long as it can separate the desired pilot signal station 1=1 wave number component from Bjchi ΣAij. f7'l, ff12 correlation circuits (211) (221) are signals (sine waves) that serve as the reference for each pilot signal.

EmSin(2g−−0(j+/)) ・−・・・(9
1τm [where m is an integer from 1 to 4] is digitized data Kjl! The ROM (21!1) (223) written with the above data and the synchronous addition circuit (110) (2t4) (2
24) and an adder (215) (22) that adds the multiplication results.
5), the 110 M data KjJ and the synchronous Aij! :0IFI Seki (ifI
An operation is performed to calculate PJ=ZBj, xj/--401j=1 [where +N=τ1/τ01≦l≦M]. As described above (ROM (213') or.

If the reference signal written in (223) does not contain a DC component, the correlation value of the reference (sine wave) signal with respect to the DC component is 07, so the outputs of the adders (215) and (225) are o-t'h Comparison time vg2CfIa can be input, but 1 For example, if it is desired to perform all operations with positive numbers due to the system configuration, the analog value of the reference signal Kij will be [However, Bb is a DC component]. Therefore, depending on the magnitude of this DC component Bb, the correlation calculation value is determined by the input signal Bj and the reference signal KjI! Even if there is no similarity in waveform between the two, the calculation result (correlation value) becomes large due to the influence of the DC component, causing malfunction. In such a case, when l is varied in the range of 1 to M, the maximum and minimum values are the difference R=Pl! M-
P/m is taken, and DC components that appear to the same extent in the correlation calculation data are removed. (212) and (222) are DC component cancellation circuits that perform this calculation in conjunction with the correlation circuit.

When the output Bj of the first synchronous addition circuit (110) is applied as an input to the first detection circuit (210) K having such a correlation circuit, the multiplier (214) receives the data Bj.
For example, n read out at the same period as τ1.
The reference sine wave data Kj/ of the pilot signal P1 of oM (215) is read out and synchronously inputted as a result Bj
, KjJ is performed. The output of the multiplier (214) is transferred to the adder (215) and added up sequentially.

Σ Bj, KjI! It is extracted as an output.

j=1 Added to the comparison circuit circle.

In addition, when adopting a system in which all the various operations are performed using positive numbers, in consideration of the influence of the DC component on the correlation value, a DC component canceling circuit (212) (212) (2
22) is as described above. The above comparison times 1&2oTrc are the same as the above comparison times 1&2oTrc. Second correlation circuit (21
1) Synchronously compare the output of (221) as it is as a digital value, convert the result to D-A, and then amplify it to a predetermined level to drive the capstan motor for ATF control and change its rotational phase. The amount of displacement of the head in the track width direction is controlled by controlling the driving voltage of the bimorph for DTP control.

Next, another embodiment in which one circuit is simplified will be described with reference to FIG. In this embodiment, when the output of the playback head is stable for a relatively long period of time, both the synchronous addition circuits (110) (120) and the detection circuits (210) (220) in the 181 embodiment are used in common. The focus is on the fact that it can be used in parts.

The features of this circuit are that only one series of the synchronous addition circuit (510) and the detection circuit (320) is provided, and that one of the outputs of the detection circuit (520) is connected to the register memory (15).
0) and the output of the detection port @(320) and the memory (550) as inputs of the comparison circuit
The output of The configurations of the other low-pass filters (lυ and A-D conversion circuit fi2) are the same as those in the embodiment shown in FIG. 2, so a description thereof will be omitted except for comparing the figure numbers below.

(510) Synchronous addition circuit ...... (110) (5
11) Adder ・・・(111)(312) Shift register ・・・(112)(514) Multiplexer ・・・(114)(313) AND gate ・・・
・・・(115)(320) Detection circuit ・・・・・・(
210) (!l:50) Correlation circuit (21
1) (515) ROM ...... (215) (3
14) Multiplying circuit (214) (315) Adding circuit (215) (312) DC component cancellation circuit (212) With this configuration, A-D conversion circuit When the output Aij of tta is added to the synchronous addition circuit (511) as addition data, this data is 1 in the addition period related to the period 1/f1 of the pilot signal P1 to be detected recorded in one adjacent track. and N (for example, 16
After ~32) times synchronous addition, the next stage detection circuit <52O
) is added as input. The detection circuit 020) outputs a reference (sine wave) corresponding to the output of the synchronous addition circuit (510) and the pilot signal P1 read from the ROM (513).
A correlation calculation is performed between the signal data and the result is pz= Σ Bj , KjI! is written into the memory (350).

j = 1 When the N times of synchronous addition for detecting the pilot signal P1 is completed, the synchronous addition circuit (310) immediately adds the synchronous addition period to the pilot signal to be detected recorded in the other adjacent track T3. Switch to the addition period τ3 related to the period 1/f5 of P3 and add N (for example, 16 to 32
) times and the output is added as an input to the next stage detection circuit. The detection circuit (320) performs a correlation calculation between the output of the synchronous addition circuit and data of a reference (sine wave) signal corresponding to the pilot signal P3 successively output from the ROM, and compares the result with the above. The content of the memory (350) is applied to one input terminal of the circuit Ca at a timing that can be compared with the detection data of the pilot signal P1 component read from the memory (!+50) that is applied to the other input terminal. It will be rewritten one by one. That is,
For comparison, the detected data regarding the pilot signal P5 is written in place of the detected data regarding the pilot signal P1 which is successively output. Of course, sufficient memory capacity is provided for both pilot signals P1. The successive generation and convolution of detection data related to P3 may be performed independently. The playback track is T
1 or T3, and the adjacent track ('r2 or'
Even if the pilot signal recorded in I'4) is T2 or T4, there is no difference in principle, so the explanation will be omitted.

(F) Effects of the Invention According to the present invention, the entire circuit except the low-pass filter part can be digitalized, making it extremely easy to create a monolithic IC, reducing the mounting area with zero manufacturing steps, and reducing costs through mass production. You can expect it.

Furthermore, since the fundamental frequency fo in the reproduced signal can be used as a clock, it is not affected by VTR set compatibility, manufacturing variations, aging, and temperature fluctuations. Therefore, compared to the analog method, Q can be made higher, so fH
The effects of harmonic components can be reduced. Furthermore, since all processing is done digitally, no adjustments can be made, and the advantage is that it can be applied to both the NT80 system and the 00KR system.

[Brief explanation of drawings]

Figures 181 to 4 relate to the present invention, where Figure 1 is a block diagram of the main part and the second figure is a circuit diagram of the main part. FIG. 6 is an operating waveform diagram, and FIG. 4 is a main circuit block diagram of another embodiment. 5 and 6 relate to a conventional example, in which FIG. 5 is a recording pattern on a track and FIG. 6 is a main circuit diagram. Uυ...Low pass filter, a'a...A-D conversion circuit, ■...Cancel circuit, (110) (120)
...First and second synchronous addition circuits, (210) (220)
...1st @2 detection circuit, (20D...comparison circuit. Applicant: Sanyo Electric Co., Ltd., agent, patent attorney: Shizuo Sajo

Claims (1)

[Claims] (1) Reproduction by a device that reproduces a recording medium in which pilot signals of different frequencies are sequentially written along with the main signal on multiple parallel tracks that are densely recorded in a state where crosstalk between adjacent tracks is unavoidable due to mistracking. The tracking error detection circuit of the head includes an A-D conversion circuit that samples the pilot signal extracted from the reproduced signal using a reference signal with a frequency sufficiently lower than that frequency and converts it into a digital signal, and reproduces the digital signal output of the circuit. 181 synchronous addition circuit that performs synchronous addition N (N>10) times in synchronization with the period of the pilot signal recorded on the track to be recorded, a circuit that attenuates the output of this circuit to 100, and the output of this circuit that A cancellation circuit that subtracts from the output of the A-D conversion circuit, a two-series synchronous addition circuit that adds the output of this circuit in synchronization with the period of the pilot signal on the adjacent track, and the output of each of these addition circuits are compared. A tracking error detection circuit including a comparison circuit.