JPS60237374A - Wire harness tester - Google Patents

Abstract

PURPOSE:To elevate the working efficiency with a reduced processing time by sending a signal to perform a reading of a memory circuit for setting the transfer of the normal connection mode synchronizing the changeover of switching circuits for checking with a counter circuit which steps by a clock signal. CONSTITUTION:A start signal P0 is applied to a startup signal input terminal 18 with a start key to open a gate circuit 17. A clock signal P1 is applied to a counter circuit 20 to advance it by one step with each clock signal. With each step, a reading address for reading a memory circuit 21 for setting the transfer of the normal connection mode is advanced by one at a time to read out the contents thereof while the switching circuits 15 for checking are changed over in response to a switching signal of the counter circuit 20. At each time of the operation, the output of the memory circuit and inputs from the switching circuits 15 for checking are applied to a comparison circuit 22 to collate.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object 1 of the Invention] (Field of Industrial Application) The present invention relates to a continuity testing device for wire harnesses used, for example, in automobiles and electrical equipment.

(Prior art) Connection lines that connect various devices [for example, connections between devices such as headlights mounted on automobiles, taillights, and other electronic devices and power sources, or between devices To make the connections, as shown in Figure 1, make a so-called wire harness (1) that is wired according to the installation location of various devices, and then connect it to the vehicle body (2) that will be sent in the assembly line. After fixing it in a predetermined position, its input and output ends are connected using a carp lid (3) or the like. In the wire harness, in order to ensure reliability of operation, it is important that each connection line (4) is properly connected to a connector for connection to a device without any errors.

However, the number of connection lines (4) tends to increase more and more as automobiles and the like become more sophisticated. For this reason, for example, Figure 2 (
As shown in a), ■l~01 of the connector contact
Although it is a normal connection state that 3 to e3 are connected as a single line by the connection line (4□) (43), and the line between 02 and 02 is an empty line, as shown in Figure 2 (1) ) as shown in 0
Even if it is rare, it is impossible to avoid the occurrence of an erroneous connection such as a blank line between 3 and 03.

Therefore, in order to automatically, quickly, and reliably discover connection errors and make repairs, a continuity testing device, so-called wire harness checker, as shown in FIG. 3 is generally used. This device consists of: ■ Connector group (5), that is, the input end of the wire harness 0) placed on the test stand (6) and connected to the connector (3) provided on the test stand (6);
Connect the test relay wire (6
) Connector (5□) (52)...
・A connector group (5) consisting of (5n), ■ A microcomputer (7) (referred to as the lower microcomputer) which is a processing circuit, for example, an address designation keyboard (8) corresponding to the contact number of the carp lid, For example, by pressing [1] and then pressing the single line connection key (9), specify the address and set the connection status to 1'', for example, by pressing [2] on the keyboard (8) and then pressing the blank line key aα 1j by pressing , specify the address, and select the address shown in Fig. 2 (
Sending switching commands for the write/read memory circuit Qll (RAM) in which the normal connection state shown in a) is set, and the checking switching circuit group Q5) to be described later, the setting contents of the memory 0D and the checking switching circuit group 0S The memory circuit 0 is provided with a read-only memory circuit 0 in which an operation management program for performing a program step-a-nob operation for checking the output of the controller is set. The operation starts when the start key is pressed to 0, and when an error occurs through verification, the operation is temporarily stopped and the return key is pressed.
When 141 is pressed, the microcomputer (7) starts operation again from the beginning, and the ■ check switching circuit group α9, for example, as shown in Fig. 4, connects the ■ side contacts of the connector group (5) to the electric ht, E At the same time, the switching transistor Tr□ connected to the negative polarity of the switching transistor Tr□ and the e side contact are connected to the positive polarity side of the power supply E via the switching transistor Tr2, and at the same time, the potential appearing at the ○ side contact is set to '1''.
Check switching circuits (15□) (152) each consisting of a level detector that detects a signal of O"°.
...(15n) is provided. Then, the switching transistors Tr□T are sequentially turned on in the order of ■1-el and ■2-02 contacts by a switching signal from the microcomputer (7), so that current flows through each connection line. As shown in Fig. 2 (b), when the ■1 to ○l contacts are connected by a single wire, the level detector indicates °“1”, ■2 to e2,
■ Check phase switching filH group housing 9, which sends an "O" signal when the line is empty like 3 to 03, ■ Display circuit α
e, for example, according to a command from the microcomputer (7)), steps in synchronization with the switching of the checking switching circuit group αω, and sequentially
and ○Display the contact number, for example in Figure 2 fa
Although the single wire connection state between 03 and 03 as shown in Figure 1 is a normal connection state, it is a blank wire as shown in Figure 2 (b) and the check switching circuit (153) When the output is ○, the microcomputer stops due to verification operation ('7)
A display circuit 06) that stops advancing in response to stopping the transmission of commands, displays the contact number in which the abnormality has occurred, and generates an abnormal sound at the same time; A series of determination operations are performed to check continuity between wires and wires.

(Problems with the prior art) However, as described above, the output of the check switching circuit +151 and the settings of the memory circuit Uυ for setting the normal connection mode are collated and analyzed by a program (software) to determine pass/fail. , the time required for the program step by the operation management program setting memory circuit a2 is required for each contact. Therefore, especially the wire harness (1)
If there are many connection lines, the time required for processing will increase, reducing work efficiency.

[Structure of the invention]

(Structure and operation for solving problems) The present invention is characterized by providing the continuity test device shown in FIG. 3 with an external circuit shown in the example of the device in FIG. The checking operation is performed by hardware, and the time required for the program step is eliminated by only the switching time of the switching circuit group for checking. That is, the settings of the normal connection mode setting memory circuit 0υ are analyzed so that they can be easily compared for each connection line, and the normal connection mode transfer setting memory circuit (2+1 and It starts with the start key, advances at the required step speed, and sends out a switching signal for the checking switching circuit group o9, and in synchronization with this, a readout signal for the memory contents of the normal connection mode transfer setting memory circuit (211) is sent out. and display circuit Ql
A counter circuit (a) that sends out a step signal of No. 19, and a readout output of a memory circuit for setting normal connection mode transfer;
A comparison circuit (external circuit (B) consisting of 2z is installed in the continuity test equipment section) that compares and verifies the output of the switching circuit group for checking, and this is used only to set the transfer contents in the normal connection mode, compared to the conventional Instead of software processing, hardware processing is used to check the numbers, thereby reducing the check time. This will be explained in detail next.

In Figure 6, (/J indicates a continuity test device, and in Figure 3 (
Therefore, as mentioned above, the wire bars (1), the connection coil/lid group (5), the microcomputer (7),
), a check switching circuit 05), a display circuit Q5j, etc.

(Bl is the main circuit of the device of the present invention, of which α is a gate circuit, oQ is a start signal input terminal, o9 is a clock signal input terminal, (A) is a presettable binary counter circuit, and eυ is a Normal connection mode transfer setting memory circuit, @
is a comparison circuit, and the following two circuits operate as follows.

The normal connection mode transfer setting memory circuit c! 1), give an address designation signal, read and write signals, convert the contents of the memory circuit 01) into a form that is easy to compare for each connection line by the microcomputer (7), and transfer it to the memory circuit eυ. Set. At the same time, the switching circuit group for checking (one switching circuit and the stepwise circuit of the display circuit 0θ) is disconnected from the memory circuit 01 by the switch S1.
Connect to. Further, the required initial address designation number and the required final address designation number are set in the counter circuit (2) from the memory area of the normal connection mode transfer setting memory circuit CH1+ to complete the preparation. After that, a start signal P is input to the start signal input terminal 0ε by the start key. is added to open the gate circuit αη. Then 5
The clock signal P1 applied to the counter circuit ■
is added to and increments it by one step for each clock signal. Then, at each step, the read address of the normal connection mode transfer setting memory circuit 01) is advanced by one address and its contents are read out, and at the same time, the counter circuit (2
), the checking switching circuit group (151) is switched. Each time, the output of the memory circuit QIl and the input from the checking switching circuit group 051 are applied to the comparator circuit 051 for comparison. If there is no check, a completion signal P is sent to notify completion of the check, and at the same time, the display circuit 06) displays the final contact number. When an abnormality occurs, the comparator circuit C2 applies an abnormality signal P to the gate circuit αη to close the gate and stop sending out the clock signal. Therefore, the counter circuit f20)
stops advancing, switches the check switching circuit and stops the display circuit Q61, and the display circuit α6) displays the contact number where the abnormality has occurred.

(Effects of the Invention) As described above, the present invention does not require verification by a microcomputer, which requires time for program steps.
A new external circuit attached to the continuity test equipment is used to perform hardware verification. Therefore, there is no need for the time required for program steps as in the past, and the processing time is determined only by the step speed of the counter circuit based on the clock signal. The faster the speed, the shorter the processing time. In addition, since the microcontroller is idle while the verification operation is being performed, during this time it is necessary to set the normal connection mode to the memory circuit for setting the normal connection mode in order to test the next wire harness with a different connection state. , the normal connection mode transfer setting memory circuit can be set. Therefore, this also reduces the processing time, speeds up the continuity check, and improves work efficiency.

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram of the wire hardware, Figure 2 (al(b)
1 is a diagram showing an example of a normal connection state and an irregular connection state of a wire harness, FIG. 3 is a circuit diagram of a conventional continuity test device, FIG. 4 is a check switching circuit diagram, and FIG. 5 is a processing flow diagram.
FIG. 6 is a diagram showing an example of an apparatus for implementing the present invention. (11...Wire harness, (2)...■Automobile, (3)...Connector, (4)...Connection wire,
(6)...Wire harness test stand, (A+...
Continuity test device, (5)... Connector group, (51)
(52) - (5n)... Line connector, (7)... Microcomputer, (8)... Keyboard for address specification, (9)... Single wire connection key, αO)...
...Empty wire connection key, 01)...Memory for setting regular connection mode, θ2...Memory circuit for setting operation management program, θ3...Start key, 04)...Return key, 09...Check switching circuit group, (15□)(152)-(15n)...Check switching circuit, 06)...Display circuit, (B)...
External circuit, On...Gate circuit, Q81...
Start signal input terminal, Q-reference circuit. Representative Patent Attorney Kano Inuzuka'I#J5Figure 6

Claims (1)

[Claims] A processing circuit equipped with a memory circuit for setting an operation management program and a memory circuit for setting a normal connection mode, and its operation management program, are switched to sequentially apply current to the connection line circuit under test and output a signal indicating the presence or absence of the connection state. The checking switching circuit group to send out and its output are sequentially compared with the normal connection state of the memory circuit for setting the normal connection mode according to the commands of the memory circuit for setting the dual operation management program, and the connection line circuit under test is checked. In a continuity testing device for detecting abnormalities, a normal connection mode in which the setting output of the memory circuit for setting the heavy-fire connection mode is analyzed for each connection line and transferred and stored: 'The memory circuit for transfer setting and the start switch 1) a counter circuit that sends out a signal that is incremented by the sent clock signal and reads out the memory circuit for setting the normal connection mode transfer in synchronization with the switching of the checking switching circuit group, and the normal connection; A wire high speed test device characterized in that it is equipped with an external circuit consisting of a comparison circuit that compares and matches the readout output of the mode transfer setting memory circuit and the output of the check switching circuit, thereby reducing processing time. .