JPS60236246A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60236246A
JPS60236246A JP9371484A JP9371484A JPS60236246A JP S60236246 A JPS60236246 A JP S60236246A JP 9371484 A JP9371484 A JP 9371484A JP 9371484 A JP9371484 A JP 9371484A JP S60236246 A JPS60236246 A JP S60236246A
Authority
JP
Japan
Prior art keywords
layer
oxide film
film
etching
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9371484A
Other languages
Japanese (ja)
Inventor
Atsuhiko Menju
毛受 篤彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP9371484A priority Critical patent/JPS60236246A/en
Publication of JPS60236246A publication Critical patent/JPS60236246A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To form an insulating film for separating elements with necessary thickness only on a necessary region by forming the insulating film for separating by a selective oxidizing method, and removing by etching an unnecessary portion of bird beak. CONSTITUTION:An oxide film 12 for separating is formed by a selective oxidizing method, and a polysilicon film 16, a nitride film 17 and an organic polymer film 18 are laminated. The layer 18 is etched, the layer 17 is exposed at the portion of the separating region X, and the portion of an element region Y remains masked with the layer 18. The exposed portion of the layer 17 is etched, and the layer 16 is exposed. The layer 18 is removed, and a mask oxide film 19 is grown on the exposed portion of the layer 16. The portions of the layers 17, 18 are removed by etching. The film 19 and the bird beak 15' of the film 12 are removed by etching. Separating oxide film 15 remains only at the portion of the separating region X, and the bird beak does not exist on the element region Y.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置の製造方法、特に素子分離用の絶縁
膜の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing an insulating film for element isolation.

〔発明の技術的背景〕[Technical background of the invention]

半導体装置の構成要素である各素子の間は、一般に厚い
酸化膜によって絶縁分離される。この厚い酸化膜の製造
方法の1つとして、半導体基板全面に厚い酸化膜を形成
した後、素子領域の部分の酸化膜を取除く方法がある。
Each element that is a component of a semiconductor device is generally insulated and isolated by a thick oxide film. One method for manufacturing this thick oxide film is to form a thick oxide film over the entire surface of the semiconductor substrate and then remove the oxide film in the element region.

しかしこの方法では分離領域にいわゆるチャネルカット
領域を形成しにくい欠点があるため、最近は選択酸化法
が一般に用いられる。
However, this method has the disadvantage that it is difficult to form a so-called channel cut region in the isolation region, so recently, a selective oxidation method is generally used.

従来の選択酸化法による絶縁膜の製造方法を第3図を用
いて簡単に説明する。まず第3(a)図に示すように、
半導体基板11上に緩衝酸化膜12を形成し、更にその
上に窒化膜13を形成する。続いて分離領域とたる部分
の窒化[13に開孔部14を設け(第3(b)図)、こ
の開孔部14を酸化することにより厚い分離用酸化膜1
5を形成する(第3(0)図)。
A method of manufacturing an insulating film using a conventional selective oxidation method will be briefly explained using FIG. First, as shown in Figure 3(a),
A buffer oxide film 12 is formed on a semiconductor substrate 11, and a nitride film 13 is further formed thereon. Subsequently, an opening 14 is provided in the nitriding region and the barrel portion (FIG. 3(b)), and the opening 14 is oxidized to form a thick isolation oxide film 1.
5 (Figure 3(0)).

第3(i図および第3(C)図で、Xと示した領域が分
離領域、Yと示した領域が素子領域である。この方法の
特徴は、素子領域内に管でバーズビーク15’と呼ばれ
るJ−1い酸化膜1−が入り込む点である。
In FIGS. 3(i) and 3(C), the region indicated by This is the point where a thin oxide film 1- called J-1 enters.

〔背景技術の問題点〕[Problems with background technology]

LSI素子は、年々高集積化の一途をたどっており、例
えばMO日メモリの典型であるダイナミックRAMでは
わずか2年で2倍の集積度向上がなされている。このよ
うな実情からLSIの高集積化を図るために、素子自身
の縮小化たけでなく素子間の分離領域の縮小化も必要と
なってくる。
LSI devices are becoming more and more highly integrated year by year, and for example, the integration of dynamic RAM, which is a typical type of MO memory, has been doubled in just two years. Under these circumstances, in order to achieve high integration of LSIs, it is necessary not only to reduce the size of the elements themselves but also to reduce the isolation regions between the elements.

しかし前述した選択酸化法では、バーズビークIFI’
が素子領域にまで入り込み、実質的に分離領域が拡大す
ることになる。
However, in the selective oxidation method described above, the bird's beak IFI'
penetrates into the element region, substantially expanding the isolation region.

一般に分離領域形成後のLSIの各製造プロセスにおい
ては、様々なエツチングプロセスが存在し、このエツチ
ングプロセスは集積度が向上する程通常多くなる。従っ
て、分離領域に形成された絶縁膜がこれらのエツチング
プロセスで侵蝕されることを予定して、集積度が高くな
ればなる程、初めに形成される絶縁膜を厚くする必要が
生じる。
Generally, there are various etching processes in each LSI manufacturing process after the isolation region is formed, and the number of etching processes usually increases as the degree of integration increases. Therefore, in anticipation of the insulating film formed in the isolation region being eroded by these etching processes, the higher the degree of integration, the thicker the insulating film initially formed becomes.

ところが絶縁膜を厚くするとバーズビークの侵入部分も
増加し、高集積化のだめの分離領域の縮小に逆行する結
果となる。
However, when the insulating film is made thicker, the portion of the bird's beak that penetrates also increases, which goes against the reduction in the isolation region required for higher integration.

あらかじめバーズビークの発生を予定して開孔部14を
小さくしておく方法も考えられるが、開化部14が小さ
くなると絶縁膜形成のだめの酸化過程が十分行われず、
厚い酸化膜を形成させることが困離となる。
A method of making the openings 14 smaller in advance to anticipate the occurrence of bird's beaks may be considered, but if the openings 14 become smaller, the oxidation process required to form the insulating film will not take place sufficiently.
It becomes difficult to form a thick oxide film.

以上のように従来の選択酸化法には、高集積化を行9上
での欠点があった。
As described above, the conventional selective oxidation method has the disadvantage that it is difficult to achieve high integration on the row 9.

〔発明の目的〕[Purpose of the invention]

そこで本発明は、必要な厚みをもった素子分離用絶縁膜
を必要な領域にのみ形成することのできる半導体装置の
製造方法を提供することを目的とする。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that can form an element isolation insulating film having a necessary thickness only in a necessary region.

〔発明の櫃要〕[A chest of inventions]

本発明の特徴は、分離用絶縁膜を有する半導体装置の製
造方法において、従来の選択酸化法により分離用絶縁膜
を形成させた後、該分離用絶縁膜の必要な部分のみをマ
スクし、バーズビーク等の不発な部分をエツチングによ
り除去し、必要な領域にのみ絶縁膜を形成させ、半導体
装置の高集積化を図った点にある。
A feature of the present invention is that in a method for manufacturing a semiconductor device having an isolation insulating film, after forming an isolation insulating film by a conventional selective oxidation method, only necessary portions of the isolation insulating film are masked, and bird's beaks are formed. The semiconductor device is highly integrated by removing unexploded parts such as etching by etching and forming an insulating film only in necessary areas.

〔発明の実施例〕[Embodiments of the invention]

以下木琴間を図示する実施例に基づいて詳述する。オず
従来の選択酸化法によって第a (a)〜(c)図に示
すように分離用酸化膜を形成させる。第1(a)図は第
3(c1図と同じ図であり、ここまでの工程については
説明を省略する。続いて窒化膜13を剥離した後、分離
用酸化膜12上にポリシリコン膜16を例えば4000
λ積層させ、第1の層とし新たな窒化膜17を例えば1
000λ積層させ第2の層とし、更にその上から有機高
分子膜18を積層させ第3の層とする。ここまでの工程
を第1(b)図に示す。なお第3の層の表面は平面にな
るようにする。これは例えば、有機高分子の溶液を第2
の層の上に流しこみ、半導体基板を回転させながら溶媒
を蒸発させることによって実現できる。第1の層16と
して本実施例ではポリシリコン膜を用いているが、これ
は分離用酸化膜12とエツチング特性の異なる物質であ
れば他のものを用いてもかまわない。第2の層17とし
ては窒化膜を用いているが、これは耐酸化性があり、か
つ、第1の層16とエツチング特性の異なる物質でおれ
ば他のものを用いてもかまわない。また、第3の層18
としては、有機高分子膜を用いているが、これは第2の
層17とエツチング特性が異なり、かつ上側表面が平面
になるように積層することが可能な物質(例えばスピン
オングラスのよう表無機材料)であれば、他のものを用
いてもかまわない。
A detailed description will be given below based on an example illustrating a xylophone. First, a conventional selective oxidation method is used to form an isolation oxide film as shown in FIGS. FIG. 1(a) is the same diagram as FIG. For example, 4000
λ is laminated, and a new nitride film 17 is formed as the first layer, for example, by one layer.
000λ is laminated to form a second layer, and an organic polymer film 18 is further laminated from above to form a third layer. The steps up to this point are shown in FIG. 1(b). Note that the surface of the third layer is made to be flat. This means, for example, that a solution of an organic polymer is
This can be achieved by pouring the solvent onto the semiconductor substrate and evaporating the solvent while rotating the semiconductor substrate. Although a polysilicon film is used as the first layer 16 in this embodiment, other materials may be used as long as they have etching characteristics different from those of the isolation oxide film 12. Although a nitride film is used as the second layer 17, other materials may be used as long as they are oxidation resistant and have etching characteristics different from those of the first layer 16. In addition, the third layer 18
For example, an organic polymer film is used, which has different etching characteristics from the second layer 17 and can be layered so that the upper surface is flat (for example, an inorganic material such as spin-on glass). Other materials may be used as long as the materials are suitable.

続いて飴3の層18をR工E (Reactive I
onEtching ) 等の異方性エツチングでエツ
チングを行い、第2の屓17を開孔部14と同程度露出
させる( tJ=’、 1 (c)図)。即ち、分離領
域Xの部分は第2のW117が露出し、素子領域Yの部
分は第3の層18以上の工程は容易に行いうる。
Next, layer 18 of candy 3 with R (Reactive I)
Etching is performed using anisotropic etching such as onEtching) to expose the second protrusion 17 to the same extent as the opening 14 (tJ=', Figure 1(c)). That is, the second W 117 is exposed in the isolation region X, and the process for forming the third layer 18 and above can be easily performed in the element region Y.

次に残った第3の層18をマスクとして用い、第2の1
117の露出部分をエツチングし、第1の層16を露出
させる。続いて残っていた第3の層18をすべて除去す
る。更に、第1の層16の露出した部分にマスク用酸化
膜19を例えば2000λ成長させる(第1(d)図)
Next, using the remaining third layer 18 as a mask, the second layer 18 is
The exposed portions of 117 are etched to expose first layer 16. Subsequently, all remaining third layer 18 is removed. Furthermore, a masking oxide film 19 is grown to a thickness of, for example, 2000λ on the exposed portion of the first layer 16 (FIG. 1(d)).
.

続いて第2の層17の残った部分をエツチングにより除
去し、マスク用酸化膜19をマスクとして第1の1#1
6のマスクされていない部分をエツチングにより除去す
る。最後にマスク用酸化膜19と分離用酸化膜のバーズ
ビーク15°の部分をエツチングにより除去する。
Subsequently, the remaining portion of the second layer 17 is removed by etching, and the first 1#1 is etched using the mask oxide film 19 as a mask.
The unmasked portions of No. 6 are removed by etching. Finally, the bird's beak 15° portion of the mask oxide film 19 and isolation oxide film is removed by etching.

以上の工程終了後の状態を第1(e)図に示す。分離用
酸化膜15は第1の層16とともに分離領域Xの部分の
み残り、素子領域!にはバーズビークが存在しなくなり
素子配置に有効に利用できる。また第1の層16が分離
用酸化膜上に残されているため、これ以後の素子形成工
程において、エツチング等による分離用酸化膜の俊敏を
防ぐことができる。
The state after the completion of the above steps is shown in FIG. 1(e). The isolation oxide film 15 remains only in the isolation region X together with the first layer 16, leaving only the element region! Bird's beak no longer exists and can be effectively used for element arrangement. Furthermore, since the first layer 16 remains on the isolation oxide film, it is possible to prevent the isolation oxide film from becoming fragile due to etching or the like in the subsequent element formation process.

例えば第2因で面積10μm8のセルキャパシタ部10
0を素子領域として設計した場合、従来の方法では分離
用酸化膜の厚みを0.8μ市として形成させると、バー
ズビークの侵入により、実際の素子領域110は面積的
5.6μmlと減少してしまり。本発明による方法では
実際の素子領域は設計当初の素子領域100と同面積と
なり、従来の方法に比べて1.79倍の素子領域を確保
することができる。
For example, due to the second factor, a cell capacitor portion 10 with an area of 10 μm8
If 0 is designed as the element region and the isolation oxide film is formed with a thickness of 0.8 μm using the conventional method, the actual device region 110 will be reduced in area to 5.6 μm due to the invasion of bird's beaks. . In the method according to the present invention, the actual device area has the same area as the device area 100 at the beginning of the design, and it is possible to secure a device area that is 1.79 times larger than the conventional method.

従来は設計時にバーズビーク侵入による素子領域の減少
を予想して、いわゆる変換差をもったマスクを用いるこ
とが行われていたが、本発明によればそのようなことは
必要なくなり、集積度を向上させることができるだけで
なく、設計も非常に容易になる。
Conventionally, masks with so-called conversion differences were used in anticipation of the reduction in device area due to bird's beak invasion during design, but with the present invention, this is no longer necessary and the degree of integration is improved. Not only can it be done easily, but it can also be designed very easily.

なお、本発明の付加的な効果として、第3の層のエツチ
ング量をコントロールして、第2の層の露出面積を増減
することにより、最終的な分離領域の面積を増減するこ
ともできる。これは同じマスクを用いて種々の面積をも
った分離領域を形成させる場合に便利である。
As an additional effect of the present invention, the area of the final separation region can be increased or decreased by controlling the amount of etching of the third layer and increasing or decreasing the exposed area of the second layer. This is useful when using the same mask to form isolation regions with different areas.

〔発明の効果〕〔Effect of the invention〕

以上のとおり本発明によれば、半導体装置における素子
分離用絶縁膜の不要な部分であるバーズビークを除去す
るようにしたため、必要な厚みをもった絶縁膜を必要な
領域にのみ形成させることができ、より集積度を増加さ
せることができる。
As described above, according to the present invention, since the bird's beak, which is an unnecessary part of the insulating film for element isolation in a semiconductor device, is removed, an insulating film having the necessary thickness can be formed only in the necessary area. , the degree of integration can be further increased.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に係る半導体装置の製造方法の工程説明
図、第2図は本発明に係る方法と従来の方法とで製造さ
れた半導体装置の比較説明図、第3図は従来の半導体装
置の製造方法の工程説明図である。 11・・・半導体基板、12・・・緩衝酸化膜、13・
・・窒化膜、14・・・開孔部、15・・・分離用酸化
膜、16・・・第1の層(ポリシリコン膜)、17・・
・第2の層(窃化騨)、18・・・第3の層(有機高分
子膜)、19・・・マスク用酸化膜、100・・・設計
時の素子領域、101・・・バーズビークの俊敏受けだ
後の素子領域。 出願人代理人 猪 股 清 61 口 62 図 も3 閉
FIG. 1 is a process explanatory diagram of the method for manufacturing a semiconductor device according to the present invention, FIG. 2 is a comparative diagram of semiconductor devices manufactured by the method according to the present invention and a conventional method, and FIG. 3 is a diagram explaining the process of manufacturing a semiconductor device according to the present invention. It is a process explanatory diagram of the manufacturing method of a device. 11... Semiconductor substrate, 12... Buffer oxide film, 13.
...Nitride film, 14...Opening portion, 15...Isolation oxide film, 16...First layer (polysilicon film), 17...
・Second layer (sealed), 18... Third layer (organic polymer film), 19... Oxide film for mask, 100... Element area at the time of design, 101... Bird's beak The element area after the agile reception. Applicant's agent Kiyoshi Inomata 61 Kuchi 62 Figure 3 Closed

Claims (1)

【特許請求の範囲】 1、半導体基板上に緩衝用酸化膜、およびその上に耐酸
化性膜を形成する工程と、 前記耐酸化性膜に開孔部を設ける工程と、前記半導体基
板の前記開孔部に対応した部分を酸化し、前記緩衝用酸
化膜の前記開孔部に対応した部分の膜厚を増加させて分
離用酸化膜とする工程と、 前記耐酸化性膜を除去する工程と、 前記分離用酸化膜上にのみ、前記分離用酸化膜とエツチ
ング特性が異なる物質からなるマスク層を形成する工程
と、 前記マスク層を利用して、前記緩衝用酸化膜をエツチン
グにより除去する工程と、 を有することを特徴とする半導体装置の製造方法。 2、半導体基板上に緩衝用酸化膜、およびその上に耐酸
化性膜を形成する工程と、 前記耐酸化性膜に開孔部を設ける工程と。 前記半導体基板の前記開孔部に対応した部分を酸化し、
前記緩衝用酸化膜の前記開孔部に対応した部分の膜厚を
増加させて分離用酸化膜とする工程と、 前記耐酸化性膜を除去する工程と、 前記緩衝用酸化膜および前記分離用酸化膜上に、これら
の酸化膜とエツチング特性が異なる物質からなる第1の
層を形成する工程と、前記第1の層上に、前記第1の層
とエツチング特性が異なり、かつ、耐酸化性の物質から
なる第2の層を形成する工程と、 前記第2の層上に、前記第2の層とエツチング特性の異
なる物質からなる第3の層を上側表面が平面となるよう
に形成する工程と、前記第3の層をエツチングして一部
分を取除き、前記第2の層の一部分を露出させる工程と
、前記第2の層のうち、露出した部分をエッチングして
敗除き、前記第1の層の一部分を露出させる工程と、 前記第3の層のうち残っている部分を取除く工程と、 前記第1の層の露出した部分にマスク用酸化膜を形成す
る工程と、 前記第2の層のうち残っている部分をエツチングにより
取除く工程と、 前記第1の層のうち、前記マスク用酸化膜が形成されて
いない部分をエツチングにより取除く工程と、 前記緩衝用酸化膜および前記分離用酸化膜のうち、前記
マスク用酸化膜が形成されていない部分をエツチングに
より取除く工程と、を有することを特徴とする半導体装
置の製造方法。 3、半導体装置の全製造プロセス終了後にも、第1の層
が残るように、十分な厚みをもって前記第1の層を形成
することを特徴とする特許請求の範囲第2項記載の半導
体装置の製造方法。 4、第1の層がポリシリコンからなることを特徴とする
特許請求の範囲第2項または第3項記載の半導体装置の
製造方法。 5、第2の層が窒化シリコンからなることを特徴とする
特許請求の範囲第2項乃至第4項のいずれかに記載の半
導体装置の製造方法。 6、第3の層が有機高分子からなることを特徴とする特
許請求の範囲第2項乃至第5項のいずれかに記載の半導
体装置の製造方法。
[Claims] 1. A step of forming a buffer oxide film on a semiconductor substrate and an oxidation-resistant film thereon, a step of providing an opening in the oxidation-resistant film, and a step of forming the buffer oxide film on the semiconductor substrate. a step of oxidizing a portion corresponding to the opening to increase the film thickness of the portion of the buffer oxide film corresponding to the opening to form an isolation oxide film; and a step of removing the oxidation-resistant film. forming a mask layer made of a material having etching characteristics different from those of the isolation oxide film only on the isolation oxide film; and removing the buffer oxide film by etching using the mask layer. A method for manufacturing a semiconductor device, comprising the steps of: 2. A step of forming a buffer oxide film on a semiconductor substrate and an oxidation-resistant film thereon; and a step of providing an opening in the oxidation-resistant film. oxidizing a portion of the semiconductor substrate corresponding to the opening;
a step of increasing the thickness of a portion of the buffer oxide film corresponding to the opening to form an isolation oxide film; a step of removing the oxidation-resistant film; and a step of removing the buffer oxide film and the isolation film. forming a first layer on the oxide film made of a material that has etching properties different from those of the oxide films; forming a third layer made of a material having etching properties different from those of the second layer on the second layer so that the upper surface thereof is flat; etching a portion of the third layer to expose a portion of the second layer; etching and removing the exposed portion of the second layer; exposing a portion of the first layer; removing the remaining portion of the third layer; forming a masking oxide film on the exposed portion of the first layer; a step of removing by etching the remaining portion of the second layer; a step of removing by etching a portion of the first layer where the mask oxide film is not formed; and the buffer oxide film. and a step of removing by etching a portion of the isolation oxide film where the mask oxide film is not formed. 3. The semiconductor device according to claim 2, wherein the first layer is formed to have a sufficient thickness so that the first layer remains even after the entire manufacturing process of the semiconductor device is completed. Production method. 4. The method of manufacturing a semiconductor device according to claim 2 or 3, wherein the first layer is made of polysilicon. 5. The method for manufacturing a semiconductor device according to any one of claims 2 to 4, wherein the second layer is made of silicon nitride. 6. The method for manufacturing a semiconductor device according to any one of claims 2 to 5, wherein the third layer is made of an organic polymer.
JP9371484A 1984-05-10 1984-05-10 Manufacture of semiconductor device Pending JPS60236246A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9371484A JPS60236246A (en) 1984-05-10 1984-05-10 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9371484A JPS60236246A (en) 1984-05-10 1984-05-10 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60236246A true JPS60236246A (en) 1985-11-25

Family

ID=14090088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9371484A Pending JPS60236246A (en) 1984-05-10 1984-05-10 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60236246A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5234859A (en) * 1988-06-28 1993-08-10 Mitsubishi Denki Kabushiki Kaisha LOCOS type field isolating film and semiconductor memory device formed therewith

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5234859A (en) * 1988-06-28 1993-08-10 Mitsubishi Denki Kabushiki Kaisha LOCOS type field isolating film and semiconductor memory device formed therewith

Similar Documents

Publication Publication Date Title
US5998290A (en) Method to protect gate stack material during source/drain reoxidation
US6579757B2 (en) Method for fabricating semiconductor device which prevents gates of a peripheral region from being oxidized
US5700733A (en) Semiconductor processing methods of forming field oxide regions on a semiconductor substrate
US5512509A (en) Method for forming an isolation layer in a semiconductor device
JPS6228578B2 (en)
US4564394A (en) Preventing lateral oxide growth by first forming nitride layer followed by a composite masking layer
US4435446A (en) Edge seal with polysilicon in LOCOS process
JPS62290146A (en) Manufacture of semiconductor device
US4030952A (en) Method of MOS circuit fabrication
JP2531481B2 (en) Method for manufacturing semiconductor device
JPS60236246A (en) Manufacture of semiconductor device
JP2822211B2 (en) Method for manufacturing semiconductor device
JPS63204746A (en) Manufacture of semiconductor device
US6420248B1 (en) Double gate oxide layer method of manufacture
JPS6083331A (en) Forming method of groove
JPS59104140A (en) Manufacture of semiconductor device
US6136671A (en) Method for forming gate oxide layers
JP2558289B2 (en) Method of forming altered layer
JPS59181639A (en) Manufacture of semiconductor device
KR0124637B1 (en) Method of forming the isolation on semiconductor device
US20030030101A1 (en) Semiconductor device and manufacturing method thereof
JP2961860B2 (en) Method for manufacturing semiconductor device
KR940003219B1 (en) Element segregation method for semiconductor memory device
JPH028451B2 (en)
JPS61219148A (en) Manufacture of semiconductor device