JPS60236193A - Memory cell circuit - Google Patents

Abstract

PURPOSE:To obtain an associative memory cell which has less number of constituting transistors and acts at a high speed by providing a sensor line where the connection to the ground in the same direction as that of a word line is controlled by serial transistors acting in correspondence to a bit line potential and storage contents of a memory cell. CONSTITUTION:A sensor line (d) is provided whose potential is set to a high level in the same direction as that of a word line (c) of an associative memory cell Mo formed by inverters I1 and I2 having two sets of nodes X is and Y, etc. Between said line (d) and a ground transisitors Q3 and Q5 controlled in accordance with potential of bit lines (a) and (b), and transistors Q4 and Q6, which are connected to said transistors Q3 and Q5 in serial and controlled by potentials of the nodes X and Y, are provided. When a refrerence potential is different from a momory potential produced by the lines (a) and (b), the line (d) is connected to the ground. Consequently, if the line (d) is set to a high potential level, cells are not sequentially detected by any one of cell forming words at the time of the dissident detection, but the line (d) goes to a grounding potential instantaneously. Thus an associative memory which has less number of constituting transistors and acts at a high speed can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to the configuration of an associative memory circuit capable of high-speed operation.

Conventional configuration and its problemsAssociative memory circuit (Content Addressable)
eMemory (CAM) is a function that, contrary to normal memory, provides data (vector of data) and checks whether the same data is stored, and if so, outputs the address where the data is located. When searching or sorting data in a memory with
If M is used, it can be executed directly on hardware, so it can be executed very quickly and is effective. A conventional CAM had a configuration shown in FIG. 1, for example.

In Figure 1, RAM is a normal random access memory, AD is an address decoder, (Mo is a storage element (memory cell) part, C is a counter and a start signal ST
starts counting when input, binary output A1
~Am is applied to address decoder AD as an address signal. If the number of words in the RAM (corresponding to the number of upper and lower rows in the example of FIG. 1) is 2m, the counter counts at 211nm. Therefore, the number of A is required to be m. D'1～
Dn is an input terminal for reference data for comparison, and the comparator E compares each bit with the data D1 to Dn output from the RAM, and if they are all the same, outputs E1 to EnK all output a "1" code. The address at this time (i.e. counter output A
1 to Am), the function as a CAM can be realized.

The disadvantage of this conventional method is that it takes 2n cycles to match one reference data. In the case of high-speed CAM, one cycle is about 0.1 μsec, and the number of address bits n is 10 bits or more, 2, that is, 1
It takes more than 000 cycles. In other words, even high-speed CAM is 1
It takes about 100μ8eC or more to process one cycle, which is extremely slow compared to the execution time (1μ to several tens of μ8QC) of various calculations (arithmetic operations, etc.) such as high-speed arithmetic circuits, which causes problems in program execution. It had become.

Next, since the operating speed in the example shown in Fig. 1 is extremely slow, Fig. 2 shows an example in which the degree of integration is greatly sacrificed compared to ordinary RAM, etc., and in return high-speed operation is obtained. Shown below. Figure 2 shows the basic memory cell circuit of this example, 0)
) shows the configuration of a memory array using the cells in (a).

The upper half of the cell indicated by M1 in (a) is the same as a normal static RAM memory cell, and C(C1,C
2...C4) is a word line to which an address signal is applied, a (&1...a n )+b(bl...
...bn) are bit line pairs for inputting and outputting data. When storing information in the same manner as normal static RAM and then using it as an associative memory, a, b
When a reference data 6, - tsuta signal is applied at a complementary potential to the node N1, a negative output of exclusive OR with the data stored at the node N1 is obtained.DN1=M-B+M・B
, DNl: state of N1, M: memory state, B: state of bit line, each is its negation). In other words, if they match, N1 becomes pa1'', and if they do not match, N1 becomes o''.

Next, there is a match across one word consisting of n bits.

In order to detect a mismatch, the negative exclusive OR output of each bit is successively ANDed and propagated, so that finally, the AND of all bits is obtained at the right end. If there is even one mismatched bit in the cell on the left, the state of the node N2 in FIG. 2(, ) becomes "0" and the AND output N3 also becomes "0". Since it is difficult to configure a logical product using a single stage gate in a normal integrated circuit, this is achieved by connecting a negative logical product (NAND) and an inverter in series. The problems with this second conventional example are as follows: (1) The number of circuit elements constituting the basic cell is considerably large. For example, in an Nch type LSI, the normal RAM part (Ml) requires 6 elements and an additional part (M2) of 14 elements, and even if it is simply estimated, the storage capacity per unit area deteriorates by % to %. do.

(2) N to detect matches and mismatches for the whole one word
Each bit passes through AND and an inverter. Therefore, for word configurations of 10 bits or more, this propagation delay limits access speed.

In this way, in FIG. 2, when manufactured as an LSI, only an associative memory was obtained whose storage capacity was small and the operating speed was not sufficiently high.

OBJECTS OF THE INVENTION Accordingly, an object of the present invention is to obtain an associative memory that is constructed of memory cells that are not much larger than ordinary RAM cells and that operates faster than the example shown in FIG.

Structure of the Invention The memory cell circuit according to the present invention includes a bistable circuit having two points having complementary potentials, and electrical connection between each of the two points and two bit lines. 7 Part 1 of the second part. For a memory element consisting of a second switch element and one word line that controls these switch elements, one sense line is provided in the same direction as the word line, and the potential of one of the two nodes is A first circuit element in which a third switch element controlled by the potential of one of the two bit lines and a fourth switch element controlled by the potential of one of the two bit lines are connected in series to the sense line and the power supply. a sixth switch element connected between the two nodes and simultaneously controlled by the potential of another node of the two nodes; and a sixth switch controlled by the potential of the other of the two bit lines. A second circuit element in which elements are connected in series is connected to the sense line and the power source in parallel with the first circuit element.

DESCRIPTION OF EMBODIMENTS FIG. 3 shows storage elements (
(memory cell) structure is shown. A portion M0 surrounded by a dotted line in the figure has the same cell structure as a conventional static RAM, where data is read and written using peer lines a and b, and a word line C selects a row of cells to be accessed. Inverter. , I
2 constitute a bistable circuit, and the electrical connection between the nodes X and Y having complementary potentials and each of the bit lines a and b is an insulated gate field effect transistor (IGFET) Ql.

Controlled by Q2. This is an N-channel IGF
In the case of DT, by setting the word line C to a high potential, Ql, Q
2 becomes conductive, and data is written or read from memory cells arranged on the word line.

Now, in the memory cell of the present invention, Mo is used as the switch element Q3.
Q4. Q6. Q6 and sense line d are added.

The circuit configuration is M, which is part of a memory cell. The switching element Q5. is controlled by the potentials of the complementary nodes X and Y of the switching element Q5. Q
Switch element Q4.3 is controlled by the potentials of bit lines a and b complementary to Q4.3. Q6 are each connected in series, and Q
3-04. Both circuits of Q6-06 are connected in parallel between the sense line and the power supply (low potential power supply in the example of FIG. 3).

Operation explanation〉 9 B-7 To simplify the explanation, Q3. Q4. Q5. Although it is assumed that Q6 is an N-channel IGFET, a P-channel IGFET or other switching elements can have the same function if the polarity of the signal is considered.

The fact that this memory cell M has a match detection function will be explained.

Whether the data of a certain word matches or does not match the reference data for comparison is determined depending on whether the sense line d has a high potential or a low potential.

First, before starting the coincidence detection operation, the potential of the sense line d is set to a high potential. As shown in FIG. 4, a sense amplifier SA for potential detection and a load element RL are connected to the end of the sense line in the word direction, and the other end of RL is connected to a high potential power supply VD. If the initial state is maintained at a low potential, the sense line is charged to a high potential via RL, and the initial setting is completed.

However, the word line C is always kept at a low potential during the match detection operation, and the Q
1 and Q2 are kept in the OFF state.

Next, comparison reference data is supplied complementary to the pitch 1° line as potential information. This is the same operation as the data write operation in static RAM. For example, the information stored in the memory cell shown in FIG. : High potential, bit line = low potential (this is defined as 1" being supplied as reference data), then Q3. Q4. Q5
゜The status of each of Q6 is Q3: OFF Q4: ○NQ5
:○N Q6: OFF and Q3-04 connected in series. All circuits Q5-06 are turned off. Since the configuration of the memory cell circuit is symmetrical about bit lines a and b, stored data is x: low potential, Y: high potential (i.e. "0"), reference data is focused line a: low potential, Pit line: Both circuits Q3-Q4.Q6-Q6 are in the OFF state also when the potential is high (that is, reference data "o').To summarize the above, when the stored data and reference data are the same, 03-Q4. Both circuits of Q5-06 are OFF.On the other hand, if the reference data and the stored data are different from each other, for example, the reference data '°0' and the stored data '1'.
'', Q: OFF Q4: OFF Q: ○NQ6: ON, and the Q5-06 circuit is turned ON.

Therefore, a current flows from the sense line d to the low potential power supply (ground in this case), and if the resistance value of the load element is selected to be higher than a certain level, the potential of the sense line d will be lowered. If there is a difference in even one bit between the reference data and the stored data in one word, an ON circuit is present, so the potential of the sense line d is lowered, and a mismatch can be detected.

In Figure 3, Q3. Y as the control potential of Q6.

The node potential of X is used, but conversely, if X is 03. Y to Q5
Coincidence detection operation is possible even if connected to . However, in this case, the polarity of the stored data must be considered in reverse. That is, X:
The state of high potential and Y: low potential must be defined as 0'', and the state of X: low potential and Y: high potential must be defined as 1''.

As is clear from the detailed description of the invention, the memory cell of the present invention not only operates correctly as an associative memory cell, but also requires only four transistors to be added to the memory cell of a normal static RAM. extremely small scale;
A high degree of integration can be obtained. Moreover, the coincidence detection operation speed is comparable to the read operation speed of a normal static RAM, and all the drawbacks of the conventional example are overcome. In addition, the switch element Q3. Q4. Q5. Q6 is all MI 5FET
(Insulated gate field effect transistor) is extremely effective.

[Brief explanation of the drawing]

Figure 1 is a diagram showing an example of a conventional associative memory configuration, and Figure 2 (a
), (b) is a diagram showing another conventional associative memory configuration example, FIG. 3 is a diagram showing the structure of an associative memory cell according to an embodiment of the present invention, and FIG. 4 is a diagram showing the structure of an associative memory cell according to an embodiment of the present invention. FIG. 3 is a diagram illustrating an example of a configuration of one word of an associative memory. a, b...Pit i, C-=...Word line, 1
1. I. 13,...Inverter, X, Y...Node, Q
1~Q6...IGFET (switch element) 0 Name of agent Patent attorney Toshi Nakao and 1 other person 1st
Figure (Regret)

Claims (2)

[Claims] (1) A bistable circuit having two nodes having a phase-line potential, and a three-tube first circuit that controls the electrical connection between each of these two nodes and two bit lines. For a memory element consisting of a second switch element and one word line that controls these switch elements, one sense line is provided in the same direction as the word line, and the potential of one of the two nodes is A first circuit element is connected in series with a third switch element controlled by a potential of one bit line of the two focus lines and a fourth switch element controlled by the potential of one bit line of the two focus lines. a sixth switch element connected between the two nodes and simultaneously controlled by the potential of another node of the two nodes; and a sixth switch controlled by the potential of the other of the two bit lines. A memory cell circuit characterized in that a second circuit element in which elements are connected in series is connected to the sense line and the power supply in parallel with the first circuit element. (2) Third. 4th. Fifth. An insulated gate field effect transistor is used as the sixth switch element, and each two nodes are connected to the third... The gate of the sixth insulated gate field effect transistor is connected to each of the two bit lines. 6th
2. The memory cell circuit according to claim 1, wherein the memory cell circuit is connected to a gate of an insulated gate field effect transistor.