JPS60233772A - Vector processor - Google Patents

Abstract

PURPOSE:To attain partially vector processing to an arithmetic by having mutual comparison of indirect address elements for the arithmetic processing including the indirect address designation fed at both sides of an arithmetic equation, and informing quickly the impropriety of reference to data by a high-order processing unit. CONSTITUTION:When the vector processing is started by a scalar processor 9, a decoder 3 resets a state control circuit 4, an FF within a comparison mask register 5 and counters via buses 13 and 15. Then a vector instruction train fetch requester 2 feeds a request to a main memory 1 via a bus 11 to read out a vector instruction. Thus the mutual comparison is carried out between indirect address elements in case an arithmetic is performed with an equation including the designation of indirect addresses fed at both sides of the equation. The result of said comparison is sent to the circuit 4 and the register 5. In other words, the impropriety of reference to data on the arithmetic including the designation of indirect addresses fed at both members of the equation is informed quickly to a high-order processor that started a vector processor. Thus the partial vector processing is made possible with this arithmetic.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a vector processing apparatus, and relates to an apparatus suitable for changing processing based on a comparison between vector data.

[Background of the invention]

Operations involving indirect addressing on both sides of an expression are generally coded as follows:

Do 100 i=1 , N 100 A(Eng.NnE+41) = A(Eng.anE!
xt:))re Btl) here indicates that any of the four arithmetic operations is represented by one operator. If this type of processing is vector processed, the A array will be processed as NDEx2
When loading from the main memory to the vector register due to indirect addressing m, the process of storing the A array, which is being created at the same time, by the NDKX pile is not synchronized, so by chance the NDIX and NDIX NDFiX
If there is something that indicates the same value in both vector element sets of two vectors, the A array load value will not be guaranteed after the A array is stored, and the vector processing result will be an invalid value (this phenomenon is hereinafter referred to as data reference inappropriateness). ). For this reason, conventional vector processing devices exclude calculations that include indirect addressing on both sides of an expression from vector processing, and perform sequential processing using a scalar processing device other than the vector processing device.

However, in calculations that include indirect addressing on both sides of an expression that appears in scientific and technical calculations, it is thought that cases in which data referencing is inappropriate are extremely rare, and this exceptional inappropriateness of data referencing makes it difficult to perform high-speed vector arithmetic processing. becomes impossible,
The vector processing device was in a state where its performance could not be demonstrated.

[Purpose of the invention]

An object of the present invention is to enable partial vector processing of calculations by combining the function of high-speed processing of arithmetic processing that includes indirect address specification on both sides of a calculation formula with the function of performing high-speed comparison of indirect address data. The object of the present invention is to provide a vector processing device that realizes the following.

[Summary of the invention]

An expression that includes indirect addressing on both sides of the expression is converted by a compiler into a group of six machine instructions as shown in FIG. That is, in the first stage of processing, indirect address elements are compared with each other, and it is determined whether data reference is inappropriate or not. As a result of this determination, if the reference is not found to be inappropriate, the process branches to the second stage vector instruction and performs high-speed vector processing. If such unsuitability is found, a branch is made to the third stage scalar instruction group.

The effect of this method is shown in terms of the processing time ratio compared to the conventional sequential processing method. Since, we get . Here, id/dex means an array holding indirect address data. The effectiveness of this method depends on the software's logic configuration, which performs index comparisons at high speed and extracts the results.

In order to perform index comparison at high speed, NDKX and IND
Consider a matrix that can be constructed from EX 20 vectors (Figure 2). The range in which index comparisons must be made is below the diagonal of the matrix in FIG. (This part will be referred to as the search space from now on).

The search space can be used to perform comparison operations in any order. Furthermore, comparison operations can be performed using any number of arithmetic units. These two features are well suited to vector processing devices, and can achieve processing speeds nearly 100 times faster than scalar comparison operations. On the other hand, if an inappropriate data reference is detected, it is necessary to immediately stop the operation of the processing device performing the search process and report the detection of the inappropriate data reference to an external processing device.

Conventional vector processing devices are not equipped with this function of rapidly interrupting the processing device and continuing to hold the information while performing the logical sum of the comparison results.

In order to realize this processing capacity interruption and holding function, the vector instruction control circuit in the vector processing device is designed to match the 1-bit wide 7-lip float 2 that holds the comparison operation result and the element at which the comparison result matches. A plurality of sets of counters (hereinafter, these sets will be referred to as comparison mask registers) are provided to indicate whether a difference (or a mismatch) has been taken. The comparison mask register is reset when the vector processing device is activated by an external upper processing bag @, and is reset when a match is found as a result of the index comparison operation that is processed subsequently.
1". This bit is immediately detected by another logic circuit in the vector control circuit and stops the vector processing device. At the same time, the value of the coincidence counter at the time when the comparison mask register becomes "1" is is set in a register readable by the processing unit, and the vector processing unit
The interrupt is reported to the higher-level processing device that started it. In the case of a mismatch as a result of the comparison operation, if a vector instruction sequence that causes the above operation is specified by the compiler, the comparison operation result is reversed by an inverter to enable the same processing as in the case of "match".

As described above, when an inappropriate data reference is detected, control is transferred by interrupt to the higher-level processing device that started the vector processing device that detected the inappropriate reference, and the processing device includes indirect addressing on both sides of the expression. Arithmetic processing is performed using a scalar code (see Figure 1); conversely, if no inappropriate data reference is detected by comparison processing, the vector processing device that performed the comparison processing terminates normally, and the next Execution of the vector code (see FIG. 1) for arithmetic processing including indirect addressing is started.

As described above, index comparison operations are performed using high-speed vector processing.
By performing vector processing when there is no inappropriate data reference, and sequentially performing scalar processing when the reference inappropriate condition is detected,
Processing becomes possible at high speed. FIG. 3 shows a time chart of arithmetic processing including indirect addressing by the vector processing device of the present invention, with time on the horizontal axis. In FIG. 3, (a) shows a case where data reference is not inappropriate, and (h) shows a case where data reference is inappropriate.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Fourth
The figure is a schematic block diagram of one embodiment of the invention. 1 is the main memory, 2 is a 7-chiri requester for the vector processing unit to read a vector instruction string, and 3 is a requester and an arithmetic unit (hereinafter referred to collectively as both are used to decode the read vector instruction and are necessary for executing the instruction). A logic circuit (hereinafter referred to as a decoder) 4/fi that assigns a resource (hereinafter referred to as a resource), a state vector register of a resource for executing a vector instruction, and a state holding 7 that manages the state of a comparison mask register introduced in the present invention. A state management circuit consisting of a lipflot 1 circuit group and a logic circuit that controls them; 5 a logic circuit that has a group of comparison mask registers and logic that controls and sends out the interrupt information they indicate (hereinafter referred to as a comparison mask register); 6 is used to generate activation information for activating these resources and the register control circuit when permission is given to use the resources and register group required by the vector instruction to be executed by the state holding circuit of the state management circuit 4. The instruction activation circuit 7 indicates the value of the quanta in the comparison mask register 5 when there is a match (or mismatch) between the index array elements holding indirect addresses, that is, the index array element number where the match was found. 7 lip-flop circuits are set; 8 is a pect for comparing index elements;
9 is a scalar processing device that controls the vector processing device.

Using FIG. 4, an outline of the operation up to the generation of an interrupt to the scalar processing device 9 when a match (or non-t) is found as a result of comparison with the comparison operation between indirect addresses will be explained ( Therefore, in FIG. 4, the vector registers necessary for the vector processing device to perform vector operations, the vector arithmetic unit for performing the four arithmetic operations, and the Questa circuit for transferring data between the main storage device 1 and the vector registers are shown. (Not shown. Data transfer buses between the scalar processing device 9 and the main storage device 1, etc. are also omitted).

After the vector processing device is activated by the scalar processing device 9, the decoder 3 resets the state management circuit 4, the seven lip-flops in the comparison mask register 5, and all counters via the bus 13.about.15. Next, the vector instruction string fetch requester 2 issues a request to read the vector instruction from the main memory 1iC via the bus 11. In response to this request, a vector instruction sequence is sent to the decoder 51C via the requester 2 using the main memory 1 and the storage 12. The decoder 3 decodes the vector instruction sequence, signs the resources and registers necessary for executing the instruction, and indicates the busy state of the resources and registers.
The state management circuit 4 is connected to the state management circuit 4 through the bus 13.

Details of the state management circuit 4 are as shown in FIG. This circuit has one beat equal to the number of resources and registers.

The resource and register states sent from the decoder 6 are input to 30 AND circuits through a bus 13 (the bus is the east line) according to the number assigned to each resource register. The output from the latch 61 is also input to this AND circuit. The latch 31 is “1” at reset.
Therefore, when the resource or register is not in a busy state, the logical sum is taken, and the output 14 (east line) K of the state management circuit 4 is "1", which means that the resource or register is permitted to be used. is output. This output is sent to the decoder 3, and at the same time is reversed by the input node 232, changing the content of the latch 31 to "0". At the same time, the selector 63 is closed, and the reset signal is output from the node 16. It will not be opened until a signal comes and the contents of the latch become “1”.If a subsequent vector instruction inquires about the status of the resource or register corresponding to the latch, the contents of the latch 31 will become “0”. Therefore, the AND is not performed and "0" is output on the node 14.

The above operations manage the states of resources, registers, and so on. The vector instruction that has been enabled to be activated by the state management circuit 4 is sent to the instruction activation circuit 6 through the )< path 50 . After the instruction activation circuit generates the information necessary to execute the vector instruction, it sends the information to each resource and vector register control circuit using steps 51 and 52, respectively.

Next, the operation of the vector processing device after a vector instruction for indirect address comparison is activated will be described. Using the arithmetic unit 8 and the servers 16, 17, and 18, the comparison operation is completed, the comparison result is enabled, and the comparison result is sent to the state management circuit 4 and the comparison mask register 5, respectively. A signal indicating the end of the comparison operation passes through the bus 16 and becomes a reset input of the latch 61 corresponding to the arithmetic unit shown in FIG. The signal releases the busy state of the arithmetic unit.

FIG. 6 shows the details of the comparison mask register circuit, in which the comparison result enable is passed through the bus 17 to the AND circuit circuit 2 and 0 to the timing register bus 17 via the bus 40. The results are entered. The AND circuit 20
The output of is sent to the flip-flop 24 via the OR circuit 23.
is input. The output of the flip-flop 24 passes through the bus 42 and becomes an input to the OR circuit 23. These circuits activate the vector processing device, and the OR of all comparison operation results is stored on the flip-flop 24, which is then cleared to zero. The flip-flop 24 is not reset by the computation end signal K of the arithmetic unit 8 (on the switch 16). On the other hand, if a vector instruction that generates an interrupt is decoded when the comparison operation does not match, a comparison result inversion signal is sent through the decoder 5d bus 19.

This signal activates the selector 29 of FIG. 6, which switches the bus 18, on which the comparison results are transmitted, to the inverter 28. This operation yields a comparison result in which both p and AND circuits are inverted. The following operations are the same in the case of "match".

If the content of flip-flop 24 is "1", ie, a match, the signal is sent via bus 43 to circuit 10 of FIG. The circuit 10 performs the logical sum of all the "coincidence" signals corresponding to a plurality of arithmetic units. As a result, the index INDEX and index NDRX2 shown in FIG.
A matrix-like space constructed from a group of elements to be compared can be searched in parallel by multiple arithmetic units. The output of the circuit 10 is sent as an interrupt signal through the bus 44 to an external processing device controlling the vector processing device.

A signal indicating that the arithmetic unit has performed comparison processing is sent to the shim ND circuit 21 via the bus 17. The circuit 21 eliminates the timing and WM process and sends the output to the element number counter 25 via the bus 46.

The counter 25 is incremented by +1 to the mother for comparison in ascending order as shown above. The counter 2s is cleared to 0 by the comparison end signal of the computation unit. That is, this comparison end signal is sent from the arithmetic unit to the AND circuit 2 via the bus 16.
After performing a logical product with the timing at step 2, the counter 25 is cleared to 0 via the bus 47.

On the other hand, if a match is found as a result of the comparison operation, a signal indicating that there is a match is generated on the bus 45 corresponding to the arithmetic unit, and the count-up operation of the color/receiver 25 is carried out through the bus 45. Make it stop. At the same time, the contents of the counter 25 are transferred to the flip-flop 7 via the bus 48. The flip-flop 7 can be removed from an external processing device using the bus 49.

A signal indicating the completion result of the comparison operation of the arithmetic unit is sent to the comparison mask register 5 via the bus 16, and is also sent to the state management circuit 4 at the same time. The state/α management circuit 4 resets the flip-flop circuit 61 (FIG. 5), which indicates the busy state of the resource, to 1" by the end signal. The state management circuit 4 resets the flip-flop circuit 61 (FIG. 5), which indicates the busy state of the resource When the contents of the vector instruction group are all "1" and the completion of the vector instruction group is detected, the completion of the comparison operation is reported to the external processing device that started the vector processing device via the bus 27.

〔Effect of the invention〕

According to the present invention, data reference inadequacies in calculations that include indirect addressing on both sides of an expression can be compared with conventional vector processing devices, and the processing device that has started the vector processing device can immediately know the The information can be used to perform subsequent vector or scalar operations. As a result, operations that include indirect addressing on both sides of an expression can be practically processed by a vector processing device, which hardly includes inappropriate data references that often occur in scientific and technical calculations.

In addition, by reading the counter value at the time of the coincidence detection in the vector processing device that detected the scissors interrupt by the interrupt report at the time of a coincidence between vector data elements, which can be expected according to the present invention, the following can be achieved. Processing including branching outside the o-loop can be performed as vector processing.

DOlooi =j, N 工F(A(i), II!Q, B(i)) Go
To 200100 C0NT Engineering NUIe 200 The new functions realized by the present invention beyond the processing using the variable value i can expand the scope of application of the vector processing device and substantially improve the processing performance of the device.

The increase in the amount of hardware due to application of the present invention is much smaller and more economical than designing a new dedicated arithmetic unit for vector processing of inappropriate data references.

[Brief explanation of drawings]

Figure 1 shows how a 10-gram that includes indirect addressing on both sides of the expression is converted into three blocks by the compiler. Figure 2 shows a data reference made up of two index array elements indicating indirect addresses. Figure 3 is a matrix space diagram to check for inappropriateness; Figure 3 is a time chart of processing in the case of no data reference failure and reeds for calculations that include indirect addressing on both sides of the equation; Figure 4 is a vector diagram based on the present invention. Conceptual diagram of vector instruction control system of processing unit, 1i45 diagram butterfly, 4th
FIG. 6 is an explanatory diagram of the state management circuit shown in the figure, and FIG. 6 is an explanatory diagram of the comparison mask register circuit shown in FIG. Explanation of symbols 1...Main storage device 2...Fexecution requester 6...Decoder 4...State management circuit 5...Comparison mask register 6...Instruction wJ circuit 7...Furi 717021 Circuit 8... Vector arithmetic unit 9... Scalar processing unit 10... OR circuit 24... Comparison result holding flip-flop 25...
Comparison element number counter 31: Resource status holding flip frog. Figure 1 Atsushi Figure 2 INDEX 2 X3 Figure Time (o-) -111 Cheer 4. Figure S

Claims (1)

[Claims] A main storage device, a plurality of vector registers, a plurality of data transfer circuits that manage data transfer between the main storage device and the vector registers, and vector operations and processing on vector data received from the vector registers. and has a plurality of vector arithmetic units that send results to the vector register, and manages startup and termination of the data transfer circuit and the vector arithmetic units, and at the same time manages writing and reading of data to the vector register. In a vector processing device comprising a control circuit that performs activation control of vector instructions so that there is no logical contradiction in data processing, the comparison operation result sent from the vector arithmetic unit is held in the control circuit. It is equipped with a flip-flop circuit and a counter circuit for finding the comparison element number, and manages these in the same way as the vector register, and when the comparison operation result shows a match or mismatch, the processing by the vector processing device is stopped, and at the same time, the counter circuit is The count value of the circuit is set in the 7-lipfrog circuit from an external processing device controlling the vector processing device, and the completion of this series of operations is reported to the external processing device. Vector processing unit.