JPS60233731A - Digital information processor - Google Patents

Abstract

PURPOSE:To stop the execution of a program instruction with an optional timing by providing a gate circuit which is controlled by a prescribed control signal at an output part of an instruction decoder circuit. CONSTITUTION:The output signal of a control matrix ROM is delivered via NOR gate circuits G1-G4 respectively. These gate circuits are controllingly opened and closed by the output signal of an OR gate circuit which receives a delay signal DL which requests a temporary stop of actions, a reflesh signal RF, a bus request signal BR, a sleeve signal SL, etc. An action stop request signal is produced with the timing where a microinstruction action of one or several steps is through to a program instruction which is under execution. Then the request signal is supplied to the circuit G5. Thus the output of the circuit G5 is set at ''1'' and at a high impedance, and the circuits G1-G4 are fixed at ''0''. These gate circuits can be held in a non-operation state as long as the action stop request signals are continuously produced.

Description

[Detailed Description of the Invention] (Technical Field) This invention relates to a digital information processing device,
For example, it relates to technology that is effective for use in microprocessors.

[Background technology]

In microprogram control adopted in digital information processing devices such as microprocessors,
The information processing is realized by microinstructions that control the selection and order of static functional units instead of hardwired logic.

(For microprogram control methods, see 19
(Refer to pages 400-401 of the Integrated Circuit Handbook, published by Asakura Shoten on June 30, 1981) In other words, it is realized by microinstructions which static units are to function when and in what control order for a specific program instruction word. do. In this way, microprogram-controlled information processing equipment
The conventional control circuit using wire logic is replaced with a series of microprograms in control storage.

In such a microprocessor using a microprogram control system, it has become necessary to temporarily stop the information processing operation at an arbitrary timing according to a plurality of types of operation modes. In other words, when the DMAC (direct memory access control) acquires the bus, the dynamic type R
This is because it is necessary to temporarily stop the operation of the microprocessor in order to extend the AM (Random Access Memory) refresh cycle.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital information processing device that has a function of stopping execution of program instructions at any timing using a simple circuit configuration.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, by providing a gate circuit controlled by a predetermined control signal at the output part of an instruction decoder circuit that receives program command words and realizes order control and selection control operations for predetermined information processing operations, This is to generate a decoded output signal that puts the device into a no-operation state.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of the main part of the present invention.

The instruction register R1 is used to input a series of program words one after another. The program word input to the instruction register R1 is decoded as follows, and desired information processing is performed.

The program word of the instruction register R1 is the gate circuit G
The ROM (read only memory) address register R2 is entered via the ROM (read only memory) address register R2. Decoding tree D
A series of control pulses (system clock) φ generated by a pulse generation circuit (not shown) is supplied to T. According to the instruction word of the ROM address register R2, each of the above pulses passes through one output line of the decoding tree DT and the control matrix (instruction decoder)
Input to μROM. This control matrix μROM
is composed of a selection control matrix μROMI and an order control matrix μROM2. The selection control matrix μROMI uses its output to operate various gates in the static control field SCF consisting of arithmetic units, control registers, etc. corresponding to microinstructions. Moreover, the order control matrix μROM2 is
An address signal for the next microinstruction to be executed is formed and supplied to register R3.

Furthermore, if there is a signal indicating a conditional branch, the ROM address register R3 refers to this signal and forms a microinstruction to be executed next. When the execution of a microinstruction consisting of one or several steps for one program word in the instruction register R1 is completed by repeating the same operation as described above, the gate circuit G is opened and the next program word is taken in, and a series of information processing programs are completed. is carried out.

The above decoding tree DT and the control matrix μ
Each ROM is composed of a ROM. That is, the above decoding tree DT is AND
The control matrix μROM is composed of an array, and the control matrix μROM is
It is composed of an OR array, and the PLA as a whole
(programmable logic array).

In this embodiment, since a function is added to temporarily stop the information processing operation of the microprogram control method using the PLA at an arbitrary timing, the output signal of the control matrix μROM is not particularly limited, but is as an example. The signals are outputted through NOR gate circuits 01 to G4 shown in FIG. The opening and closing of the gates of the NOR gate circuits 01 to G4 shown as representatives above are controlled by the output signal of the OR gate circuit G5, which receives various signals requesting a temporary stop of operation.

The signals requesting the temporary suspension of operation are, but are not particularly limited to, the delay signal DL, refresh signal RF, bus request signal BR, and sleeve signal SL. Note that these signals requesting to stop the operation are not generated immediately when the request is made, but are generated at the timing when the operation by the microinstruction consisting of one or several steps for one program instruction that is currently being executed is completed. be made to do. That is, a signal requesting the stop of the operation is generated, which is supplied to the OR gate circuit G5 after waiting until the timing to take in a new program command.

Further, the structure of the microinstruction word of this embodiment is that when all the signals are logic "0", the static control field SCF
The gate circuit G is closed, and the gate circuit G is closed.
The program words loaded into the instruction register R1 are stored in the ROM.
This prohibits the data from being transferred to the address register R2.

As a result, the microprocessor can be maintained in a non-operating state in which no operation is performed as long as the above-mentioned operation stop request signal continues to be generated.

FIG. 2 shows a circuit diagram of a specific embodiment of the gate circuits 01 to G4.

In this embodiment, a clocked inverter circuit and a pull-down MOSFET are used in place of a normal logic gate circuit in order to simplify the circuit. That is, taking the NOR gate circuit G4 as an example, the output signal of the sequential control matrix μROM2 is supplied to the input of the clocked inverter circuit IVI. The clock signal of this clocked inverter circuit IVI is provided by an inverter circuit V2 which inverts the output signal of the OR gate circuit G5.
The clock signal φ'' formed by the clocked inverter circuit IVI is supplied with a pull-down MO3 between the output terminal of the clocked inverter circuit IVI and the ground potential point of the circuit.
FETQ is provided. Although not particularly limited, this MO3FETQ is constituted by an N-channel MO3FET, and its gate receives the output signal φ" of the OR gate circuit G.
is supplied.

Note that when the clocked inverter circuit Iv1 is used in this manner, the OR gate circuit G5 is supplied with the clock signal for its output together with the request signal for stopping the operation. As a result, when no operation stop request signal is supplied, the clock signal is output to the clocked inverter circuit! v1, the inverter circuit IVI operates according to this clock signal.

Then, when any of the above-mentioned operation stop request signals is generated, the output signal of the OR gate circuit G5 is forced to the logic "
1", the clocked inverter circuit IVI is put into a non-operating state, in other words, the output is put into a high-impedance state, and the MO3FETQ for pull-down is
is turned on, so its output is fixed at logic "0" like a normal NOR gate circuit.

In this way, when a clocked inverter circuit is used, a pull-down MOSFE is selectively connected to its output terminal.
By providing a T or pull amplifier MOSFET, an output signal with an arbitrary bit pattern can be formed. Therefore, the bit configuration of the microinstruction that creates the above-mentioned non-operation state is all logic “0”.
”, M for pull-down/pull-up above
A corresponding bit configuration can be easily created by combining OSFETs.

〔effect〕

(By providing a gate function at the output section of the control matrix that executes the 11 microinstructions, an effect can be obtained in that the information processing operation can be stopped very easily.

(2) Since the operation is stopped at the output section of the control matrix, there is an operation delay time from when a new program word is taken in until it is output from the control matrix. Since it is only necessary to close the gate function of the output section at the same time, it is possible to obtain the effect that the control for creating the operation stop state becomes extremely simple.

(3) A clocked inverter circuit as a gate function,
When a pull-up or pull-down MOSFET is used, the above gate function can be achieved with an extremely simple circuit.

(4) A clocked inverter circuit as a gate function,
When a pull-up or pull-down MOSFET is used, it is possible to form an output signal with an arbitrary bit pattern.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples, and it is possible to make various changes without departing from the gist of the invention. For example, the logic configuration of a gate circuit can take various embodiments depending on the signal level.Furthermore, the operation stop request signal can be used to control various operations in commonly used information processing systems. Various embodiments can be adopted depending on the situation.

[Application field]

The present invention can be widely used in digital information processing devices such as microprogram type microprocessors.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the main part of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the gate circuit. R1...Instruction register, G...Gate circuit, R2...R
OM address register, DT...Decoding tree, μROM...Control matrix, μROMI...Selection control matrix, μROM2...Sequence control matrix, SCF...Static control field, R3...Register, 01-G4...Nor gate Circuit, G5...OR gate circuit, Ivl...clocked inverter circuit, IV2...
・Inverter circuit

Claims (1)

[Scope of Claims] 1. An instruction decoder circuit that receives program command words and realizes order control and selection control operations for predetermined information processing operations; A digital information processing device comprising: a gate circuit controlled by a signal. 2. The gate circuit is provided at a clocked inverter circuit supplied with a clock signal formed based on the control signal and at the output side of the clocked inverter circuit, and when the clocked inverter circuit is in an inactive state. Pull amplifier or pull-down MO3FE that is activated when
The digital information processing device according to claim 1, characterized in that the digital information processing device is made of T. 3. The digital information processing device includes a microprocessor, and its instruction decoder circuit is a PL
A digital information processing apparatus according to claim 1 or 2, characterized in that the digital information processing apparatus is constituted by A.