JPS60232774A - Reader - Google Patents

Abstract

PURPOSE:To attain highly accurate picture reading in various originals by controlling the conversion of an A/D converter by a peak holding circuit. CONSTITUTION:An image sensor 21 inputs reflected light from an original and forms a picture signal 22 and a signal 26 amplified by an amplifier 23 is sent to a programmable attenuator 24 and a peak holding circuit 61. The circuit 61 receives also a picture singal 27 from the attenuator 24 and supplies a selected signal 63 to an A/D converter 64. The converter 64 outputs the converted correcting signal 65 as a shading correcting signal. The signal 65 is encoded into a binary signal by a comparator 66 and data formed by a multiplexer 67, an addressable latch circuit 68, etc. are stored in an RAM72 as attenuation ratio data for one line. The data are sent to the attenuator 24, and when the data are held in the circuit 61 as a peak value, a picture signal corrected at its shading is obtained from the converter 64.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a reading device using a photoelectric conversion element.

[Prior art]

2. Description of the Related Art Solid-state image sensors are widely used as photoelectric conversion elements in reading devices, such as facsimile machines or some types of copying machines, that convert image information on a document into electrical signals and read them.

FIG. 1 shows an example of such a device. A document 2 is placed on a platen 1 with its reading surface facing down. Immediately below the platen 1 is a platen 1 that irradiates the document 2.
A book fluorescent lamp 3 is arranged in the main scanning direction of the document 2. Light reflected from the original 20 by the fluorescent lamp 3 is incident on a lens 4, and an optical image is formed on a solid-state image sensor 5. The solid-state image sensor 5 is a one-dimensional image sensor using, for example, a CCD, and is adapted to read image information using a rask scan method by moving the original 2 in the sub-scanning direction.

In such a reading device, even when the density of a blank document is uniform over one line, the photoelectric conversion output of the solid-state image sensor 5 becomes non-uniform. One of the causes of this is variation in the luminance distribution of the light source.

FIG. 2 is for explaining this. When the fluorescent lamp 3 is used as a light source, the light beam 6 is most concentrated at the center of the reading line of the document 2.

The illuminance is highest at the center of the document 2 and decreases toward the edges, which causes a large change in the photoelectric conversion output. Other causes of non-uniform photoelectric conversion output include a decrease in the amount of light around the lens 4 due to the cosine fourth law, and non-uniform sensitivity of the elements of the solid-state image sensor 5.

If the photoelectric conversion output of the solid-state image sensor 5 becomes non-uniform in this way, it will adversely affect the signal processing process at the stage of converting an analog image signal into a digital signal, causing deterioration of image quality. FIG. 3 is for explaining the deterioration in image quality when an image signal is binarized. Image information 7 (black and white information) as shown in figure a is placed on the reading line of the original.
Suppose that exists. On the other hand, from the solid-state image sensor, a non-uniform photoelectric conversion output 8 as shown in ab of the same figure is obtained. Assume that this is binarized at a certain threshold level. In this case, there is a possibility that the signal level corresponding to black image information (hereinafter referred to as black level) in the center of one line will be erroneously binarized as white image information; There is a possibility that a signal level corresponding to image information (hereinafter referred to as white level) may be erroneously binarized as black image information. Therefore, if the threshold level 11 is set, for example, as shown in FIG. 2C, a digital image signal 9 that is considerably degraded compared to the original image information will be obtained, as shown in FIG.

In order to prevent such deterioration of image information during the binarization process, there is a reading device equipped with a threshold/level setting through shading correction circuit using an AD converter and a DA converter.

In this device, a line on a white background is first read by a solid-state image sensor, and a photoelectric conversion output (shading waveform) 11 covering one line and one line is obtained as shown in FIG. 4a. This is then converted into a digital quantity using an AD converter and stored in a memory. Thereafter, at the stage when image signals are actually read, these digital quantities are converted into analog quantities using a DA converter. Based on this, the shape ink waveform 11 and the threshold level 12 (
b) in the figure is set, and the image signal 12 is binarized.

As a result, the white level and black level of the image information are binarized without error, and a high-quality digital image signal 13 is obtained as shown in FIG.

However, in such a conventional reading device, a D-digital signal is used to convert the digital signal after A/D conversion into an analog signal.
This method requires an A converter for shading correction, making the device expensive.

Therefore, the inventor wanted to propose a shading correction device using a programmable attenuator in March 1980.
Patent application dated May 17th). FIG. 5 shows a reading device using this device. The image sensor 21 of the reading device is a reading element that photoelectrically converts image information, and generates an image signal 22 by receiving reflected light from a document. This image signal 22
is an analog signal, and as described above, even if the density of the original is constant, the signal level is non-uniform. The amplifier 23 amplifies the image signal 22 to a predetermined level and then supplies it to the programmable attenuator 24 . The programmable attenuator 24 is designed to attenuate the amplified image signal 26 in accordance with 8-bit attenuation ratio data 25. After the attenuated image signal 27 is quantized in a subsequent circuit, it is sent to a recording section (not shown) or undergoes image processing such as image synthesis.

By the way, the 8-bit parallel attenuation ratio data 25 supplied to the programmable attenuator 24 is stored in the O to 7th RAM (Random Access Memo! J) 2L-
It is separated into 1 bit each from 0 to 29-7 and stored as a bit string (bit string for attenuation) with a length of two I-lines. These (7) RAM29-0 to 2.9-7
is read out under the control of the RAM:17 controller 31.

For this purpose, the RAM controller 31 is supplied with a main scanning start signal 32 and an image signal clock 33. The data read out one bit at a time is latched by the latch circuit 35 through the AND gates 34-o to 34-7, and is supplied to the programmable attenuator 24 as attenuation ratio data 25. The latch circuit 35 has an image signal clock 3 for setting the latch timing.
3 is supplied.

This reading device is provided with a circuit section for initializing attenuation bit strings in each of the RAMs 29-0 to 29-7. The peak hold circuit 37 holds the level of the image signal 26 corresponding to the white portion of the original, and outputs this to a voltage dividing circuit made up of two resistors 38 and 39. The voltage (2) created by the voltage dividing circuit will be used as a reference voltage for the comparator 41. This comparator 41 outputs an image signal 27 whose level is changed according to various types of attenuation ratio data 25.
is input as a signal for comparison. The resulting comparison result 43 is supplied to an addressable latch 44.

Addressable latch 44 has eight output terminals Q. -Q, and the corresponding RAMs 29-0 to 29-
It is connected to the input/output terminal I10 of No.7. The addressable latch 44 receives the count value 46 from the line counter 45.
is input, and the comparison result 43 described above is output from an output terminal corresponding to this count value. The comparison result output from the addressable latch 44 is stored in either RAM 29 under the control of the RAM controller 31.
(the address corresponding to the main scanning position).

The 8-bit shift register 48 has an AND gate 34-0.
This is a shift register that outputs parallel data for controlling the opening and closing of 34-7. ANDGATE 34-0~
34-7 outputs data read out from the RAMs 29-0 to 29-7 one bit at a time, and attenuation ratio data for correction is created in accordance with the procedure described below.

This 8-bit shift register 48 and line counter 45
is supplied with a main scanning start signal 32 and a correction work start signal 49.

Next, a procedure for creating correction attenuation ratio data using a reading device having such a configuration will be described.

(2) For example, when a service engineer sets a blank original in a reading device and presses a button for shedding correction (not shown), a correction work start signal 49 is generated. At the same time, line counter 45 and 8-bit shift register 48 start operating.

■After this, when the main scanning start signal 32-1 is generated, the 8-bit shift register 48 receives the following parallel data 5.
Outputs 1-1.

“10000000” (51-1) This parallel data 51-1 creates the seventh anime) 34
-7 is opened, and the other AND gates 34-0 to 34-6 are closed.

■Each RAM29-0 to 29-7 has all "1" initially.
” data has been written. Therefore, along with this, the 7th data has been written.
Data "1" is continuously output from the computer 34-7, and is sequentially latched by the latch circuit 35 in response to scanning of the original. The latch circuit 35 outputs the first stage attenuation ratio data 25 in which only the MSB (most significant bit) is 1.
-1 is output, and the programmable attenuator 24 is set to an attenuation ratio corresponding to this.

(2) In this state, the image signal 27-1 outputted from the programmable attenuator 24 is compared with the voltage (2) by the comparator 41.

Assume now that the image signal 26 before correction is as shown in FIG. 6a. The maximum level of the image signal 26 is the voltage ■,
It is. As shown in the figure, the image signal 27-1 output from the programmable attenuator 24 has a signal level that is attenuated by the attenuation ratio expressed by the parallel data 51-1. This image signal 27-1 is sent to the comparator 41
are compared and binarized. The voltage ■ for comparison can be set freely, but in this example it is 1/1 of the voltage ■2.
It is set to 2. In the sections L+ and L- where the voltage level of the image signal 27-1 is lower than the voltage (2), data "0" is output as the comparison result 43.

In other sections H, data "1" is output as the comparison result 43.

■The image signals of N pixels output from the image sensor 21 by scanning one line are sequentially compared by the comparator 41,
The data string as the comparison result 43 is written into the seventh RAM 29-7 via the addressable latch 44. FIG. 6C shows the correction result when it is assumed that only the data written in this RAM 29-7 is adopted as the attenuation ratio data 25. The programmable attenuator 24 does not perform any attenuation in sections L1 and L2, and outputs the image signal 26 as it is as an image signal 27. Further, in section H, attenuation is performed at the above-mentioned attenuation ratio, and the image signal 27-1 is output. It can be seen that shading correction has been performed, albeit only roughly.

■When data writing to the seventh RAM 29-7 is completed, the 8-bit shift register 48 shifts the data in response to the generation of the next main scanning start signal 32-2, and outputs the following parallel data 51-2. .

“11000000” (5i2) This parallel data 51-2 opens the sixth and seventh AND gates 34-6, 34-7, and other AND gates 34-0
~34-5 remains closed.

■7th Antogame) From 34-7, follow the previous steps to
The data stored in the RAM 29-7 is output bit by bit in synchronization with the image signal clock 33. Further, the sixth AND gate 34-6 sequentially outputs all "1" data initially stored in the sixth RAM 29-6.

The programmable attenuator 24 inputs these second-stage attenuation ratio data 25-2 and outputs an image signal 27-2 at each attenuation ratio each time the image signal 26 is input for one pixel.

(2) The image signal 27-2 is compared with the voltage (2) by the comparator 41. The addressable latch 44 then outputs this comparison result 43 for one line to the sixth RAM 29-6. In this way, data "0" or 1" is also written in the sixth RAM 29-6 corresponding to each position of the line. FIG.
6. This represents the correction result when it is assumed that only the data written in 29-7 is adopted as the attenuation ratio data 25. It can be seen that shading correction is performed even better than in FIG.

(2) When the next main scanning start signal 32-3 is generated, the 8-bit shift register 48 further shifts the data one bit at a time, and outputs the following parallel data 51-3.

"11100000"(51-3>In this state, the third bit of the attenuation ratio data 25 is set, and the result is written into the fifth RAM 29-5.

Thereafter, when the data setting up to the 8th bit is performed for the damping ratio data 25 in the same manner, all RAMs 29-0 to 29-29
The writing of -7 is completed, and the shading correction is completed. FIG. 6e shows the resulting white image signal level after correction.

When actually reading an image, the RAM controller 3
1, each R is synchronized with the image signal clock 33.
Attenuation data is simultaneously output bit by bit from AM29-o to AM29-7, and is supplied to the programmable attenuator 24 as attenuation ratio data 25. Image signal 27 output from programmable attenuator 24
is quantized by an A/D converter (not shown) and supplied to a recording device or a display device.

However, in the reading device described above, since analog signals are compared using a comparator, signal processing for shading correction cannot be made sufficiently high-speed. Furthermore, when the signal after shading correction is delivered to a recording device or the like, it is necessary to convert it into a digital signal.

[Purpose of the invention]

In view of these circumstances, it is an object of the present invention to provide a reading device in which the signal after shading correction is a digital signal and can speed up the shading correction.

[Structure of the invention]

In the present invention, an image signal read by an image sensor is attenuated or amplified by a programmable gain amplifier, and then converted into a digital signal by an analog-to-digital converter. Then, attenuation ratio data or amplification factor data is created based on the converted signal. This attenuation ratio data or amplification factor data is stored in a storage means such as a RAM, and is applied to a programmable gain-in amplifier when reading image information. As a result, a shading-corrected image signal is obtained from the analog-digital converter. Since comparators and the like that process digital signals are generally capable of high-speed processing, it is possible to achieve high-speed shading correction.

〔Example〕

The present invention will be described in detail with reference to Examples below.

FIG. 7 shows the main parts of the reading device of this embodiment. An image sensor 21 of this device receives reflected light from a document (not shown) and generates an image signal 22. The image signal 26 amplified by the amplifier 23 is supplied to the programmable attenuator 24 and the peak hold circuit 61.

The peak hold circuit 61 is also supplied with the image signal 27 outputted from the programmable attenuator 24, and generates the holding doubler 63 by selectively inputting these manually under the control of a control signal (not shown). The A/D converter 64 performs analog-to-digital conversion of the image signal 27, and the holding signal 63 changes the conversion level in two stages.

In other words, ■ When creating attenuation ratio data for shading correction, the peak hold circuit 61 outputs the peak value for one line in the image signal 26 as the holding signal 63, and the A/D converter 64 outputs the peak value of the corrected image after conversion. The signal 65 is output as a shading correction signal. This correction signal 65 is binarized by a comparator 66, and is supplied to the RAM 72 via a multiplexer 67, an addressable latch circuit 68, an exclusive OR gate group 69, and a 3-state buffer 71, as will be explained in detail later. Under the control of the counter 73, the attenuation ratio data for one line is stored.

On the other hand, when reading image information using the created attenuation ratio data, the peak hold circuit 61 controls the image signal 2 output from the programmable attenuator 24.
7 is selected. At this time, the latch circuit 74
The 8-bit attenuation data read out from 72 through the OR gate group 75 is latched pixel by pixel in order and supplied to the programmable attenuator 24. That is, in this state, the programmable attenuator creates an image signal 27 with the shedding corrected, and this
The A/D converter 64 performs A/D conversion at a level matching the ground color of the original.

The corrected signal 65 after conversion can be used as it is in a digital recording device or a digital display device.

The specific operation of this reading device, which has been outlined above, will now be described.

RAM Clearing Operation Now, in this reading device, it is necessary to clear the attenuation ratio data for shading correction described above before writing it into the RAM 72. This RAM clearing operation is performed in a one-line scanning section immediately before creating data for shading correction. In this scanning period, the line counter 81 for selecting the latch output of the addressable latch circuit 68 is in a disabled state, and even if the main scanning start signal 82-1 for the first line is supplied, the line counter 81 is disabled. Do not start counting operation synchronized with .

Further, the addressable latch circuit 68 is also in a disabled state during this one-line scanning period, and is in a state in which it does not latch the selection signal 83 supplied from the multiplexer 67. Therefore, it is an output terminal for 6808 bits of addressable latch circuit. . From -08 onwards, all “0” in this state
The latch circuit output data 84 will be output.

On the other hand, the 8 output from the latch circuit 74 during this scanning period
The bit parallel attenuation data 85 is blocked by the gate control signal 88 of the signal "o" supplied to each AND gate 87 of the AND gate group 86, and the 8-bit gate output data 89 is also all signaled. “It is in a state of disrepair.

The eight exclusive OR gates 91 constituting the exclusive OR gate group 69 perform an exclusive OR on the latch circuit output data 84 and gate output data 89 by associating them with one bit each, and all eight bits are " Gate output data 92 of 0'' is output. During this scanning period, the 3-state buffer 71 is enabled, and this gate output data 92 is supplied to the eight input/output terminals I10 of the RAM 72.
be provided. This all-0 gate output data 92 is sequentially written into the RAM 72 by address information outputted from the address counter 73 in synchronization with the video clock 93.

In the reading device of this embodiment, the image sensor 21 synchronized with the video clock 93 separates one line into 2048 pixels for reading. Therefore, the address counter 73 uses the 11-bit address information to
All "0" signals are sequentially written to each address of 2o47.

When the scanning of the first line is completed in this way, the RA
The clearing operation of M72 ends. Attenuation ratio data for shading correction is sequentially created in RA and M72 in the subsequent 8-line main scan.

Attenuation ratio data creation operation Now, the image sensor 21 starts scanning the document for the first line when the main scanning start signal 82-1 for the first line is supplied, and scans the normally white document portion for shading correction. to photoelectric conversion. Image signal 26 obtained by this
is manually input to the peak hold circuit 61, and its peak value v
xEp+ is detected (Figure 8a). Peak value ■, l□
, are held during scanning of the second to ninth lines, and are supplied to the A/D converter 64 as a holding signal 63.

By the way, in this reading device, in the scanning of the second to ninth lines in the process of creating attenuation data for shading correction, the video clock 93 receives a signal in the first half of the reading operation of each pixel, as shown in FIG. 9a. The signal becomes "1" and repeats a signal change such that the signal becomes "0" in the latter half section.

Further, the gate control signal 88 repeats the opposite signal change as shown in the figure. Also 3-state buffer 7
1 is enabled every half cycle as shown in Figure C.
E" and disable "D" states are repeated.

Therefore, in the first half cycle of the first pixel on the second line, the AND gate group 86 has all gates closed by the gate control signal 88, and the 8-bit gate output data 89. ~898 are all signals “0′”
becomes. In this cycle, the state setting signal 96 kept at signal “1” is selected by the multiplexer 67, and is supplied as the selection signal 83 to the addressable latch circuit 68. At this time, the line counter 81 outputs a count value of "1" in response to the main scanning start signal 82-2. Therefore, the selection signal 83 of signal "1" is output from the first output terminal 0° to the first latch circuit output terminal 84.
He will be listed as 1. At this time, other output terminals 01-0. The latch circuit output data 84□ to 84° of signal "0" is outputted from. Exclusive OR circuit group 69
corresponds these latch circuit output data 84 and gate output data 89 bit by bit and performs an exclusive OR. As a result, only the first gate output data 921 as the most significant bit becomes the signal "i" and the others 922 to 9
Gate output data 92 in which signal 26 becomes signal "0" is obtained. At this time, since the 3-state buffer 71 is in a disabled state, no data is written to the RAM 72. That is, the gate output data 92 represented as the signal "10000000" is latched by the latch circuit 74 and supplied to the programmable attenuator 24 as the attenuation data 85 in the next half cycle.

In the second half of the cycle for the first pixel, the programmable attenuator 24 attenuates the image signal 26 to, for example, 75% based on the gate output data 92 in the signal state described above. In this attenuation state, programmable attenuator 2
The image signal 27 for 2048 pixels sequentially output from A
/D converter 64, where A is input to the corrected image signal 65.
/D converted. In this embodiment, the correction signal 65 has an 8-bit configuration, and the peak value VllEF+ is converted to the maximum value to multi-value the signal level in 256 steps. Correction image signal 65
is supplied to an IC-based comparator 66 and compared with a reference value signal 97 representing, for example, a voltage level of 50% of the peak value V I HF I. And the sixth proposal above
The corrected image signal 65 is binarized using the reference value signal 97 as a threshold level using the same principle as shown in the figure. That is, when the signal level of the corrected image signal 65 is smaller than that of the reference value signal 97, the signal "1" is outputted from the comparator 66 as the comparison signal 98, and the signal "1" is outputted from the multiplexer 67.
is supplied to If the signal level of the correction signal 65 is other than this, the comparator 66 outputs a signal "0" as the comparison signal 98.

In the second half cycle of this first pixel, the comparison signal 9
8 are compared by a multiplexer 67 and a selection signal 83
The signal is supplied to the addressable latch circuit 68 as a signal. In the addressable latch circuit 68, this signal ``'1'' or 0
" is output from the output terminal ○ as the first latch circuit output data 84. At this time, the other output terminals 01 to 0
1, the latch circuit output data 8 with the signal “0”
42 to 848 will be output.

In this state, the exclusive OR gate group 69 performs an exclusive OR operation on the latch circuit output data 84 and the gate output data 89 while correlating them bit by bit. As a result, if the first latch circuit output data 841 is a signal "1", the first gate output data 921
becomes a signal "0". Also, latch circuit output data 84.
is the signal “0”, the first gate output data 921
becomes the signal "1 Pa." The second to eighth gate output data 922 to 928 each become the signal "P0" as a result of exclusive ORing of the signals "1". 8-bit parallel gate output data 92 is enabled 3
- supplied to RAM 72 via state buffer 71;
The data is written to the memory area of the first pixel designated by address counter '73. RAM like this? 2
A signal "1" is written as the most significant bit only when the signal level of the image signal 27 is higher than that of the reference value signal 97. The most significant bit as the attenuation data 85 is determined for the second to 2048th pixels by the same operation as described above. In this way, the first scan (second line scan) for shading correction is completed.

In the first half cycle of the first pixel in the next third line of scanning, the state setting signal 96 of signal “1” is selected by the multiplexer 67 and supplied as the selection signal 83 to the addressable latch circuit 68. The addressable latch circuit 68 selects the output terminal 01 as the count value of the line counter 81 is counted up to "2",
The second latch circuit output data 842 is converted into a signal "1"'
Make it. At this time, other latch circuit output data 841.8
43 to 846 become the signal "0". On the other hand, RAM? 2 reads out 8-bit data from the memory area of the first pixel and supplies it to the OR gate group 75 in this first half cycle. Therefore, the latch circuit 74 latches the OR output in which the read 8-bit data and the gate output 92 are associated one bit at a time. The attenuation data thus output from the latch circuit 74 determines the attenuation ratio of the programmable attenuator 24 in the second half cycle of the first pixel. This means:

(2) For image signals whose peak value VREFI is less than 50% even after the initial 75% attenuation, a signal "11000000" is set in the programmable attenuator 24 in order to determine whether further attenuation is appropriate. As a result, a signal "11000000" is written in the memory area of the RAM 72 for pixels corresponding to document portions that require further increase in attenuation ratio. For other pixels, the signal “100oooo
o” is written again.

■On the other hand, the peak value V * at the first 75% attenuation
For an image signal whose value is less than 50% of p p +, the appropriateness of attenuation is examined by lowering the attenuation ratio by one step. In this case, the signal "01000000" is set to the programmable attenuator 24, and the comparator 6
As a result of the comparison operation in step 6, the signal “01000000” or “o o o o o o
o o'' will be written. The same goes for the 2nd to 2048th pixels in the third line scan.

Regarding the scanning of the fourth line to the ninth line, the image sensor 21 successively reads the white portions of the document for shading correction, and sequentially converges the attenuation ratio toward the lower bits. This principle is the same as that explained in FIG. 6, and as a result, an attenuation ratio is determined to obtain an image signal output corresponding to 50% of the peak value V IIEF + for the white portion of the document. This attenuation ratio data is stored in RAM when the scanning of the 9th line is completed. 2, writing ends for each pixel.

Reading Operation Once the attenuation data as a pattern representing the attenuation ratio in the main scanning direction is created as described above, necessary image information is read using this data. At this time, the 3-state buffer 71 is held in a disabled state, and the RAM 72 is read-only. i.e. 1
Attenuation ratio data is repeatedly read out from the RAM 72 for each line, and is supplied to the programmable attenuator 24 as attenuation data 85 to adjust the attenuation ratio for each pixel of the image signal 26.

By the way, the programmable attenuator 24 has an image signal of 2G.
Since the shading is corrected by attenuating the image signal 26, it is natural that the peak value VRep+ of the image signal 27 after attenuation is lower than the peak value VREFI of the image signal 26 before attenuation. For example, when one line of a blank portion of a document is read using the attenuation ratio data set in the RAM 72, the peak value VREF2 becomes as shown in FIG. In this embodiment, the signal level of the reference value signal 97 is the previous peak value VIEF.
Since it is 1/°2 of that of I, the relationship between these is as follows.

VREFI = VllEF2 Therefore, if the image signal 27 after attenuation is A/D converted in the same way as when creating data for shading correction, in the case of this embodiment, 256-level expression cannot be performed, and half of that, 128 It can only express gradation in stages.

Therefore, in order to utilize the A/D converter 64 at full scale, in this reading device, the image signal 27 is sent to the peak hold circuit 61 on the first line of the reading operation (the 10th line when combined with shading correction, etc.). The peak value VRE,2 is detected manually. and hold this signal 6
3 to the A/D converter 64, and the white level and black level of the image signal 27 are placed at both ends of the signal level of the corrected image signal 65. In this way, depending on the peak value VREF2, A
Since the conversion of the /D converter 64 is controlled, even if the background color of the part for which shading correction data is created and the part of the document to be actually read differs, this will be corrected at the stage of the correction image signal 65. Become.

In the embodiment described above, the damping ratio data is stored in one RAM, but as explained in the previous proposal, it may be divided and stored in several RAMs. The same applies to amplification factor data used when performing shading correction by changing the amplification factor. It is also effective to write the attenuation ratio data or amplification factor data into a ROM (read-only memory) and fix it, as long as it corrects variations between individual reading devices.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to control the conversion of the A/D converter using the peak hold circuit, so it is possible to improve the accuracy of various types of originals without having to create shading correction data for each original. It is possible to perform high-quality image reading.

[Brief explanation of the drawings] Figure 1 is a schematic configuration diagram showing the general configuration of the optical system of the reading device, and Figure 2 shows non-uniform illuminance when a fluorescent lamp is used as the light source of the reading device. Explanatory diagram showing the situation, Part 3
The figure shows various waveform diagrams to explain image signal deterioration during conventional analog image signal binarization processing, and Figure 4 shows waveform processing of a shading correction device previously proposed to prevent image signal deterioration. 5 is a circuit diagram showing the main parts of the reading device proposed earlier by the inventor,
Fig. 6 is various waveform diagrams showing the process of creating correction data by this reading device and waveforms after shading correction;
9 to 9 are for explaining one embodiment of the present invention, FIG. 7 is a block diagram showing the main parts of the reading device, and FIG. 8 is various waveform diagrams expressing the concept of two peak values. , and FIG. 9 are various timing charts when creating shading correction data. 21... Image sensor, 24... Programmable attenuator (programmable gain amplifier), 26.27... Image signal, 61... Peak hold circuit, 63.・・・・・・
・Holding signal, 64...A/D converter, 65...Corrected image signal, 66...Comparator, 68...Addressable latch circuit, 72 ...
...RAM (storage means), 97...Reference value signal. Applicant Fuji Xerox Co., Ltd. Agent Patent Attorney Umeo Yamauchi Figure 1 Figure 2 (1 (

Claims (1)

[Claims] A programmable gain amplifier that inputs serial image signals for each line obtained from a photoelectric conversion element by line scanning of a document and attenuates or amplifies them at a predetermined attenuation ratio or amplification factor, and an image output from this programmable gain amplifier. An analog-to-digital converter converts the signal into a digital signal, and the image signal output from the photoelectric conversion element or the image signal output from the programmable gain amplifier is selectively manually input and the peak value of the signal level is maintained. and a peak hold circuit which supplies this to the analog-to-digital converter as a signal for controlling the conversion amount; a data creation means for comparing an image signal output by the converter with a predetermined reference value to create attenuation ratio data or amplification factor data for shading correction in the line scanning direction; and a storage means for storing the created data. and when the attenuation ratio data or amplification factor data stored in the storage means is applied to the programmable gain amplifier and the peak hold circuit holds the signal output from the programmable gain amplifier as a peak value, the analog - A reading device characterized in that a shading-corrected image signal is obtained from a digital converter.