JPS60231950A - Head servo circuit - Google Patents

Abstract

PURPOSE:To prevent a ROM from the increase of circuit size by dividing the constitution of frequency division into a part for setting a frequency dividing ratio corresponding to the recording mode of a signal recorded in a magnetic tape and a part for setting a frequency dividing ratio corresponding to the reproducing mode and connecting respective parts in series. CONSTITUTION:A reference signal generating circuit 31 generates a reference signal by alternately actuating a circuit consisting of a counter 312 for generating the 1st signal component, a counter 315 for generating the 2nd signal component and frequency dividing circuits 317, 318 on the basis of respective outputs and an RS FF320. The counter 315 is always kept at loading state by guiding its frequency-divided output and the frequency-divided output of the counter 312 to a load terminal L through an OR circuit 321. Thus, the ROM can be prevented from the increase of circuit size and a practical head servo circuit can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a video tail recorder (hereinafter referred to as VTR) and the like.

[Technical background of the invention]

For example, in home VTRs, video signals are generally recorded and reproduced using a rotating magnetic head. A head servo circuit is also provided to control the rotational phase and rotational frequency of the head. Further, a capstan serve circuit is provided to drive the magnetic tape at a constant speed during recording, and to drive the magnetic tape in synchronization with the video signal recorded on the tape during playback.

By the way, when performing so-called variable speed playback where the tape running speed during playback (hereinafter referred to as playback speed) is different from the tape running speed during recording (hereinafter referred to as recording speed), the relative speed between the magnetic tape and the rotating magnetic head changes. This is different from that of normal playback (so-called 1x speed playback where the recording speed and playback speed are the same).
The frequency of the reproduced horizontal synchronization signal changes.

If this deviates outside the synchronization pull-in range, screen disturbances will occur,
Even if it falls within the pull-in range, color shift will occur on the screen due to the time lag between the color signal and the luminance signal.

In order to prevent the above-mentioned problems, it is necessary to change the rotational speed of the rotating magnetic head according to variable-speed playback, so that the relative speed between the rotating magnetic head and the magnetic tape during variable-speed playback is the same as that during normal playback. There is a need to.

The following two methods can be considered.

(1) Frequency control is applied to the rotating magnetic head based on the reproduction synchronization signal. The rotational frequency of the rotating magnetic head is controlled so that the frequency of the reproduced horizontal synchronizing signal always remains constant.

FIG. 1 shows its circuit configuration, where 1 is a Herad motor, 12 is a motor drive amplifier circuit, and 13 is a DC power supply. 14 is a voltage controlled oscillation circuit (■CO), and 15 is an oscillation output of this voltage controlled oscillation circuit 14 and a reproduction horizontal synchronizing signal (ps
, ), 16 is a frequency discrimination circuit, and 17 is an addition circuit.

(2) Set the period of the reference signal of the phase control system of the head servo circuit to a value different from that of normal reproduction according to variable speed reproduction, and correct it by giving an offset to the frequency control system at the addition point with the frequency control system. I do.

FIG. 2 shows the circuit configuration thereof. To explain the phase control system, 21 is a rotational phase detector, 22 is a Schmidts) trigger circuit, 23 is a reference signal generation circuit, and 24 is a phase comparison circuit. The reference signal generation circuit 23 is a mode decoder 231
, ROM 232, and presettable counter 233. To explain the frequency control system, 25 is a rotation frequency detector, 26 is an amplifier circuit, 27 is a Schmitt trigger circuit, 2
8 is a frequency discrimination circuit, and 29 is an addition circuit.

[Problems with background technology]

Method (1) above is a method that has been commonly used in the past, but the frequency control system may become unstable due to noise signals generated when the rotating magnetic head crosses the track or loss of video signals. There is a drawback that transient response characteristics deteriorate when switching between normal playback and variable speed playback.

Method (2) involves preparing reference signals with different cycles equal to the number of playback modes (types of playback speeds) multiplied by the number of recording modes (types of tape speeds during recording), and The reference signal is selected according to the mode. In this case, assuming that the period of the reference signal during normal reproduction is T1'', the period 'Tn'' during variable speed reproduction is as follows.

αH Tn=TI(1+ −(i−n)) ・(1)H However, n: Double speed number, integer NR: ] Number of horizontal synchronization signals in the field period αH: Number of H rows on the Chive pattern This (2) In the case of method (1), the output of the same detectors 21 and 25 as for normal regeneration can be used as the feedback signal for the control system during variable speed regeneration. The transient response characteristics are stable.

However, in the conventional circuit that implements method (2), as shown in FIG. This presettable counter 233
ROM that stores preset data (branch ratio data)
The problem of increasing the size of the 232 circuit is a real problem.

[Purpose of the invention]

The present invention has been made in view of the above points, and an object of the present invention is to provide a head chip circuit that can prevent the circuit scale of the ROM from increasing in the method (2) described above.

[Summary of the invention]

This invention focuses on the fact that the reference signal has a first signal component whose period changes depending on the recording mode and a second signal component whose period changes depending on the recording mode and playback mode, and divides these components over time by dividing the clock signal. A reference signal is created by alternately generating the second signal component.In this case, the frequency division configuration of the means for generating the second signal component is adjusted to a division ratio according to the recording mode of the signal recorded on the magnetic tape. It is divided into a part for setting and a part for setting the division ratio according to the playback mode.
These are configured to be connected in series.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

First, the present invention will be explained in detail.

If the above equation (1) is transformed, it becomes the following (2).

αH Tn=TI+'h-(1-n)-(2)N.

In the right side of equation (2), the first term "T1" is the period of the reference signal during normal reproduction αH, and the second term "'r1y-('
1-n)" is "'(
In)".

N.

By the way, IIT, #, IIαH# change depending on the recording mode υ, "(1-n)7 changes depending on the playback mode, and NII is a constant. Therefore, the first term “T1. " can be regarded as a periodic component whose value changes depending on the recording mode, and the second term" T1 blood (
1-n)” is the recording mode and re-N.

It can be regarded as a periodic component whose value changes depending on the mode. The period "Tn'" is the sum of the above two period components.

Therefore, the present invention provides means for generating a signal component having a period of the first term "T1" (hereinafter referred to as the first signal component and the second signal component), and connects these two circuits. By alternating operations as shown in Figure 3, 'T
A reference signal having a period of n# is obtained.

In addition, in FIG. 3, the period "TI S (1-n)" is indicated by NH Ta'.

The circuits corresponding to these two parts are set in the second signal component generating means. In other words, when the second signal component generating means divides the clock signal according to the recording mode and the reproduction mode, αH and NH having a period of the second term 'TI-(1-n)'' are used. The means for generating signal components is divided into a part for setting a division ratio according to the recording mode and a part for setting a division ratio according to the reproduction mode, and these parts are connected in series.

According to such a configuration, the number of division ratio data stored in the ROM is not given as a multiplication value of the number of recording modes and the number of reproduction modes, but as the sum of both. Therefore, the number of branch ratio data stored in the ROM can be reduced, and the circuit scale can be prevented from increasing.

Here, the present invention is applied to V of the β format of the NTSC system.
An embodiment of the present invention will be described in detail, with a case where it is applied to a TR as a representative example.

In the case of V'l'H in the above method, NH is a fixed value of 262.5. There are three types of recording modes (hereinafter referred to as β■, β■, and β■ for convenience), and αH in each mode is α, ==l, 5 (β■).

0.75 (βIf) and 0.5 (β■).゛If αH is used as it is, there will be multiple division ratios to be set by the second signal generation means, and the configuration of this means will be complicated. Therefore, in this embodiment, equation (1) is modified to Recording mode (β■), (β■).

We created three equations for (β■) to simplify the division ratio.

That is, equation (1) is first transformed as follows.

Tn=(1+-'-(1-n))T1-(1)N.

05 Here, assuming that ΔT=- is the morbidity T, this ΔT is used to express equations (3), (4), and (5), as well as equations (3) and (4).

α■ in (5) is 1.5, 0.75, and 0.5, respectively.
By substituting , equations (3), (4), and (5) can be expressed as follows.

In equations (6) # (7) and (8), the first term "
(TI-90ΔT)# is shown with the same value, but the recording mode (
β■), (1m).

If (β■) changes, T1'' changes, so it is a periodic component that changes depending on the recording mode (hereinafter, this period will be referred to as TA).

The second term “6ΔT (16n) ” + ” 3ΔT(
31-n) "'2ΔT(46-n)" is a periodic component that changes depending on the recording mode and reproduction mode (hereinafter, this period will be referred to as Tit). Among these, Pa6ΔT#, I
I 3ΔT#.

2ΔT# is a component that changes depending on the recording mode.
16-n)', ``(31-n)'', ``(46-n
)” is a component that changes depending on the playback mode.

FIG. 4 is a circuit diagram showing the circuit configuration of an embodiment of the present invention. Please note that Fig. 4 is different from the previous Fig. 2 because it shows the reference signal generation circuit 31.
The structure is different, but other parts are the same, so the same parts are given the same reference numerals.

In FIG. 4, the first signal component with the period II + rA'' of the first term of equation (6), (7, (8)) is
It is made up of a presettable counter 312 that counts a clock signal (cp) applied to a terminal 311. Preset data (frequency division data) of this counter 312 is stored in ROM JJ3.

ROM J I J has recording mode (II), (β
■).

Three pieces of data corresponding to (1m) are stored.

This preset data can be read using mode encoder 3.
It is done by 14. This mode encoder 314 encodes the discrimination output (Sl) of a recording mode discrimination circuit (not shown) to generate an address signal for the ROM 313. Therefore, the counter 312 obtains a first signal component with a period Tm'' corresponding to the recording mode.

Next, a description will be given of the part that generates the second signal component having the period "rr, ill" of the second term of the above equations (6), (7), and (8).In this example, the second term Components "6ΔT", 3ΔT#, 11 that change depending on the recording mode in
2ΔT# is further changed to 6ΔT” and “t 6 m, n 3
It is divided into two components: m and '2 m.

In this case, the signal component with a period of "ΔT" is at the terminal 32.
A presettable counter 315 counts the clock signal (cp) applied to the clock signal (cp). The reset data of this counter 315 is stored in the ROM 316.
is stored in.

The ROM 316 has recording modes (β■) and (β■).

Preset data having different values depending on (β■) is stored. Each preset data is stored in the mode encoder 31.
It is read out by the encoded output of the recording mode discrimination output (Sl) output from 4.

The output of counter 315 is given to frequency divider circuit 317.

The frequency dividing circuit 317 divides the frequency by 6 and divides by 3.

Three division ratios of frequency division by 2 can be set. For example, the mode encoder 314 uses a 2-bit selection signal to
One of the three division ratios described above is set according to the recording mode discrimination output (Sl). As the output of this frequency dividing circuit 317, signal components having periods of 6ΔT'', ``3ΔT'', and ˚2ΔT'' are obtained.

The output of this frequency dividing circuit 312 is given to a frequency dividing circuit 318, and is provided for division according to the reproduction mode. That is, the frequency dividing circuit 318 can set the division ratio according to the reproduction mode,
The selection data is stored in ROM 319. The data is read by the mode encoder 314, which encodes the playback mode designation signal (S2) and designates the address of the ROM JJ9. Accordingly, from the branch circuit 318,
'6ΔT(16-n)'','3ΔT(33-n)
”.

A signal component with a period of 2ΔT(46-n)'', t,
A second signal component having a period "TB" of the b second term is obtained.

1st. The second signal component is created as described above, but it can be used to create a signal component with a period of M 7n# in the following manner. That is, the counter 312 loads the preset data only when the divided output is obtained from the Q output terminal of the frequency dividing circuit 318, and the first
generates a signal component of Also, the frequency divider circuit? When a divided output is obtained from the Q output terminal of 1B, the RSS flip flow 9 circuit 320 becomes set state, and the frequency dividing circuit 317
．． 318 into the reset state.

This RS frizzo flop circuit 320 is a counter 312
The frequency dividing circuit 31 enters the reset state by the frequency divided output.
7,318 is reset. Therefore, a reference signal having a period of (TA+TB) is obtained from the counter 312.

In this way, the reference signal generation circuit 31 in FIG. Output and RS flip-flop 3
20 are operated alternately to generate a reference signal.

Note that the counter 315 uses its divided output and the counter 312
The divided output of is sent to the load terminal (L) via the OR circuit 321.
It is always in a loaded state by being led to the motor.

FIG. 5 shows a timing chart in the (β■) recording mode and the 12 times speed playback mode. Time (t
5(a) as shown in FIG. 5(a), the Q output of the RS frizzo flop circuit 320 becomes high level as shown in FIG. 5(b). The reset circuits 317 and 318 are released. Accordingly, the frequency dividing circuit 317 divides the divided output of the counter 315 shown in FIG. 5(e) by 1/6, and divides the divided output of the counter 315 shown in FIG.
Obtain the branch output shown in . Since the playback mode is 12x speed mode, n=12, and according to equation (6), 16-
n-16-12=4, and the frequency divider circuit 318 divides the divided output of the frequency divider circuit 317 into four. Frequency dividing circuit 318
The branch output of is generated at the time (t2) delayed by ITA'' from the time (tl), and according to this timing, the counter 31
2 starts counting. Therefore, counter 312
A reference signal with a period of ``TA+TB'' is obtained from .

〔Effect of the invention〕

As described above, according to the present invention, it is possible to prevent the circuit scale of the ROM from increasing, and it is possible to provide a practical head control circuit.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing an example of a conventional Herad servo circuit.
FIG. 2 is a circuit diagram showing another example, FIG. 3 is a timing chart for explaining the invention in detail, FIG. 4 is a circuit diagram showing the circuit configuration of one embodiment, and FIG. 4
5 is a timing chart for explaining the operation shown in the figure. 31... Reference signal generation circuit, 311... Terminal, 31
2.315...Zori settable counter, 31 J
, 316.319-RQMl 314 %-de encoder, 317.318... Branch circuit, 320... RS
Frizzo Frozzo circuit, 32-OR circuit. Figure 1 Figure 2

Claims (1)

[Claims] The relative speed between the rotating magnetic head and the magnetic tape is kept constant by changing the period of the reference signal of the phase control system according to the reproduction mode and recording mode of the signal recorded on the magnetic tape. A first signal that is included in the reference signal and that generates a first signal component whose period changes depending on the recording mode by dividing the clock signal according to the recording mode in the circuit. A component generating means, a first branching section for setting a branching ratio according to the recording mode, and a second branching section for setting a branching ratio according to the reproduction mode are connected in series, and a clock signal is transmitted. Said 1st. A second signal component that is included in the reference signal and generates a second signal component whose period changes depending on the recording mode and the reproduction mode by dividing the frequency in the series circuit of the second division section. generating means; and the first. A head servo circuit characterized in that a reference signal generating circuit includes a reference signal generating means for generating the reference signal by alternately operating the second signal component generating means.