JPS60231369A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the resistance of a gate and to improve a noise index in a semiconductor device having an FET structure, by arranging a plurality of gate- potential supplying electrodes in a region on the side of a source electrode and a region including the side of a drain electrode. CONSTITUTION:On a compound semiconductor substrate 10, a source electrode 12 and a drain electrode 13 are arranged so as to hold a gate electrode 11 and connected to a source region 16 and a drain region 17 electrically. Feeding points Pa and Pb in the vicinity of both ends of the gate electrode 11 are electrically connected to a gate potential supplying electrodes (gate pads) 14a and 14b of a pattern, which is surrounded by the source electrode 12. A feeding point Pc at the center is connected to a gate pad 14c, which is arranged in the region on the side of the drain electrode 13. The feeding points to the gate electrode are increased without increasing the size of a chip and without using a complicated structure such as multilayer wirings, and the resistance of the gate can be reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device having an FET (field effect transistor) structure, and is particularly applicable to an ultra-high frequency FET such as a GaAs (gallium arsenide) FET. This is preferable.

[Background technology and its problems]

In recent years, so-called satellite broadcasting has been realized, which uses broadcasting satellites in geostationary orbit to broadcast high-quality video, PCM audio, etc. using ultra-high frequency signals in the 12 GHz band. For purposes such as
FET (field effect transistor) for ultra-high frequency with low noise
demand is extremely high.

Here, an ultra-high frequency FET such as a GaAs (gallium arsenide) FET can be represented by any number of circuits as shown in Figure 1, and the general formula that can be claimed as the noise figure (NF) is , becomes. In this formula 0,
Kf is a constant unique to the element called the so-called finning factor, Cgs is the gate-to-north capacitance (so-called input capacitance), RI is the gate resistance at high frequency, Rs is the source resistance, and pm is One possible method for reducing the FET's transfer conductance, 0, as a noise figure, Fo, is to reduce the gate resistance R7.

This gate resistance R1 can be expressed as follows, where Rt is the resistivity, Zu is the unit gate width, S is the gate cross-sectional area, and 21 is the full gate width. Here, as shown in FIGS. 2A to 2C, the unit gate width Zu decreases as the power supply point P for the gate electrode 1 having a total gate width of 21 increases. That is, the unit gate width Zu in FIG. 2A with one feeding point is Zu=Zt/
2. In Figure 2B, where there are two feed points, Zu = Zt/4, and in Figure 2C, where there are three feed points, Zu = Zt/6.Generally, N feed points are in the form as shown in Figure 2. When provided, the unit gate width Zu is Zu=Zt/2N. Therefore, with respect to the gate resistance RII when there is one feeding point (N=1), R and p are 1/4 when there are two feeding points (N〒2), and three (N= R at the time of 3)
t becomes 1/9, and in general, when there are N feeding points, the gate resistance Rt decreases to 1/N2, and Fok as the above-mentioned noise figure can be reduced accordingly.

However, when the power supply points Pk for the gate electrode 1 are increased, the number of electrodes, so-called bonding pads, for supplying gate potential to each power supply point increases, resulting in an increase in the pattern area and the chip size. be. That is, in Figure 3 A, B, and C, each of the nine feed points P is one.
FIG. 2 is a plan view schematically showing each electrode pattern in the case of one electrode, two electrodes, and three electrodes, in which a source electrode 2 is sandwiched between a gate electrode
and the drain electrode 3 are arranged to face each other. These third
In Figures A and BXC, the gate potential supply electrodes, so-called gate pads 4, are both source electrodes 211! It is placed in l. This connects the gate pad 4 to the drain electrode 3.
This is to prevent an increase in the drain-gate capacitance Cdt when disposed on the side, and to surround and shield the gate pad 4 by the source electrode 2, which is normally held at ground potential.

Regarding the maximum length W of the electrode pattern outline in Fig. 3 A, B, and C, the above maximum length kW1 in [Fig. 3 A] when there is one feeding point P, and when there are two feeding points P (Figure 3B)
When the above maximum length hW2 and the number of feeding points P are three (Fig. 3C
) is the above maximum length W.

Then, Wl < W2 < Wa ′, and
As the number of feeding points increases, the maximum length of the pattern outline increases, resulting in a larger chip size. As the chip size increases, not only does the cost of materials such as GaAs substrates increase, but also the yield of the product deteriorates, and the package also becomes larger, which is undesirable.

Although it is possible to increase the number of feeding points without increasing the number of bonding pads by using multilayer wiring, in order to prevent an increase in the gate-to-north capacitance (input capacitance) C2s, it is necessary to use a thick insulating film with a low dielectric constant. It is necessary to form an interlayer insulating layer by a CVD method or the like, and further steps such as opening a contact window are required, which complicates the manufacturing process and increases manufacturing costs.

[Purpose of the invention]

In view of the above points, the present invention increases the number of power feeding points to the gate electrode without using a complicated structure such as multilayer wiring, without increasing the template size or the maximum length of the pattern outline,
It is an object of the present invention to provide a semiconductor device that can reduce gate resistance Ryt and improve noise figure.

[Summary of the invention]

That is, the feature of the semiconductor device according to the present invention is that in a semiconductor device in which a gate electrode is disposed between opposing source and drain electrodes, a plurality of potential supply electrodes to the gate electrode are provided. The gate electrode is arranged in a region including a source electrode side region and a drain electrode side region with respect to the gate electrode.

〔Example〕

FIG. 4 is a schematic plan view showing the electrode pattern of the FET according to the first embodiment of the present invention, and FIG.
FIG.

4 and 5, on a compound semiconductor substrate 10 such as GaAs (gallium arsenide), a gate electrode 11 made of a Schottky-contacting metal material (for example, tungsten silicide) is formed with a predetermined gate length Lfs. It is deposited and formed with a predetermined gate width 21. A source electrode 12 and a drain electrode 1 sandwich this gate electrode 11.
The source electrode 12 and the drain electrode 13 are in ohmink contact with the source region 16 and drain region 17, which have high impurity concentration and low resistance and are formed by diffusion or the like facing the surface of the semiconductor substrate 100, and which are arranged facing each other. electrically connected. The gate electrode 11 is provided with two power supply points Pa and Pb at positions Zt/6 inside from both ends in the longitudinal direction (gate width direction), and one power supply point Pc at the center position. The width Zu is Zt/6. Of these three power supply points, two power supply points Pa and Pb near both ends are supplied with a gate potential of a pattern surrounded by the source electrode 12 inside the source electrode 12 side region through the lead electrode nosetan, respectively. Electrode, so-called gate bonding pad (hereinafter referred to as gate pad) 14a
, 14b. In addition, the central power feeding point Pc is connected to the drain electrode 1 via the lead electrode pattern.
It is electrically connected to the gate band 14c arranged in the third side region. These gate pads 14a, 14b.

14c each has a substantially square planar shape, and the length of the negative side is required to be at least 50 μm in order to perform so-called wire bonding, and is generally set to 50 μm to 80 μm. In addition, the source electrode 12 and the drain electrode 13 also require bonding pad portions of comparable or larger dimensions. On the other hand, the gate width 21 is, for example, 200 μm.
m (or 300 μm), and if a plurality of gate pads are provided only on the source electrode side, the maximum length of the source electrode will be extremely increased as shown in FIG. 3 above.

By the way, as mentioned above, disposing the gate band not only in the source electrode side region but also in the drain electrode side region increases the drain-gate capacitance Cdp'(r) and reduces the shielding effect of the source electrode. This has not been attempted in the past because it is predicted that the above capacitance Cdt exists between the input and output of the FET capacitance and acts as a feedback capacitance, especially when controlling the gain. (gain) decreases.

Contrary to such common knowledge, the inventors of the present invention determined the present invention by disposing the gate pad also in the drain electrode side region and comparing the characteristics with an FET with the same dimensions (chip size) and a conventional electrode pattern. This is an invention that has been achieved.

That is, when a conventional electrode pattern is used for a semiconductor chip 10 of the same size, as shown in FIG. 6, two power supply points P? z can be set, and the unit gate width Zu is Zt/4. Now, the gate lengths Lt in the electrode patterns shown in FIGS. 4 and 6 are set to be equal to each other, 0.5 μm and 1 μm, respectively.
Other conditions, such as the gate width 21 and the source electrode width W2, which is the maximum length of the electrode pattern, are made equal to each other, and GaAs semiconductor chips 10 of the same size are used to form an FET'!
r configuration, the gain Ga when the input signal frequency is 12 GHz is approximately equal to 9 dB, and the noise figure N
F is approximately 1.5 dB in the conventional example (Fig. 6), whereas it is approximately 1.25 dB in the case of the embodiment of the present invention (Fig. 4).
Excellent dB characteristics were obtained. This NF value of 1.25 dB at 12 GHz can only be achieved with a conventional structure when using a fine gate electrode pattern with a gate length Lt of 0.3 μm, and requires advanced ultra-fine patterning technology. However, the present invention example (
According to FIG. 4), the above NF value can be obtained by using a gate electrode pattern with Lf of 0.5 μm. cdp
Although this increases from approximately 20 fF in the conventional case to approximately 30 fF in this embodiment, the effect of reducing the gate resistance Rf by increasing the power supply points to the gate electrode 11 is greater, and as a result, ultra-low noise can be achieved. It is something that

Therefore, according to the first embodiment of the present invention, the sixth
Although the chip size is the same as the conventional structure shown in the figure, the number of power feeding points for the gate electrode 11 can be increased from two to three without using a complicated structure such as multilayer wiring. Ultra-low noise can be achieved by reducing the resistance Rf. Here, for example, the noise figure NF in a super high frequency band of about 12 GHz is a gate length of 0.3.
It is possible to obtain 1.25 dB'i with a gate length of 0.5 μm, which is comparable to μm, and combined with the above-mentioned no need for multilayer wiring, the manufacturing process can be simplified and the chip size can be reduced, resulting in cost performance. We can supply ultra-low noise FETs (r) for ultra-high frequencies with excellent performance.

Next, FIG. 7 is a schematic plan view showing an electrode pattern of an FET according to a second embodiment of the present invention. In FIG. 7, three power supply points Pa,
Pb and Pc are set, but two feeding points Pa
, Pb is the longitudinal direction of the gate electrode 21 [gate width direction]
Since the unit gate width Zu is located at both ends of Z
It becomes t/4. However, the chip size may be approximately the same size as the conventional case with one feeding point (Fig. 3A).
The characteristics can be improved compared to the conventional example of the same chip size.

In the second embodiment shown in FIG. 7, the drain electrode 23
Gate bands 24a and 24b are provided in the side region to be electrically connected to the feed points Pa and Pb, respectively, and gate pads 24c are provided in the source electrode 22 side region to be electrically connected to the feed point Pc. However, they may be provided on the gate electrode side of the gate bands 24a and 24b, and on the drain electrode side of the gate pad 24cffi, respectively.

Next, FIG. 8 shows a third embodiment of the present invention, in which power feeding points Pa''Pc'r are set at a total of five locations, ie, both end positions in the longitudinal direction of the gate electrode 31 and positions divided into four equal parts. Since the power supply points are provided at both end positions, the unit gate width Zu is Zt/8.Furthermore, the power supply points pa and Pb at both end positions and the power supply point Pc at the center position are electrically connected to each other. Gate pads 34d, 34ee are disposed in the drain electrode 33 side region, and are electrically connected to power supply points Pd, Pe at respective positions Zt/4 inside from both ends. first electrode 321
M! It is located in the I area.

In addition, as shown in the fourth embodiment in FIG. For example, 1/2 of the gate band area is arranged in the drain side region and the other I/2 is arranged in the source side region so as to span both the source electrode 42 side regions. Good too. The fourth embodiment has a total of three power feeding points, one at both ends and one at the center, as in the second embodiment, and the unit gate width Zu is Zt/4.
becomes. It is also possible to easily set five of these feeding points as in the third embodiment and make the unit gate width Zu'eZt/8.

〔Effect of the invention〕

According to the semiconductor device according to the present invention, the gate resistance R1 can be reduced by increasing the power supply points to the gate electrode without increasing the chip size or using a complicated structure such as multilayer wiring. It becomes possible to improve the characteristics, particularly the noise figure in the ultra-high frequency band, and to supply ultra-high frequency, ultra-low noise semiconductor devices at low cost.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing the equivalent circuit of FET, Figure 2 A-C
3 is a route diagram for explaining the unit gate width Zuk when the number of power feeding points to the gate electrode is 1 to 3, and FIGS. 3A to 3C are schematic diagrams showing electrode patterns corresponding to FIGS. 2A to C, respectively. A plan view, FIG. 4 is a schematic plan view showing the first embodiment of the present invention, FIG. 5 is a sectional view taken along the line v-v in FIG. 4,
FIG. 6 is a schematic plan view showing a comparative example using an electrode pattern of a conventional structure on a chip of the same size as that of the first embodiment;
FIG. 7 is a schematic plan view showing the second embodiment of the present invention;
The figure is a schematic plan view showing a third embodiment of the invention, and FIG. 9 is a schematic plan view showing a fourth embodiment of the invention. 11.21.31.41... Gate electrode 12.22
, 32, 42...source electrode 13.23, 33, 43
- Cloud - Drain electrodes 14, 24, 34, 44... Between gate potential supply electrodes 1) Sakae Mura - 15- Figure 4 Figure 6

Claims (1)

[Claims] In a semiconductor device in which a gate electrode is disposed between opposing source and drain electrodes, a plurality of potential supply electrodes to the gate electrode are provided, and these gate potential supply electrodes are connected to the source electrode side region and the drain electrode with respect to the gate electrode. A semiconductor device 0 characterized in that it is arranged in a region including a side region.