JPS60229366A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To fine the pitch width of a memory cell and memory itself by connecting a first conduction type wiring section to a drain and a gate through an insulating film on the gate and connecting a second conduction type wiring section to the drain through said insulating film. CONSTITUTION:Gate electrodes 57 are formed by first layer polycrystalline silicon containing a first conduction type impurity, and a second layer polycrystalline silicon wiring section 62a containing the first conduction type impurity is shaped on a first layer inter-layer insultaing film 59 coating the gate electrodes 57, and connected to a first conduction type drain region and the gate electrodes through a contact hole 61. A second layer polycrystalline silicon wiring section 63a containing a second conduction type impurity is shaped on the inter-layer insulating film while being connected to said wiring section, and connected to a second conduction type drain region 55 through a contact hole 61.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device, and particularly to a pair of CMOS
6-transistor type semiconductor memory 8H with inverter
related to.

(Technical background of the invention and its problems) A six-transistor type semiconductor memory device W (static memory) having a pair of CMOS inverters has a circuit configuration shown in FIG. 1. That is, Qt in the diagram) 1.0n
+ is an n-channel Mo5 t-transistor and an n-channel Mo8 t-transistor forming one CMOS inverter. Qp2 and Qn2 in the figure are the other CM
An n-channel Mo3 I-transistor forming an OS inverter, an n-channel Mo3 I-transistor. The gate of one CMOS inverter is the gate of the other CMOS
Common train portion D2 of each transistor of the inverter
In this case, the gate of the other CMOS inverter is connected to one CMOS inverter.
They are cross-connected to a common drain portion D+ of the S inverters to form a flip-flop circuit. Each of the above n
The sources of the channel MOS transistors Ql)+ and Qp2 are connected to VDD, and the n-channel MOS transistors Qn+ and Qn2 are respectively connected to Vss.

Transistors Qp+, Q of the flip-flop circuit
n+ common drain portion D1 and transistor Ql)
The common train portion D2 of 2.0n2 is set to approximately DD potential and Vss potential, and holds information. For example, when the common drain portion D+ is at vDD potential, the transistor QO2 is off and the transistor Qn2 is on, and the common drain portion D2 is at Vs s 1, so the transistor Ql)t is on and the transistor Qn+
is turned off. Further, Qn3.011 are Il+<n channel Mo5t~ transistors as transfer gates, one Mo8 t-transistor Qn3 is connected to the node of the flip-flop circuit, and the other MOS transistor Qn+ is connected to the node of the flip-flop circuit. ing. The drain sides of the transistors Qni and Qn+ are connected to pin 1 lines BL+ and B10, respectively, and the gates of the transistors Qn3 and Qn4 are connected to the word line WL. The transistor Q
n3 and Qrz are turned on when a memory cell is selected and writing or reading is performed, and are connected to the bit lines BL+ and B10 connected to the drain sides of transistors Qn and Qn4 and the flip-flop circuit. Information is transmitted between the two.

When writing information to the above-mentioned memory cell, for example, the common train portion D1 is set to Vss potential, and the common drain portion D2 is set to Vss potential.
When setting bit line BL1 to VDD potential,
is set to the Vss level and the pin 1-line BL2 is set to the VDD level, and the word line WL turns on transistors Qrz and Qrl as transfer gates. On the other hand, in the case of reading, the bit line BL
+, B10 are connected to a sense-up circuit (not shown) to form transistors Qn3 and Qn as transfer gates.
Turn on 4.

As the memory cell of the six-transistor static memory described above, structures shown in FIGS. 2 to 4 are conventionally known. QD+ and Qr+1 in the diagram are one of the CMs
There is an n-channel Mo3 l-transistor forming the OS inverter, an n-channel Mo3 l-transistor, Ql in the figure) 2.0n21,1, a ρ tunnel MO3 l-transistor forming the other CMOS inverter, and an n-channel Mo3+- transistor. , these CMOS inverters constitute a Noritsu flop circuit by cross-connecting the gate of one to the common drain portion of the other. In addition, Qn3.0n4 in the figure is each n
The channel MOS transistor Q r+ (connected to the drain side of Qn2) is an n-channel Mo3 I- transistor as a gate.

The p-channel MO3+ to transistor Ql)1, Q
l) 2 is an island-shaped n-type silicon substrate 2 separated by a field enhancement film 3 on which a p-well 1 is selectively formed, as shown in FIGS. are formed in each area. One transistor Ql)t is
A p+2 source 41 is formed on the island-shaped substrate 2 to be electrically isolated from each other. Said n-channel MO8I-transistor is disposed via a gate oxide H6 on the substrate 2, including a drain region 51 and a channel region between these source and train regions 41, 51. The gate electrode 7 is made of, for example, a first layer of n-type polycrystalline silicon doped with phosphorus, and is shared with the gate of the nl gate. the other transistor. p2 includes the p+ type source 41 and drain regions 52 formed electrically isolated from each other in the island-shaped substrate 2 region, and these source and train regions 4, . A first layer made of n-type polycrystalline silicon doped with phosphorus, for example, is disposed on the substrate 2 including the channel region between 52 and 52 with a gate oxide film 16 interposed therebetween, and is shared with the gate of the n-channel MO8l-transistor Qn2. It is composed of a gate electrode 72. Note that the p1 type source region 41 is connected to the transistors QD1 and Ql.
)2 and functions as a vDD line. Further, the transistors Qn1 and Qn2 are formed in island-shaped ρ-well 1 regions separated by a field oxide film 3, respectively. One transistor. nl is a well 1 which includes a source 42, a drain region 53, and a channel region between these source and drain regions 42 and 53, which are formed electrically isolated from each other in the island-shaped p-well 1 region. the first layer made of n-type polycrystalline silicon]
- It is composed of an electrode 71. The other 1-transistor Qn2 includes an n+ type source 43 and drain region 54 formed electrically isolated from each other in the island-shaped p-well 1 region, and these source and drain regions 4:l, 5.
The well 1 includes a channel region between 4 and 4, with a gate oxide film (not shown) interposed therebetween, and is composed of a layer 1 to an electrode 72 made of the first layer n-type polycrystalline silicon. Furthermore, one transistor Qn3 as the transfer gate is connected to an island-shaped well 1 as shown in FIG.
The drain region 53 is electrically isolated from each other in regions.
n+ type source and drain regions 55 common to
A first layer n doped with phosphorus, for example, is placed in the well 1 region including the channel l between the source and drain regions [(53) and 5s via the gate oxide WA6, and is shared with the other transistor On4. It is composed of a goo 1 to an electrode 73 made of type polycrystalline silicon. The other transistor Qn4 has a common n transistor with the drain region 54 which is electrically isolated from each other in the island-shaped well 1 region.
The first layer The gate electrode 73 is made of n-type polycrystalline silicon.The gate electrode 73 functions as a word line WL.

Moreover, on the substrate 2 including the gate electrodes 71 to 73,
A first CVD-3i02 film 8I as a first layer interlayer insulating film is coated.
Disposed above are Vss power wiring lines 9t and 92 made of a second layer of n-type polycrystalline silicon doped with an impurity (phosphorus) of the same conductivity type as the first layer of n-type polycrystalline silicon. These Vssiilli wiring 9+, 921tlF
It is connected to the source regions 42, 43 of the transistors Qn1, Qn2 through holes 101, 102 opened in the CVD-3i 02 film 81.

Note that since the Vse power supply wirings 9+ and 92 also serve as wiring for adjacent memory cells, one is arranged for each memory cell. Then, on the first (7) CVD-8iO2 film 81 containing the Vss power supply wiring 91.92'e: a second CVD film as a second layer interlayer insulating film.
-8i02 film 82 is coated, the second part (7)
CVD-3i 0211Q82 has a pair of crossing β
Wiring lines 111 and 112 are arranged to cross the island-shaped substrate 2 region and the island-shaped well 1 region, respectively. One cross AR wiring 111 has contact holes 103, 10+, 10, which are opened across the first and second CVD-3i02 films 8+, 82, as shown in FIGS. 3 and 4.
The drain region ff of the transistor QD+ via ir
15t is connected to the extension portion 7a of the gate electrode 72 extending over the field oxide film 3 and the drain region 53 of the i-transistor Qnt, respectively. Other crossing A wiring 1121J first and second CVD-8i 021
*8+, contact hole 1 opened at 82
0s, the transistor QD via 107.10a
2, an extension 7b of the gate electrode 71 extending over the field oxide m3, and the drain region [54 of the transistor Qn2].

By providing β wirings 111 and 112 for such intersection, the gate electrode 72 of the transistor Ql)2.0n2 constituting the other CMOS inverter can be connected to the gate electrode 72 of the transistor QDt constituting the one CMOS inverter,
The crossing A℃ wiring 1 is connected to the drain region 5 and 5 of Qn+.
11 and contact holes 103 to 10s, and constitute one CMOS inverter. The gate electrode 71 of Qnt is connected to the i-transistor Qp2, which constitutes the other CMOS inverter.
The crossing A2 wiring 1 is connected to the drain region 52 and 54 of Qn2.
12 and contact holes 106 to 10g, thereby realizing a flip-flop circuit in which the CMOS inverters are cross-connected to each other.

Further, on the second CvD-3i021182, A°C wiring 121.122 (BL
I, B10) are arranged, and β wiring 1 is connected to these.
2+, 12+1, said first and second CVD-3i 02
The contacts 1118+ and 82 are connected to the drain regions 5S and 56 of the transistors Qr13 and Qr14 as the transfer gates through balls 10g and 10m, respectively. Note that 13 in the figure indicates the crossing Aλ wiring 11s, 112 and A9. Second CVD-3i 02 l including wiring 121.122
This is a protective film coated on ll82.

By the way, as is well known, 0MO8 is accompanied by a latch-up phenomenon. This will be explained with reference to a schematic diagram showing the latch-up phenomenon of CMO3IJ\i, that is, a thyristor effect, shown in FIG. 5, and its equivalent circuit diagram shown in FIG. 6.

Reference numeral 21 in FIG. 5 is an n-type silicon substrate, and a p-well 22 is selectively provided on the surface of this substrate 21. A field oxide film 23 for isolating device regions is formed on the surface of the substrate 21 including the well 22. the substrate 21 separated by the field oxide film 23;
The region includes p+ type sources electrically isolated from each other,
Drain region 241.2! llz is provided. In a region of the substrate 21 adjacent to this source region 241, an n+ type diffusion region 261 for biasing the substrate 21 is formed. The source and drain regions 241.25+
A gate oxide I is formed on the substrate 21 including the channel region between
! Gate electrode 28 made of polycrystalline silicon via 27
1 is provided. Further, the field oxide film 23
In the island-shaped p-well 22 region separated by p-type source and drain regions 242 . which are electrically isolated from each other.
252 are provided. A p1 type diffusion region t1262 for biasing the well 22 is provided in a region of the well 22 adjacent to the source region 242. Gate oxide l! is formed on the well 22 including the channel region between the source and drain regions 242 and 252. A gate electrode 1282 made of polycrystalline silicon is provided via the gate electrode 127 . Further, the entire surface of the substrate 21 including the gate electrodes 28+ and 282 is covered with an interlayer insulating film 29. On this inter-office insulation 1129, the p+ type source region 2
41 and the n+ type diffusion region b 126s through contact holes, the drain A2 wiring 31 connected to the drain region 251 through contact 1 to the hole, and the gate electrode 28s. Gate AI wiring 32 connected via contact hole
are rated E11 respectively.

Further, on the interlayer insulating I film 29, there is a source AN wiring 33 connected to both the N1 type source region 242 and the P1 type diffusion region 262 via contact holes, and a contact L-hole to the drain 1m252. The drain A2 wiring 34 and the gate electrode 282 connected via
A gate AP arrangement 1135 connected to each other through a contact hole is provided. Note that the gate AQ
ISi! The lines 32 and 35 are on the Vin side, the drain A2 wirings 31 and 34 are on the VOUTt, the source A2 wiring 30 of the p-channel MOS transistor is on the Vp side, and the source Af of the n-channel MO3l-transistor is on the Vp side.
The fi wires 33 are connected to V, respectively. These C
In the MOS m structure, the n + type source region 241 of the n-channel MO8 t-transistor, the parasitic non-transistor Qn whose emitter, base, and collector are the p- well 22 and the n-type silicon substrate 21, respectively, and the p1 of the p-channel MO8 I- transistor type source region [242, n-type silicon substrate 21, and p-well 22 as emitter, base, and collector, respectively;
p is formed, and a latch-up phenomenon occurs as shown below during operation of 0MO3.

Due to the high integration of CMOS inverters, the source and drain of each MOS transistor fr4bA 241.242.
When 25+ and 252 are miniaturized, for example, when an n-channel MO3t- transistor is turned on, holes are generated near the drain region 252 by impact ionization, raising the potential of the p-well 22. When the potential of the p-well 22 rises, the parasitic npnt-transistor Qn based on the well 22 causes a bipolar action, and the collector current IR8 of the transistor Qn flows through the n-type substrate 21. This is because this collector current IR8 flows through the resistor Rs of the n-type silicon substrate 21 on the VDD side.

The base potential of the transistor Qp is lowered to cause the transistor Qp to have a bipolar action. As a result, the same transistor Qp
The collector current I Rw b< starts to flow. And this collector current I Rw i! D-well 22
The above-mentioned parasitic npb
This increases the base potential of the transistor Qn, and even after the impact ionization no longer occurs, the base potential of the transistor Qn increases.
Make n take bipolar action. This transistor Q
Due to the bipolar action of n, its collector current l
Rw further lowers the base potential of the parasitic pnpt-transistor Ql, and increases the collector current IR of the transistor Qp.
w to flow easily, thereby further increasing the base potential of the parasitic npn transistor Qn, and causing the transistor Qn to
Due to positive feedback that further increases the collector current of V
A large current will flow from DD to Vss. Not only does the 0MO3 become inoperable due to such a large current, but the integrated circuit (static memory) having the 0MO3 is thermally destroyed by the large current.

An effective means to improve latch-up fog resistance is to reduce Rs (resistance of the n-type silicon substrate 21) and RW (resistance of the p-well 22) shown in FIGS. 5 and 6. It is. Specifically, by providing a p+ type diffusion region for biasing the well formed in the p-well for each CMOS inverter, and connecting wiring for biasing each diffusion region, the well is All you have to do is lower the resistance.

Therefore, the memory cells of the static memory shown in FIGS. 2 to 4 described above are constructed by forming two pairs of CMOS inverters on a second CVD-3iO2O2 film for the purpose of cross-connecting a pair of CMOS inverters to form a flip-flop circuit. Since the crossing Afi wirings 11+ and 112 are provided, the second
Determining the pitch width of memory cells on the CVD-8i02 82 A wiring density decreases. For this reason, the first C
V, power supply wiring 91.9 on the VD-8i02 film 81
2 is formed of a second layer of n-type polycrystalline silicon, and the second layer (
7) CVD-8+ 02 film 82 Upper Te (7) A/l wiring diffusion region of the same type 4 as the n-type impurity in the polycrystalline silicon, that is, n-channel M as shown in FIGS.
Ohmic contact is made with the n+ type source regions 42 and 43 of the OS transistor Qr+s and the transistor Qn2 of the same channel by connecting the p1 type diffusion region for biasing the well 1 together with the source region in common. In order to lower the resistance of the tube 1 and improve the latch-up resistance, a pn junction is formed at the contact portion between the VSS power supply wiring made of n-type polycrystalline silicon and the ρ" type diffusion region. It becomes difficult to make good ohmic contact.As a result, in the static memory shown in FIGS. For example, in a conventional static memory, four A multi-wires (two for cross-connection, two for bit lines) are provided for each memory cell in the second (7) CVD. -8i 02 g, the pitch width of the memory cell increases, and since the area for forming the well bias A2 wiring is provided in a region different from the memory cell region, the memory itself The area increases and the total memory density decreases.Furthermore,
Since it is not possible to form A° C. wiring for well bias every 8 memory cells, the latch-up resistance cannot be sufficiently improved.

For this reason, as shown in Figures 7 to 9, the second
Static memory cells have been attempted in which a pair of CMOS inverters are cross-connected to each other in layered polycrystalline silicon. That is, this method t'J t /l, j is formed on the first (7) CVD-3i 0211!81 by a pair of crossing wirings 141 and 142 made of second layer polycrystalline silicon.
are arranged so as to cross the front two island-shaped substrate 2 regions and the island-shaped well 1 region, respectively. One crossing wiring 141
As shown in FIGS. 8 and 9, the first CVD-8i
The p4 type drain region 5I of the transistor Ql)1 is connected to the p4 type drain region 5I of the transistor Ql)1 through the contact hole 151 opened in the
Field oxidation of the gate electrode 72 made of the first layer n-type polycrystalline silicon is performed through the interconnection part 16a of n-type polycrystalline silicon connected to 113 and the n+ of the l-transistor Qnl.
It is composed of an n-type polycrystalline silicon wiring portion 17a connected to the type drain region 53. The other crossing wiring 142 is connected to the n-type polycrystalline silicon wiring portion 16b connected to the p+ type drain region 52 of the transistor Qpz via the contact hole 154 opened in the first CVD-3i 02118+, and the same CVD-3i 02118+. The extending portion 7b of the gate electrode 71 made of the first layer n-type polycrystalline silicon extends onto the field oxide film 3 through the contact holes 155 and 156 opened in the 8i02 film 81 and the n+ type of the transistor Qn2. The drain region 54 is connected to an n-type polycrystalline silicon wiring portion 17b. Furthermore, the crossing wiring 14! , 142
On the first CVD-8i02 film 81 containing
VD-3i 0211#82 is coated. On this second CVD-8i02 film 82, the crossing wiring 14 is
p-type and n-type polycrystalline silicon wiring portions 16 constituting the
a, p constituting the crossing wiring 142 as well as between 17a and 17a.
A pair of Afi layers 181 and 182 are provided to remove the adverse electrical effects of the ρn junctions formed between the wiring portions 16b and 17b of polycrystalline silicon of type and n type, respectively. In other words, one of the two layers 181 has an elongated opening in the second CVD-3i○2 film 82 including the pn junction between the p-type and n-type polycrystalline silicon wiring parts 16a and 17a. Contact 1~through the hole 191 for the crossing edl! Connected to 14+. The other AR layer 18
2 is the p-type, n%4 polycrystalline silicon wiring section 16.
b, said second CVD- including the pn junction part between 17b
It is connected to the crossing wiring 142 through an elongated contact hole 192 opened in 3i 02 ll82.

However, in the static memory with the structure shown in FIGS. 7 to 9, the density of occlusion wiring within the cell is lower than that of the static memory shown in FIGS. 2 to 4, but the bit line two Aβ wirings 121 and 122, and a crossing wiring 14+ made of second layer polycrystalline silicon.
, 142 4-mink connection A1ii18+,
There is no change in the fact that a total of 4 pieces, 2 pieces of 182, are required.
Therefore, the pitch width of the memory cell determined by 8β cannot be reduced. Therefore, even in such an ill-built Stictic memory, the cell size cannot be made smaller than that of a conventional static memory, and furthermore, since the second layer n-type polycrystalline silicon is used as the Vss power wiring, the well bias The reduction in the degree of integration of the memory itself and the sufficient improvement in latch-up resistance due to the provision of an area separate from the cell area for forming the second wiring for use are not improved.

[Purpose of the invention]

The present invention aims to provide a semiconductor memory device in which the pitch width of memory cells and the memory itself can be miniaturized, and the latch-up resistance is significantly improved.

[Summary of the invention]

The present invention has a pair of CMOS inverters, one C
a flip-flop circuit formed by cross-connecting the gate electrode of a MOS inverter to the drain region of each transistor of the other CMOS inverter via wiring;
In a semiconductor memory device in which a pair of transfer MOS transistors connected to each node of the flip-flop circuit are integrated in a matrix on a semiconductor substrate, the Goo 1-electrode is connected to the first electrode. A first layer of polycrystalline silicon containing conductivity type impurities is formed, and the wiring is provided on a first layer interlayer insulating film covering the gate electrode, and is connected to a first S conductivity type drain region and the gate electrode. a second layer polycrystalline silicon interconnection section containing impurities of a first conductivity type connected via a contact hole;
It is characterized by comprising a second-layer polycrystalline silicon wiring section containing impurities of a second conductivity type, which is connected to the drain region of the mold via a contact hole, and a metal layer pasted on each of the wiring sections. It is something to do.

In a semiconductor memory device having such a structure, one '1IIli! i, and the metal wiring is connected to both the source region of one CMOS inverter and a diffusion region of the opposite conductivity type to the source region for biasing the substrate region where this source region is formed. It becomes possible to connect to the memory cell through a contact hole, and as mentioned above, it is possible to reduce the pitch width of the memory cell and achieve high integration of the memory itself.
Latch-up resistance m can be significantly improved.

[Embodiments of the invention]

Hereinafter, an example in which the present invention is applied to a CMOS static memory will be described in detail in No. 1 with reference to FIGS. 10 to 12.

In the figure, 0) QD], QnJLL, while (7) 0MO8-1
'>ρ channel MO8l-transistor forming bark, n-channel MO3l-transistor, QD2 in the figure
, QD2 is the other (7) p-channel MO8t-transistor forming a CMOS inverter, n-channel MO
8T-transistors, these CMOS inverters form a flip-flop circuit by cross-connecting the gate of one to the common drain portion of the other. Also, QD3 in the figure. QD4 is an n-channel M serving as a transfer gate connected to the drain side of each n-channel MO8l- transistor Qn+ and QD2.
It is an OS transistor.

Said n-channel MOS l- transistor Ql)+
, QD2 is an island-shaped region of the n-type silicon substrate 52 separated by field oxidation l1153 of the n-type silicon substrate 52 on which the p-well 51 is selectively formed, as shown in FIGS. 11 and 12. is being formed on a large scale. One transistor QD+ includes a p+ type source 541 and drain region 551 formed electrically isolated from each other in the island-shaped substrate 52 region, and these source and drain regions 54+.
, 55+, with a gate oxide film 56 interposed therebetween, and the n-channel MOS
It is composed of a gate electrode 571 made of, for example, a first layer of n-type polycrystalline silicon doped with phosphorus, which is shared with the gate of the transistor Qnt.

The other transistor QO2 includes the p1 type source 541 and drain regions 552 formed electrically isolated from each other in the island-shaped substrate 52 region, and a channel region between these source and drain regions 541 and 552. disposed on the substrate 52 with a gate oxide film 56 interposed therebetween
For example, a first layer made of n-type polycrystalline silicon doped with phosphorus is shared with the gate of the channel MO3 transistor Qn2. It is composed of an l pole 572.

Note that the p++ source region 54+ is shared by both the transistors Qp1 and QD2, and functions as a VDD line. Further, the transistors Qn+, Qn2
are formed in island-shaped p-well 51 regions separated by field oxide film 53. One transistor Qn1 includes an n+ type source region 542 formed electrically isolated from each other in the island-shaped p-well 51wA region;
Drain region 553 and these source and drain regions 5
42.553 on the well 51 including the channel region between
The gate electrode 571 is composed of a layer of n-type polycrystalline silicon. The other transistor Qn2 has an n+ type source region 543 and a drain region 554 that are electrically isolated from each other and are formed in the island-shaped p-well 51 region.
and a gate electrode 572 made of the first layer n-type polycrystalline silicon, which is disposed on the well 51 including the channel region between these source and drain regions 543 and 554 with a gate oxide film (not shown) interposed therebetween. It is configured. One transistor Qn as the gate of the transformer 71
3, 01 type source and drain regions 555 common to the drain i region 553 electrically isolated from each other in the island-shaped well 51 region, and these source and drain regions (553 A gate I- electrode made of a first layer of n-type polycrystalline silicon doped with phosphorus and is placed in the well 51 region including the channel region between 55a and 55a via the gate oxide 1I56, and is shared with the other transistor Qn+. 573. The other transistor Qrz includes an n+ type source region and a drain region 556 that are common to the drain region R554 and are electrically isolated from each other in the island-shaped well 51 region; It is arranged in the well 51 region including the channel region between the drain region (554> and 55a) with a gate oxide film interposed therebetween, and is composed of a goo electrode 573 made of the first layer n-type polycrystalline silicon. The gate pole 573 functions as a word line W. The p- well 51 adjacent to the n+ type source region 542, 543 has a p++ diffusion region 581 for well bias.
．． 582 are provided respectively.

Moreover, on the substrate 52 including the gate electrodes 571 to 573, the 11th! First CVD as interlayer insulating film of i
8'+02 membrane 591 is coated.

(7) CVD S l 0211591 A pair of crossing wiring lines t and t are arranged so as to cross the island-shaped substrate 52 area and the island-shaped well 51 area, respectively. ing. One crossing wiring 60+ is connected to the first crossing wiring 60+.
As shown in FIGS. 0 to 12, the p-type drain region 551 of the transistor Ql)t is connected through a contact hole 611 opened in the first CvD-3iO2 film 591.
The connected n-type polycrystalline silicon wiring part 62a and the CV
D-5+021159s through the contact holes 612. I! Field oxide film 53 of gate electrode 572 made of n-type polycrystalline silicon
The extending portion 57a extending upward and the transistor Qr+
n-type polycrystalline silicon wiring portions 63a connected to the n1-type drain regions 553 of s, and these wiring portions 62a, 6
3a, and a tungsten layer 64a placed on top of the tungsten layer 64a. On the other hand (7) the crossing wiring 602 is the first
(7) Through the contact hole 614 opened in CVD-8i 021I591, the transistor Ql)
The n-type polycrystalline silicon wiring portion 62b connected to the two p+-type drain regions 552,! :, nocVD-8i 02
l159i 11M1 Contact hole 61
s, 616, are connected to an extension 57b extending over the field oxide 1153 of the gate oxide film 571 made of the first layer n-type polycrystalline silicon and to the n4' type drain region 554 of the transistor Qn2, respectively. N-type polycrystalline silicon interconnection section 63b and these interconnection sections 62b, 63
A tungsten layer 64b is provided on top of the tungsten layer 64b. Such crossing wiring 60s, 602
By providing the gate electrode 572 of the transistor Ql)2, On2 constituting the other CMOS inverter, the gate electrode 572 of the transistor Ql)2, On2 constituting the other CMOS inverter is connected to the drain region 5Fz, 55 of the transistor Qpl, QrH constituting the one CMOS inverter.
3, the crossing wiring I-cutting and contact hole 611.
612.613 and one CM
Transistors Ql)+, Q that constitute the OS inverter
The gate electrode 571 of the nl is cross-connected to the drain regions 552 and 554 of the transistors Qp2 and On2 constituting the other CMOS inverter through the contact holes 614 and 61s of the crossing wiring 602, whereby each of the CMOS inverters is connected to each other. A cross-connected flip-flop circuit is realized.

Further, the first CVD-3i02 film 591 including the crossing wiring 601 and the moxibustion layer is covered with a second CVD-8102 film 592 as a second interlayer insulating film. This second CVD-8i02111592 upper niha v8
11+ power supply Aj2 wiring 65s and 652 are arranged. Each Aβ wiring 65+, 652La said first and second (
7) Through the contact hole 617.61a opened across CVD-3i0211591.592,
Helangister Qn+, Qn2 n1 type source area M54
2.543 and p++ diffusion regions 581.582, respectively. Note that the A wiring 65+, 6
52 also serves as wiring for adjacent memory cells, so one is arranged for each memory cell. Further, on the second CVD-CVD-8i02, there are △-shaped wirings 66+, 662 (BL+,
B10) are arranged, and these A2 wiring 66+
, 66+ is the first and second CVD-3i02 training 591
．． A contact hole 619 opened at 592.
Transistor Qn3.61m as the transfer gate. Drain regions 55s and 55a of Qn4
are connected to each other. In addition, 67 out of 8 is covered with a protective coating on the entire surface! ! It is a membrane.

According to the present invention, as one of the crossing wirings for cross-connecting a pair of CMOS inverters to each other, the first CVD-3i is connected as shown in FIGS. 10 to 12.
The p+ type drain region 5 of the transistor QD+ is connected to the transistor QD+ through the contact hole 611 opened in the
an n-type polycrystalline silicon wiring section 62a connected to 5+;
Same CVD-8102M! The field mosquito film 5 of the gate electrode 572 made of the first layer n-type polycrystalline silicon is connected through contact holes 612 and 613 opened at 59t.
3 and the transistor Qn.
The n-type polycrystalline silicon wiring portions 63a connected to the n+ type drain regions 553, and these wiring portions 62a, 6
3a and a tungsten layer 64a disposed on top of the tungsten layer 64a. The other crossing wiring 602 is connected to the p+ type drain region 552 of the transistor Qp2 through a contact hole 614 opened in the first CVD-8i 0211591.
type polycrystalline silicon wiring part 62b and the same CVO-3i 0
Contact holes 61s and 6 opened in 2159t
The extending portion 57b extends over the field oxide 1153 of the gate electrode 57+ made of the first layer n-type polycrystalline silicon through the The crystalline silicon wiring portion 63b is composed of a tungsten layer 64b provided over these wirings P[162b, 63b. As a result, the history of cross-wiring moxibustion began.

602 and the p+ type and n" drain regions 551, 552, 553, and 55, which have different conductivity types. Good contact can be made without forming a pn junction between the drain regions 551, 552, 553, 55, and the n-type polycrystal. Since tungsten layers 64a and 64b are pasted on both the silicon wiring parts 62a and 62b and the n-type polycrystalline silicon wiring parts 63a and 63b, respectively, tungsten layers 64a and 64b are formed between the wiring parts of different conductivity types. This (1
) tc, 1st (7) CVD-3i 02 discipline 591
CMO with only crossing wiring 601 and 602 placed above
Since the S inverters can be cross-connected to each other, a pair of CMOs can be connected on the second interlayer dielectric (second CVD-3i 02 II) as in the conventional memory cells shown in FIGS.
There is no need to provide an Aρ wiring for cross-connecting the S inverters, and the margin of the A2 wiring on the memory cell, which determines the pitch width of the memory cell, increases. As a result, the 217th) CVD-3i 02 discipline 592JJ:V, along with the AI wiring 66+ and 662 as bit lines.
Aff wiring 651 and 652 for power supply can be arranged. In this way, the configuration for Vssli source! ! 65+, 652 can be formed with AI, as shown in FIG.
Good connection can be made between both p+ type diffusion regions 581 and 582 for well bias via contact holes 617 and 618. In other words, Aβ wiring 6 for Vssii source
Since the wires 5t and 652 can also be used as I-well bias wiring, a well bias can be applied to each memory cell. Therefore, the bias point to the p-well 51 can be increased and the resistance of the well 51 can be effectively reduced, thereby significantly improving latch-up resistance.

In addition, unlike the conventional structure shown in Figures 2 to 4, there is no need to place the Aj2 wiring for well bias in a separate area from the memory cells, for example, for 8 cells, so the area of the memory itself can be reduced. can.

Further, on the second CVD-8i02 film 592, Vss
Electric I Al1E wire 65+ (also t, t652) (7) 1
There are three wires in total, including the main wire and two AR wires 661 and 662 as bit lines, and since the number of β wires can be reduced by one compared to the conventional memory cell, the pitch width of the memory cell can be reduced. In fact, if the design rule is a 1.5 μm process, the pitch width of the memory cell shown in FIG. 2 is 17. C
1 m, whereas in the memory cell shown in FIG. 10 of the present invention, it can be significantly reduced to 15.5 μm.

In the above embodiment, tungsten was used as the metal layer to be attached to both the n-type polycrystalline silicon wiring part and the n-type polycrystalline silicon wiring part, but instead of tungsten, molybdenum, tantalum, platinum, etc. Selected high melting point metals may also be used.

[Effect of Light] As detailed above, according to the present invention, the pitch width of memory cells and the memory itself can be miniaturized, and it is also possible to create highly integrated and highly reliable static memories with significantly improved latch-up resistance. A semiconductor memory device can be provided.

[Brief explanation of drawings]

Fig. 1 is an equivalent circuit diagram of a 6-transistor static memory having a pair of CMOS inverters, Fig. 2 is a plan view showing a memory cell of a conventional static memory, and Fig. 3 is taken along the line X-X in Fig. 2. 4 is a sectional view taken along the Y-Y line in FIG. 2, FIG.
7 is a plan view showing a memory cell of another conventional static memory, FIG. 8 is a sectional view taken along the line X-X in FIG. 7, and FIG. Y in the diagram
10 is a plan view of a memory cell of a static memory showing one embodiment of the present invention, FIG. 11 is a sectional view taken along x-xIia in FIG. 10, and FIG. 10 is a sectional view taken along Y-Yl in FIG. 10. FIG. QD+, QD2...p channel Mo5t~ransistor, Qn+, Qn2. Qn3. Qn+-n channel MOS l-transistor, 51...p-well,
52... nIl silicon substrate, 53... field oxide film, 54+, 542.543... source region. 55+, 552.553.554.55s, 556
...Drain region, 57+, 572.573...
First rib made of n-type polycrystalline silicon electrode, 58
1.582... p1 type diffusion region for well bias,
59 knee 1st (7) CVD-8i 02 II (first interlayer insulating film), 592... second CVD-8i0
21! (Second 11 insulation l1l), 60+, 60
2...Cross wiring, 611-61 association...] Nushita 1
Heholes, 62a, 62b...N-type polycrystalline silicon wiring part, 63a, 63b...N-type polycrystalline silicon wiring part, 64a, 64b-...Tungsten layer, 651.6
52-Vss power supply/l wiring, 66+, 662 =-
A2 wiring as a pill line.

Claims (3)

[Claims] (1) Has a pair of CMOS inverters, one CMOS
A flip-flop circuit formed by cross-connecting the gate electrode of the S inverter to the drain region of each transistor of the other CMOS inverter via wiring, and a pair of transfer MO8l- connected to each node of this flip-flop circuit. In a semiconductor memory device in which memory cells constituted by transistors are integrated in a matrix on a semiconductor substrate, the gate electrode is formed of a first layer of polycrystalline silicon containing impurities of a first conductivity type, and The wiring is provided on the first interlayer insulating film covering the gate electrode, and is connected to the drain region of the first conductivity type and the gate electrode through a contact hole, and includes a first conductivity type impurity. a crystalline silicon interconnection section, and a second interconnection section provided on the interlayer insulating film so as to be connected to the interconnection section, and connected to the drain region of the second conductivity type via a contact hole.
a second layer polycrystalline silicon wiring portion containing conductivity type impurities;
A semiconductor memory device comprising: a metal layer pasted on each of the wiring portions. (2) The metal layer is tungsten, molybdenum, tantalum,
The semiconductor memory device Vi according to claim 1, characterized in that it is made of a high melting point metal selected from platinum. (3) A metal wiring serving as one power source is provided on the second layer interlayer insulating film covering the wiring, and the metal wiring is connected to one CMO.
The source region of the S inverter and the diffusion region of the opposite conductivity type to the source region for biasing the substrate region in which the source region is formed are connected via contact holes. A semiconductor memory device according to scope 1.