JPS6022828A - Fm signal generator - Google Patents
Fm signal generatorInfo
- Publication number
- JPS6022828A JPS6022828A JP58130193A JP13019383A JPS6022828A JP S6022828 A JPS6022828 A JP S6022828A JP 58130193 A JP58130193 A JP 58130193A JP 13019383 A JP13019383 A JP 13019383A JP S6022828 A JPS6022828 A JP S6022828A
- Authority
- JP
- Japan
- Prior art keywords
- controlled oscillator
- voltage controlled
- frequency
- signal
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 3
- 238000001514 detection method Methods 0.000 claims 2
- 238000001914 filtration Methods 0.000 claims 1
- 230000010355 oscillation Effects 0.000 description 14
- 238000010586 diagram Methods 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 241000270666 Testudines Species 0.000 description 1
- 241000307523 Xenostegia media Species 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 230000001012 protector Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03C—MODULATION
- H03C3/00—Angle modulation
- H03C3/02—Details
- H03C3/09—Modifications of modulator for regulating the mean frequency
- H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
- H03C3/0966—Modifications of modulator for regulating the mean frequency using a phase locked loop modulating the reference clock
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03C—MODULATION
- H03C3/00—Angle modulation
- H03C3/02—Details
- H03C3/09—Modifications of modulator for regulating the mean frequency
- H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
- H03C3/095—Modifications of modulator for regulating the mean frequency using a phase locked loop applying frequency modulation to the loop in front of the voltage controlled oscillator
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
- H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は１周波数変調（ＦＭ変調）された任意の周波
数の信号を出力することができるＦＭ信信号発生上係わ
り、特に、そのＦＭ基準信号源を形成するＦＭ信号発生
ＰＬＬ回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to FM signal generation capable of outputting a single frequency modulated (FM modulated) signal of any frequency, and particularly relates to FM signal generation that forms an FM reference signal source. This relates to a PLL circuit.
電子機器における調整用の標準信号発生器等においては
、周波数変調された信号源が要求され、かつ、その中心
周波数が変化できるようなＦＭ信号発生器が必要となる
。A standard signal generator for adjustment in electronic equipment requires a frequency-modulated signal source, and also requires an FM signal generator whose center frequency can be varied.
第】図はか〜るＦＭ信号発生器の回路例を示Ｌ−たもの
で、１０はＦＭ変調信号ｅｍで周波数変調されるＦＭ基
準信号源、２０は位相検出器、３０はＦＭ変調信号ｅＩ
１．ｌの周波数より高い周波数をカットするローパスフ
ィルタ、４０は電圧制御発振器（ＶＣＯ）、５０は分周
回路でその分周比Ｎは可変できるものである。The figure shows an example of the circuit of such an FM signal generator, in which 10 is an FM reference signal source that is frequency-modulated with an FM modulation signal em, 20 is a phase detector, and 30 is an FM modulation signal eI.
1. 40 is a voltage controlled oscillator (VCO); 50 is a frequency divider circuit whose frequency division ratio N is variable;
このようなブロック回路は良く知られているように、Ｆ
Ｍ基基準信号源１０岡
御発振を４０のｘＡ撮周波数ｆ．をＮ分周した周波（
Ｐｈａｓｅ Ｌｏｃｋ Ｌｏｏｐ ）回路を構成するも
のである。As is well known, such a block circuit is F
M-base reference signal source 10 Oka oscillation is carried out at 40xA imaging frequency f. The frequency obtained by dividing by N (
This constitutes a Phase Lock Loop (Phase Lock Loop) circuit.
したがって、今、ＦＭ変調信号ｅ０が０であれば，を圧
制御発振器４０の発振周波数ｆ．はＦＭ基準（１号源１
０の中心周波数ｆ０に対しｆ，＝Ｎ−ｆ。Therefore, if the FM modulation signal e0 is now 0, the oscillation frequency f of the pressure-controlled oscillator 40 is set to f. is FM standard (No. 1 source 1
f,=N−f for the center frequency f0 of 0.
となり１分周比Ｎｖ変化させることによって任意の周波
数ケ出力することができる。By changing the frequency division ratio Nv by 1, an arbitrary frequency can be output.
又、ＦＭ変調信号ｅゆを加えＦＭ基基準信号源１０同
偏移に対応して電圧制御発振器４０の発振周波数ｆ．も
変化し、ｆ，＝Ｎ−ｆ，のＦＭ信号が出力される。Further, the FM modulation signal e is added to adjust the oscillation frequency f of the voltage controlled oscillator 40 in response to the deviation of the FM base reference signal source 10. also changes, and an FM signal of f,=N-f, is output.
ところで、上述したようなＦＭＭ準信号源１０としては
周波数安定度の高いものが好ま（７いが、周波数安定度
の高い、例えは水晶発振器等を採用すると、大きな周波
数偏移を得ることができないという問題があり、逆に比
較的周波数変調がか（り易いＬＣ回路からなるＬＣ’Ｊ
振器な採用すると、周波数偏移が小さい場合に、ＬＣ発
振器の中心周波数変動がＦＭ変調信号ｅｌＩ＋を加えた
時の周波数偏移に比べ℃無視しえない値となり、電圧制
御４１発振器４０から出力される信号の中心周波数精度
が著るしく悪化するという問題がある。By the way, as the FMM quasi-signal source 10 as described above, it is preferable to use one with high frequency stability (7), but if a highly stable one, such as a crystal oscillator, is used, it is not possible to obtain a large frequency shift. On the other hand, the LC'J, which consists of an LC circuit that is relatively susceptible to frequency
If an oscillator is adopted, when the frequency deviation is small, the center frequency fluctuation of the LC oscillator becomes a value that cannot be ignored compared to the frequency deviation when the FM modulation signal elI+ is applied, and the output from the voltage control 41 oscillator 40 increases. There is a problem in that the center frequency accuracy of the signal generated is significantly deteriorated.
この発明は、か〜る実状にかんがみてなされたもので、
周波数安定度の高い第１の信号源と、周波数変調が深く
か−る第２の信号源を備え、これらの信号源’４１つの
ＰＬＬ＠略内に配置することによって周波数偏移な広い
範囲で可変すると共に。This invention was made in view of the actual situation,
It is equipped with a first signal source with high frequency stability and a second signal source with deep frequency modulation, and by placing these signal sources within one PLL, it is possible to achieve a wide range of frequency deviation. Along with being variable.
信号源の周波数変動も実用上問題とならないようにした
ＦＭ信号発生器な提供するものである。The present invention provides an FM signal generator in which frequency fluctuations of a signal source do not pose a practical problem.
以下、この発明の概要を図面に基づいて説明する。Hereinafter, an outline of the present invention will be explained based on the drawings.
第２図はこの発明の一実施例火ブロック図と［。FIG. 2 is a block diagram of an embodiment of the present invention.
たもので、特に、図中のＦＭ基基準４婦徴ケ有している
。なお、第１図と同一記号は同一機能を示すブロック台
である。In particular, there are four female characteristics based on the FM standard shown in the figure. Note that the same symbols as in FIG. 1 are block stands indicating the same functions.
この発明のＦＭ信号発生器では、ＦＭＭ準信号源１０と
して、周波数安定度の商い第１の電圧制御発振器１６と
、大きい周波数偏移が得られる第２の電圧制御発振器１
７が備えてあり、これらがＦＭ変変調１縛
ットオフ周波数より十分高いときはＰＬＬ回路によって
参照信号ｅｒで位相回期されるように構成されている。In the FM signal generator of the present invention, as the FMM quasi-signal source 10, a first voltage-controlled oscillator 16 with a frequency stability ratio and a second voltage-controlled oscillator 1 with a large frequency deviation are used.
7, and when these are sufficiently higher than the FM modulation 1 cut-off frequency, the phase is rotated by the reference signal er by the PLL circuit.
すなわち、１１は参照信号・ｅｌと前記第１．第２の電
圧制御発振器１６．又は１７のいずれかの発振周波数と
の位相差！検出する位相検出器，１２はフィルタ、１３
は直流増幅器．又は減衰器等からなる利得制御回路、１
４はＦＭ変調信号ｅｍと周波数制御信号の加算回路、１
５はＦＭ変調信号源である。That is, 11 is the reference signal el and the first . Second voltage controlled oscillator 16. Or the phase difference with any of the 17 oscillation frequencies! Detecting phase detector, 12 is a filter, 13
is a DC amplifier. or a gain control circuit consisting of an attenuator etc., 1
4 is an addition circuit for the FM modulation signal em and the frequency control signal; 1
5 is an FM modulation signal source.
なお、１８は分周回路であり、ＰＬＬ回路が動作してい
るときは参照信号ｅｒ の周波数と、前記第１．又は第
２の電圧制御発振器１６．１７の発振周波数（中心周波
数）を１にした信号と一致させるものである。Note that 18 is a frequency dividing circuit, and when the PLL circuit is operating, the frequency of the reference signal er and the first . Alternatively, the oscillation frequency (center frequency) of the second voltage controlled oscillator 16, 17 is made to match the signal set to 1.
又、ＳＩは前記第１．第２の電圧制御発振器１６、又は
１７のいずれかを選択するスイッチで、このスイッチＳ
１の切り替えと同時にＰＩ，Ｌ回路のループゲイン？：
ｇ整している利得制御回路１３の利得を変更するもので
ある。Moreover, SI is the above-mentioned No. 1. This switch S is a switch for selecting either the second voltage controlled oscillator 16 or 17.
Loop gain of PI and L circuits at the same time as switching 1? :
This is to change the gain of the gain control circuit 13, which has been adjusted.
この発明のＦＭ信号発生器は上記したような構成とされ
ているので、ＦＭ基準信号源１ｏからは周波数安定度ひ
高い第】の電圧制御発振器１６又は周波数偏移を大きく
できる第２の電圧制御発振器１７からの信号がスイッチ
Ｓ、の切り替えによって出力される。Since the FM signal generator of the present invention has the above-described configuration, the FM reference signal source 1o is connected to the voltage controlled oscillator 16 with high frequency stability or the second voltage controlled oscillator 16 which can increase the frequency deviation. A signal from the oscillator 17 is output by switching the switch S.
そして、前記第１．第２の電圧制御発振器１６゜１７は
ＰＬＬ回路により参照信号ｅ、と位相同期される。And the above-mentioned 1. The second voltage controlled oscillator 16, 17 is phase synchronized with the reference signal e by a PLL circuit.
今、ＦＭ変調信号ｅＩＴｌが印加され、第１．第２の電
圧制御発振器１６．１１にＦＭががげられると、参照信
号ｅｒ は無変調とされているので、位相検出器１１の
出力には前記ＦＭ変調信号ｅｌ、ｌが出力される。Now, the FM modulation signal eITl is applied and the first . When the FM is applied to the second voltage controlled oscillator 16.11, the FM modulated signals el and 1 are output from the phase detector 11 since the reference signal er is not modulated.
フィルタ１２のカットオフ周波数はこのＦＭ変調信号輸
の周波数粍より充分低い値とされているので、フィルタ
１２はＦＭ変調信号成分を通過せず、直流成分に近い制
御信号のみを通過させる。Since the cutoff frequency of the filter 12 is set to a value sufficiently lower than the frequency of this FM modulation signal, the filter 12 does not pass the FM modulation signal component, but only passes the control signal close to the DC component.
そのため参照信号ｅ、の周波数と、第１又は第２の電圧
制御発振器１６．１７の中心周波数を−に■１
した信号が一致することになり、中心周波数は参照信号
ｅ、にフェーズロックされる。すなわち、第１．第２の
電圧制御発振器１ｆｉ、１７自体の周波数安定度が多少
悪くても問題が１工い。この発明では、この状態なＦＭ
−ＡＣモードと称している。。Therefore, the frequency of the reference signal e, and the signal obtained by changing the center frequency of the first or second voltage controlled oscillator 16.17 to -1 will match, and the center frequency will be phase-locked to the reference signal e. . That is, 1st. Even if the frequency stability of the second voltage controlled oscillator 1fi, 17 itself is somewhat poor, there is still a problem. In this invention, FM in this state
-It is called AC mode. .
ところで、第１の電圧制御発振器１６は周波数安定度の
高い水晶発振器等で構成されており、制御電圧の変化に
対する周波数偏移、つまり変換利得が小さく、第２の電
圧制御発振器ＩＴは大きい周波数偏移が得られるように
ＬＣｙＡ振器等によって構成されており、その変換利得
は太きい。したがって、第１の電圧制御発振器１６がス
イッチＳ。By the way, the first voltage controlled oscillator 16 is composed of a crystal oscillator or the like with high frequency stability, and has a small frequency deviation, that is, a conversion gain, with respect to changes in the control voltage, and the second voltage controlled oscillator IT has a large frequency deviation. The conversion gain is large, and the conversion gain is large. Therefore, the first voltage controlled oscillator 16 is connected to the switch S.
で選択されている時のループケインの方が、第２の電圧
制御発振器１Ｔが選択されている時のループでインより
／Ｊ’ｓさくなるので、この両者の場合でＰＬＬ回路の
応答特性が異なることになり好ましくない。そのため、
この発明ではスイッチＳ、の選択に応じて利得制御回路
１３の利得を変更し。The loop cane when selected is /J's smaller than the loop in when the second voltage controlled oscillator 1T is selected, so the response characteristics of the PLL circuit are It's different and I don't like it. Therefore,
In this invention, the gain of the gain control circuit 13 is changed according to the selection of the switch S.
いずれの電圧制御発振器（１６，１７）が選択されてい
る時も同一のループゲイン（応答特性）で働（ように制
御する。そのため利得制御回路１３と［、ては可変利得
形の増幅器、又は可変減衰器等が採用される。When either voltage controlled oscillator (16, 17) is selected, it is controlled so that it operates with the same loop gain (response characteristic). A variable attenuator etc. is adopted.
スイッチＳ、はＦＭ変調信号ｅｍの周波数がフィルタ１
２０力ツトオフ周波数以下にまで低下する場合に閉成と
するものである。すなわち、ＦＭ変調信号ｅｌＴｌの周
波数が低下（７、直流に近くなると、第］又は第２の電
圧制御発振器１６．１７のＦＭ変調された信号が位相検
出器１１で検出され。switch S, the frequency of the FM modulation signal em is filter 1
It is closed when the force drops below the 20-force cut-off frequency. That is, when the frequency of the FM modulated signal elTl decreases (7) and approaches DC, the FM modulated signal of the second voltage controlled oscillator 16, 17 is detected by the phase detector 11.
この検出されたＦＭ変調信号成分がフィルタ１２を通過
することになり、この検出されたＦＭ変調信号成分はＦ
Ｍ変調信号源１５０ＦＭ変調信号ｅＩ、。This detected FM modulation signal component passes through the filter 12, and this detected FM modulation signal component passes through the filter 12.
M modulation signal source 150 FM modulation signal eI,.
と逆極性となるので周波敬愛１ｉｌｌヲかけることが困
難になる。Since the polarity is reversed, it becomes difficult to apply the same frequency.
このような場合には、スイッチＳ、を閉ｇ［２て接地す
ることによってフィルタ１２からの制御信号ケＯレベル
に固定しＰＬＬ回路のロック状態夕解除する。この発明
ではフィルタ１２からの制御信号’ｔｔｏｖベルに固定
した状態’ｋＦＭ−ＤＣモードと称し工いる。この状態
では第１．又は第２の電圧制御発振器１６．１７’＝”
フリーランとして周波数変調がか（るようにする。In such a case, by closing the switch S and grounding it, the control signal from the filter 12 is fixed at the O level and the locked state of the PLL circuit is released. In this invention, the state in which the control signal from the filter 12 is fixed at ttov is called FM-DC mode. In this state, the first. or second voltage controlled oscillator 16.17'="
Allow frequency modulation to occur as a free run.
この場合、第１．又は第２の電圧制御発振器１６゜１７
の中心周波数は参照信号ｅ、の周波数に〕ニーズロック
されないので、その中心周波数の変動はそのま（出力さ
れる。このような場合においてＦＭ偏移が小さいときは
第２の電圧制＃３ｆ：保器１１を用いると中心周波数の
変動が問題となって（るので、周波数安定度の高い第１
の電圧制御発振器１６を使用し、周波数変調をか１する
ことＫなる。In this case, 1. Or second voltage controlled oscillator 16°17
Since the center frequency of the reference signal e is not locked to the frequency of the reference signal e, the fluctuation of the center frequency is output as is.In such a case, when the FM deviation is small, the second voltage control #3f: When using the protector 11, fluctuations in the center frequency become a problem, so the first
By using a voltage controlled oscillator 16 of 1 and performing frequency modulation of 1, K is obtained.
なお、位相検出器１１から検出される制御信号のＯＶベ
ベル同期状態の電位に設計しであるので、スイッチＳ、
のオンによって第１．又は第２０亀圧制御発振器１６．
、１７の発振周波数が瞬間的に大きく変化することはな
い。Note that the switch S is designed to have a potential in the OV bevel synchronization state of the control signal detected from the phase detector 11.
By turning on the first. or the 20th turtle pressure control oscillator 16.
, 17 do not change significantly instantaneously.
第１．又は第２の電圧制御発振器１６．１７には前記ス
イッチＳ！ と連動して動作する発振停止及び開始スイ
ッチを設け、使用しない電圧制御発振器（１６，１７）
は発振停止の状態に（−ておくことがスプリアス防止の
点から好ましい。1st. Alternatively, the second voltage controlled oscillator 16,17 has the switch S! The voltage controlled oscillator (16, 17) is equipped with an oscillation stop and start switch that operates in conjunction with the unused voltage controlled oscillator (16, 17).
It is preferable to keep oscillation stopped (-) from the viewpoint of preventing spurious noise.
第３図は、第１．又は第２の電圧制御発振器１６゜１７
の具体的な一実施例を示す回路図で、Ｔ１は制御信号の
入力端子、Ｔ２は中心周波数な調整する入力端子、■、
は出力端子である。この回路において、２１は電圧可変
容量ダイオード、２２は発振周波数を設定する共振回路
であり１例えば周波数安定度の高い第１の電圧制御発振
器１６の場合は水晶共振子、周波数偏移が広くなる第２
の電圧制御発振器１７の時はＬＣ並列共振回路か使用さ
れる。２３は発振のオン、オフを制御するスイッチで制
御端子Ｃからの信号（スイッチＳ、と連動）によって動
作するりＶ−２４によって作動するものである。スイッ
チ２３かオンすると共振回路２２に並列に抵抗分が付加
され発振か持続できなくなり発振停止する。２５は互（
・に正帰還されているトランジスタＱ＝ −Ｑｔ から
なる発振回Ｖ各、２６はトランジスタＱ３−Ｑ４からな
る出力回路を示す。なお、Ｔ８は出力端子である。Figure 3 shows the 1. Or second voltage controlled oscillator 16°17
In this circuit diagram, T1 is an input terminal for a control signal, T2 is an input terminal for adjusting the center frequency,
is the output terminal. In this circuit, 21 is a voltage variable capacitance diode, and 22 is a resonant circuit that sets the oscillation frequency.1 For example, in the case of the first voltage controlled oscillator 16 with high frequency stability, it is a crystal resonator, and 22 is a resonant circuit that sets the oscillation frequency. 2
When the voltage controlled oscillator 17 is used, an LC parallel resonant circuit is used. Reference numeral 23 denotes a switch for controlling oscillation on and off, which is operated by a signal from control terminal C (interlocked with switch S) or by V-24. When the switch 23 is turned on, a resistance is added in parallel to the resonant circuit 22, making it impossible to sustain the oscillation and stopping the oscillation. 25 is mutual (
26 indicates an output circuit consisting of transistors Q3-Q4. Note that T8 is an output terminal.
この回路では、入力端子■１から入力される信号がＯＶ
ベベル時に、虐定の発振周波数（例えを王２０ＭＨ，）
がイセられるように入力端子Ｔ、の電位（−Ｅ）及びホ
リューム２Ｔを調整し℃固定する。In this circuit, the signal input from input terminal ■1 is OV
When beveled, the oscillation frequency of abuse (eg 20MH,)
The potential (-E) of the input terminal T and the volume 2T are adjusted so that the temperature is fixed at ℃.
この状態で入力端子Ｔ１の電位が正、負に変化すると電
圧可変客員ダイオード２１の容量が変化し、この容量変
化が共振回路２２に付加されることによって発振周波数
が変化するものである。In this state, when the potential of the input terminal T1 changes from positive to negative, the capacitance of the voltage variable visitor diode 21 changes, and this capacitance change is applied to the resonant circuit 22, thereby changing the oscillation frequency.
前述した第１．第２の電圧制御発振器１６．１７を選択
するスイッチＳ、は１例えばＦＭ変購信号ｅＩ、ｌ の
振幅に応じて自動的に切り替えるようにしてもよく、又
周波数偏移に対応してパネル面で切り替えを指示し、マ
ニュアルで切り替えるようにしてもよい。又、スイッチ
Ｓ、についてもＦＭ変調信号ｅｍの周波数が低下した時
自動的にオンとするようにしてもよく、マニュアルで切
り替えるようにしてもよい。The above-mentioned 1. The switch S, which selects the second voltage controlled oscillator 16, 17, may be automatically switched depending on the amplitude of the FM signal eI,l, for example, or may be switched on the panel surface in response to frequency deviation. You may also be able to manually switch by instructing the switch. Further, the switch S may be turned on automatically when the frequency of the FM modulation signal em decreases, or may be turned on manually.
以上説明したように、この発明のＦＭ信号発生器は、Ｆ
Ｍ基準信号源として周波数安定度の高い第１の電圧制御
発振器と、周波数偏移が広い第２の電圧制御発振器を設
けであるので、広い周波数偏移ｔもち、かつ、ＦＭ変調
周波数が低い小さな周波数偏移でも周波数安定度のよ−
・ＦＭ−ＤＣモードの信号火発生すること力ｔできる。As explained above, the FM signal generator of the present invention has F.
Since the first voltage controlled oscillator with high frequency stability and the second voltage controlled oscillator with wide frequency deviation are provided as the M reference signal source, it has a wide frequency deviation t and a small FM modulation frequency with low frequency. Frequency stability even with frequency deviation
- Capable of generating signal fire in FM-DC mode.
又、ＦＭ−ＡＣモードでは第１．第２の電圧市ＩＪ御発
振器は、同一のＰＬＬ回路にお（・て参照イば号で位相
同期され、電圧制御発振器の切９替えに際してループゲ
インを同一になるようにする回路構成としたので、ＦＭ
基準信号源として中ＩＣ？周波数が安定化すると共に、
ＦＭ変調周波数特性や切換応答特性も同一になるという
利点かあるつAlso, in FM-AC mode, the first. The second voltage controlled oscillator is phase synchronized with the same PLL circuit (see Iba), and has a circuit configuration that makes the loop gain the same when switching the voltage controlled oscillator. , F.M.
Medium IC as a reference signal source? As the frequency stabilizes,
One advantage is that the FM modulation frequency characteristics and switching response characteristics are also the same.
第１図は従来のＦＭ信号発生器の７１ツク図、第２＠は
この発明の一実施例を示すＦＭ信号発生器のブロック図
、第３＠は第１（第２）の電圧ｉ制御発振器の１例を示
ず具体的な回路図である。
図中、１１は位相検出器、１２はフィルり、１３は利得
制御回路、１４は加算回路、１５【まＦＭ変調信号源、
１６．１７は第１．第２の鳳圧佑１］御発振器、１Ｂは
分周回路を示す。Fig. 1 is a block diagram of a conventional FM signal generator, Fig. 2 is a block diagram of an FM signal generator showing an embodiment of the present invention, and Fig. 3 is a block diagram of a first (second) voltage i-controlled oscillator. It is a specific circuit diagram without showing one example. In the figure, 11 is a phase detector, 12 is a fill, 13 is a gain control circuit, 14 is an addition circuit, 15 is an FM modulation signal source,
16.17 is the 1st. The second oscillator, 1B indicates a frequency dividing circuit.
Claims (1)
れる電圧制御発振器を備えてなるＦＭ（ｉ＠発生器であ
って；前記ＦＭ基準信号源が１周波数偏移幅の小さいｍ
ｌの電圧制御発振器と、周波数偏移幅の大きい第２の電
圧制御発振器と、前記第］又は第２の電圧制御発振器の
出力信号のいずれが一方を選択し°Ｃ出力する切替手段
と、参照信号と前記選択された出力信号との位相差７検
出する位相検出器と、該位相検出器の検出信号をろ波す
るフィルタと、該フィルタの出力に接続され前記第１の
電圧制御発振器が動作している時に利得が増加するよう
に制御される利得制御回路と、ＦＭ変調発生源のイ「号
と前記利得制御回路の出力とを加η−し、前記第１又は
第２の電圧制御発振器に制御信号と（−て供給する加算
回路とを備えたＰＬＬ回路からなることを特徴とするＦ
Ｍ （ｆｉ号発生器。 （２） 周波数変調されるＦＭ基準信号源に位相同期さ
れる電圧制御発振器を備えてなるＦＭ信号発生器であっ
て；前記ＦＭ基基準４暗 移幅の小さい第１の電圧制御発振器と、周波数偏移幅の
大きい第２の電圧制御発振器と、前記第１又は第２の電
圧制御発振器の出力信号のいずれか一方を選択して出力
する切替手段と、参照信号と前記選択された出力信号と
の位相差ヶ検出する位相検出器と．該位相検出器の検出
信号をろ波するフィルタと、該フィルタの出力に接続さ
れ前記第１の電圧制御発振器が動作している時に利得が
増加するように制御される利得制御回路と，ＦＭ変調づ
ご生涯の信号と前記利得制御回路の出力とを加算し，前
記第１又は第２の電圧制御発振器に制御信号として供給
する加算回路と、前記ＦＭ変調信号発生源の信号が前記
フィルタのカットオフ周波数以下の時に、前記利得制御
回路の出力を断とするためのスイッチとを備えたＰＬＬ
回路からなることを％徴とするＦＭ信号発生器。[Claims] (]) An FM (i@ generator) comprising a voltage controlled oscillator phase-locked to an FM reference signal source with a one frequency deviation; small width m
a voltage controlled oscillator of l, a second voltage controlled oscillator with a large frequency deviation width, a switching means for selecting one of the output signals of the first voltage controlled oscillator or the second voltage controlled oscillator and outputting the output signal in °C; a phase detector for detecting a phase difference 7 between a signal and the selected output signal; a filter for filtering a detection signal of the phase detector; and a first voltage-controlled oscillator connected to the output of the filter. a gain control circuit that is controlled so that the gain increases when F characterized in that it is comprised of a PLL circuit equipped with a control signal and an adder circuit that supplies a control signal to (-).
(2) An FM signal generator comprising a voltage controlled oscillator that is phase-locked to a frequency-modulated FM reference signal source; a voltage controlled oscillator, a second voltage controlled oscillator with a large frequency deviation width, a switching means for selecting and outputting either one of the output signals of the first or second voltage controlled oscillator, and a reference signal. a phase detector that detects a phase difference with the selected output signal; a filter that filters a detection signal of the phase detector; and a first voltage-controlled oscillator connected to the output of the filter that is in operation. a gain control circuit that is controlled so that the gain increases when the oscillator is in use; and a gain control circuit that adds the signal during FM modulation and the output of the gain control circuit, and supplies the resultant signal to the first or second voltage controlled oscillator as a control signal. and a switch for cutting off the output of the gain control circuit when the signal from the FM modulation signal generation source is below the cutoff frequency of the filter.
An FM signal generator that consists of a circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58130193A JPS6022828A (en) | 1983-07-19 | 1983-07-19 | Fm signal generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58130193A JPS6022828A (en) | 1983-07-19 | 1983-07-19 | Fm signal generator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6022828A true JPS6022828A (en) | 1985-02-05 |
| JPH0345937B2 JPH0345937B2 (en) | 1991-07-12 |
Family
ID=15028308
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58130193A Granted JPS6022828A (en) | 1983-07-19 | 1983-07-19 | Fm signal generator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6022828A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2022108561A (en) | 2021-01-13 | 2022-07-26 | 住友重機械建機クレーン株式会社 | winch brake device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57188435U (en) * | 1981-05-25 | 1982-11-30 |
-
1983
- 1983-07-19 JP JP58130193A patent/JPS6022828A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57188435U (en) * | 1981-05-25 | 1982-11-30 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0345937B2 (en) | 1991-07-12 |
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