JPS60227525A - Automatic equalizer - Google Patents

Abstract

PURPOSE:To easily integrate circuits and to improve the equalizing accuracy and operation stability of an automatic equalizer, by performing the operation in the automatic equalizer through simple digital operation by using a ternary level taken by bipolar codes. CONSTITUTION:A received signal from the signal input terminal 1 of an automatic equalizer and an equalizing signal from an LPF11 are added to each other at an analog adder 3 and the output of the adder 3 is quantized to a ternary code or a code higher than the ternary code by AD converting devices 12 and 13 and further quantized to ternary codes of 1, 0, and -1 at a decoding circuit 4. The output of the circuit 4 is delayed by a period equal to the bit cycle of a bipolar code at unit delaying circuits 5-1-5-3 and each tap output A1-A3 is inputted to arithmetic circuits GACs 6-1-6-3. Moreover, output of the device 13 is inputted to the GACs 6-1-6-3 and tap coefficients corrected in accordance with the change in tap are outputted from arithmetic circuits CADs 7-1-7-3. Outputs of the circuits 5-1-5-3 are multiplied by the tap coefficients by multipliers 8-1- 8-3 and DA converted 10. The converted output is inputted into the adder 3, and thus, the accuracy and operation of the equalizer are improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an automatic equalizer for removing waveform distortion caused by code amount interference of codes transmitted in the form of bipolar pulses.

[Prior art]

FIG. 1 is a block diagram showing a conventional automatic equalizer,
(l) is a signal input terminal, (2) is a signal output terminal, (3)
is an analog adder, (4) is a bipolar signal decoding circuit (the drawing symbol is DEC), (5-1), (5-
2).

... (5-N) are unit delay circuits (drawing symbol is D), (6-1)', (6-2), ...
(6-N) are arithmetic circuits, tentatively called GAC circuits, and (7-1).

(7-2'), ... (7-N) are arithmetic circuits, which are tentatively called CAD circuits.8-1), (8-
2) , . . . (8-N) are each multipliers.

Also, x (t) is the input signal waveform (t is time), y (t
) is the output signal waveform, A (t) is y (t) by DEC (
41, and is decoded into a bipolar signal by threshold value judgment, and is expressed as one of the three values (1°0, -1).

T=l/fo is the transmission pulse interval, and each unit delay circuit (5-1), (5-2), . . . (5-N) provides a delay time of T.

In the circuit shown in FIG. 1, y (tl = x (tl+Σ'CiA (t +
iT )...The feedback calculation in (1) is performed, and the waveform y (tl), which removes the code amount interference caused by the reflection of the bipolar pulse, is output. However, in equation (1), Ci
is a coefficient called a tap coefficient. Still, the value of A(t) is constant for iT≦1<(1+1)T (i is an integer).

When the equalization evaluation function φ is a squared error, it is given by φ=Σh2(t−jT) (2) j=1. However, it is assumed that h (tI is an impulse response and the main pulse is received at time t. The tap coefficient Ci is modified so that φ is kept as small as possible.

At this time, if the steepest descent method is used as the correction algorithm for the tap coefficient C1, C, (new) = C1 (current) - α (δφ/δc, )...
(3) δφ/δC1-j king. y(t-jT)A(t-J
T+iT)...It may be corrected according to (4). Note that equation (4) is derived assuming that an impulse is input to the circuit of FIG. 1 expressed by equation il+. Strictly speaking, the influence of impulse input remains forever, so ideally it is necessary to calculate the sum up to j = ~ as shown in equation (4), but in order to be uniform, periodic isolated pulses Since this is used as a training signal, the summation is completed within that period.

In the GAC circuit shown in Figure 1, the calculation of equation (4) is performed to obtain δφ/
δCi is calculated, and the CAD circuit calculates equation (3) using the δφ/δCiO value to correct the tap coefficient C1.

However, it is not easy to calculate Equation 9 (4) using an analog circuit, so in the past, terms other than KoniO were omitted on the right side of Equation (4) and δφ/δCH= y(t)A (
t+iT')...(5), or the equation (4) is calculated using an analog integrator. Furthermore, there are cases in which an analog multiplier is used to perform the calculation of equation (5), and y(t) is approximated by either +1 or -1 (using only the polarity of y(t)) for further simplification.
There was a case. Analog integrators or multipliers have complicated circuits and poor accuracy. In particular, analog integrators cause errors due to a downward lift of the DC bias, and equation (5)
Since the accuracy of the approximation is not sufficient, the convergence of the equalizer becomes slow when this approximation is used.

[Summary of the invention]

This invention was made to eliminate the drawbacks of the conventional ones as described above, and in this invention, the output coefficient y (tl
The present invention provides an automatic equalizer with high equalization accuracy and stable operation by converting the signal into a digital signal and performing calculations in the GAC circuit, CAD circuit, multiplier, etc. as digital calculations.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention.
This corresponds to the case where N=3 in the conventional equalizer shown in the figure. In FIG. 2, the same reference numerals as in FIG. 1 indicate the same or corresponding parts. (lj, l.

GAC circuit (6-1), (6-2), (6-3),
CAD circuit (7-1).

(7-2), (7-3), multiplier (8-1),
Digital operations are performed in (8-2) and (8-3). (9) is an adder, (I (j is a D/A transformer, α9 is a low-pass filter, (12+ is an A/D converter, (131 is a signal format conversion circuit, and signal Y is a signal
(t) is converted into a digital signal by the A/D converter [121, and further converted into a signed 2 signal by the circuit (13).
Shows a signal converted to a base number (negative numbers are represented as complements). This light? In the tAli book, 1121 and (13) are collectively referred to as analog-to-digital conversion equipment.

FIG. 3 shows the relationship between y(t) and Y. In the example shown in FIG. 3, Y can be represented by 4 binary bits, including the sign.

The decoding circuit (4) corresponds to the decoding circuit (41) in Fig. 1, but since its input is a digital signal, it is composed of a gate circuit, and when Y≧4, A=+1.3≧Y≧-3 A
=0. When −4≧Y, A knee 1 is output.

However, the ternary signal A is expressed as a 2-bit binary signal +1=rl
OJ, 0=r00J, -1=rotJ. Signal A is delayed by T by the unit delay circuit, A-□ (same as A(t+T) in Figure 1), A-2 (A(t+2) in Figure 1),
T) and A-3 are the same as in the case of FIG. 2 is the output %Z of the adder (9) (is the output of the low-pass filter (31), Y (t) = x (tl +
z(tl...(6 corresponds to equation (1) in FIG. 1).

Furthermore, equation (4) in FIG.
i...(7). Here, i represents the tap position, and j represents the time after the arrival of the isolated pulse. By the way, since the values of A, , are limited to three values (+1.0.-1'), this can be executed.

FIG. 4 is a block diagram showing an embodiment of the GAC circuit of FIG. 2, in which 04 is an arithmetic operation unit (hereinafter abbreviated as ALU) composed of a full adder, and A9 is a register. Further, an example is shown in which Yj is 4 bits and the input/output of register 09 is 8 bits. If Aj□=+1, Yj is added to the contents of register a9 to make Gi, and A
When j-4=-1, subtract Y from the contents of register 09 to get G, and when Aj-i=O, ALU (1
4 is not operated, and the previous G.
Bind and output.

FIG. 5 is a block diagram showing an embodiment of the CAD circuit shown in FIG. 2, where 00 is an ALU and αη is a register. Tap coefficient Ci is stored in register aη. Corresponding to equation (3), Ci (new) = ct (current) - αG ... (8) is calculated, but the coefficient α is set to α = 2, (L = integer from 1 to 7). By limiting, instead of calculating αG, the right input of ALU (1G) can be made αGi by simply shifting the bits of Gi by binary digits lower than the bits of C4.

Corresponding to C and A (t + iT) in equation (1), the multiplier (8-i) in FIG. 2 performs an operation of C1A-i. FIG. 6 is a connection diagram showing an embodiment of the multiplier (8-i) in FIG. be. As explained earlier, A-1 is 3-valued and +1 is "
1o", that is, (AO=rlJ, A1=rOJ)0 is "
Oo'', i.e. (Ao=rOJ, A□=rOJ), -1
is “01”, that is, (Ao=rOJ , A,=r I
J), so when A = 0, the output of OR game 1 and 0υ is "0", the outputs of all AND gates 4 to (C) are "0", and A□ is Since rOJ, all exclusive or gates (a) ~
If the output of (b) is "0", this becomes C4A-41: If A-i = 1 and A1--1, the output of AND gates (to) to (c) is each bit of Ci. Leave it as 1i
When =1, A□ is "0", so each bit of 01 becomes each bit of C, A, and A-.

=-1, since A□ is "1", the logic of each bit of C1 is inverted and becomes each bit of C, A, and so on.

-1 Figure 7 is a block diagram showing an embodiment of the adder (9) in Figure 2, where trowel and cm are ALUs, and Z=CI
A-1''C2A-20C3A-3...(9) is added.

The right side of equation (9) is ΣC,A (t + iT
).

i=1 1 The value of 2 calculated by equation (9) is converted into an analog signal by the D/A converter ad, passes through the low-pass filter αJ, and then the calculation of equation (6) is performed by the analog adder (3). be exposed.

〔Effect of the invention〕

As described above, according to the present invention, the three-level nature of the bipolar code is used to make the calculations in the automatic equalizer simple digital calculations, making it easy to centralize the circuit and Good accuracy and operational stability. Furthermore, since it is a digital calculation, it is easy to handle changes in the algorithm.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing a conventional automatic fixture, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 is a block diagram of an analog-to-digital converter in Fig. 2. A diagram showing the characteristics,
4 is a block diagram showing an embodiment of the GAC circuit in FIG. 2, FIG. 5 is a block diagram showing an embodiment of the CAD circuit in FIG. 2, and FIG. Connection diagram showing an embodiment. FIG. 7 is a block diagram showing an embodiment of the adder in FIG. 2. (1)...Signal input terminal, (2)...Signal output terminal, (3)...Analog adder, (4)...Decoding circuit, (5-1), (5-2) . (5-3)...each unit delay circuit, (6-1)
, (6-2). (6-3)... GAC circuit, (7-1),
(7-2). (7-3)... CAD circuit, (8-1), respectively
(8-2). (8-3)...Multiplier, (9)...Adder, +lt1...D/A converter, fill...Low pass filter, (12, (t*...Analog-to-digital conversion) Apparatus. In addition, the same symbols in each figure indicate the same or corresponding parts.
Figure Y Figure 4 Figure 5

Claims (1)

[Claims] An automatic equalizer that inputs a signal transmitted in the form of a bipolar code and corrects the waveform of the input signal, comprising: an analog adder that adds a received signal and an equalized signal; an analog-to-digital converter that quantizes the output signal of the converter into multi-values of 8 or more;
It is composed of a decoding circuit that quantizes J into three values and a plurality of unit delay circuits connected in series, and receives the output of the decoding circuit and gives each unit delay circuit a delay amount equal to the bit period of the bipolar code. and output
a delay device configured to invert taps for each unit delay circuit; and a register provided for each tap, the output of the unit delay circuit being one of the three values rlJ, r-I.
Each register is controlled such that the output of the analog-to-digital converter is added to or subtracted from the contents of the register, or the contents of the register are not changed depending on whether the register is J or rOJ; Each digital arithmetic circuit is provided for each register and corrects and outputs the tap coefficient of the tap according to the contents of the register, and each digital arithmetic circuit multiplies the output of each digital arithmetic circuit by the output of the unit delay circuit of the tap. a multiplier, an adder that adds the outputs of all the multipliers, a digital-analog converter that converts the output of this adder into an analog voltage, and smoothes the output of the digital-analog converter to obtain the above equalized signal. An automatic equalizer comprising: a low-pass filter;