JPS60227414A - Manufacturing apparatus of thin film - Google Patents
Manufacturing apparatus of thin filmInfo
- Publication number
- JPS60227414A JPS60227414A JP6355985A JP6355985A JPS60227414A JP S60227414 A JPS60227414 A JP S60227414A JP 6355985 A JP6355985 A JP 6355985A JP 6355985 A JP6355985 A JP 6355985A JP S60227414 A JPS60227414 A JP S60227414A
- Authority
- JP
- Japan
- Prior art keywords
- plate
- thin film
- substrate
- thin
- target
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/0242—Crystalline insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Physical Vapour Deposition (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は薄膜の製造装置に関するもので、さらに詳述す
れば放電を介在して薄膜を堆積させる薄膜製造装置に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a thin film manufacturing apparatus, and more specifically, to a thin film manufacturing apparatus that deposits a thin film through electric discharge.
グロー放電中でのCVD (Chemical Vap
orDeposition )法(以下G−CVD法)
およびスパッタリング(Sputtering )法は
、加熱蒸着法と並んで、薄膜堆積法の最も普通な方法と
なって来ている。放電を介在する方法は元来自然の状態
では必ずしも存在しないもの、又は反応の弱いものでも
その反応を、電気化学的に生ぜしめて、薄膜化するため
、材料によっては、特性のすぐれた薄膜が得られる場合
が多い、さらにRF (Radi。CVD (Chemical Vap) in glow discharge
orDeposition) method (hereinafter referred to as G-CVD method)
Along with thermal evaporation, sputtering has become the most common method of thin film deposition. The method of mediated electrical discharge electrochemically generates a reaction even with substances that do not necessarily exist in nature or have a weak reaction, thereby creating a thin film, so depending on the material, thin films with excellent properties may be obtained. In addition, RF (Radio) is often used.
Frequency )スパッタリング法では、融点の
ないか又は、蒸着用ボートと反応するような物質材料で
も容易に薄膜化し得る方法として、巾広く用いられてい
る。スパッタ法を例にとって装置の原理を説明すると、
薄膜に堆積したい母材を一方の電極(ターゲット)とし
、その対向電極に、薄膜堆積用基板をセットする。これ
らが真空槽内に装備されている。この槽にガスを流して
1〇−雇〜1o−2Torrの真空度に保ち、電極間に
電力を供給する。The sputtering method is widely used as a method that can easily form a thin film even with materials that do not have a melting point or that react with the vapor deposition boat. To explain the principle of the device using sputtering as an example,
A base material on which a thin film is to be deposited is used as one electrode (target), and a thin film deposition substrate is set on the opposite electrode. These are installed in a vacuum chamber. Gas is flowed through this tank to maintain a vacuum of 10 to 10 Torr, and electric power is supplied between the electrodes.
しかる時、A r ’でたたき出されたターゲット母材
の元素が対極の基板ホールダ上に到達し堆積される。な
お、これについてはマッツェル著、薄膜技術ハンドブッ
ク、(MATSSEL:THINFILM HANDB
OOK )p、4−31゜↓970 に記載されている
。G−CVD法はスパッタ法と異なり膜堆積母材をガス
状で真空槽内に導入する。放電圧力は0.1〜I To
rr程度にし真空槽に配置された電極に電力を供給して
分解反応を促して電極上にセットした基板上に膜を堆積
する。At that time, the elements of the target base material that have been ejected by Ar' reach and are deposited on the opposite substrate holder. Regarding this, please refer to Thin Film Technology Handbook, written by Matzel (MATSSEL: THINFILM HANDB).
OOK) p, 4-31°↓970. Unlike the sputtering method, the G-CVD method introduces a film deposition base material in a gaseous state into a vacuum chamber. The discharge pressure is 0.1~I To
The decomposition reaction is promoted by supplying power to the electrodes placed in the vacuum chamber at a temperature of about rr, thereby depositing a film on the substrate set on the electrodes.
これらの方法は両者とも放電を介するため、蒸着法等と
比べて、膜堆積中に基板に対する、電気的な影響力が大
きく、基板にすでに能動回路が存在する時には、基板に
ある素子を破壊してしまう場合が多く、特に基板に5i
−LSIを用いる場合には基板中に構成されたp−n接
合をこわしてしまう場合が多い。このように基板に存在
するp−n接合を破壊する原因は、膜堆積用の放電電力
の実効電流が、基板を通して流れてしまうからである。Since both of these methods involve electrical discharge, they have a greater electrical influence on the substrate during film deposition than methods such as vapor deposition, and if the substrate already has active circuits, they may destroy the elements on the substrate. In many cases, especially if the board has 5i
- When using an LSI, the pn junction formed in the substrate is often destroyed. The reason why the pn junction existing in the substrate is destroyed is that the effective current of the discharge power for film deposition flows through the substrate.
本発明の目的は上記問題点のない、安定した電記的特性
を有した薄膜を形成できる薄膜製造装置を提供すること
にある。SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film manufacturing apparatus that does not have the above-mentioned problems and can form a thin film with stable electrographic properties.
上記目的を達成するための本発明の構成は、試料の保持
板と試料との間に絶縁板を介在せしめることにある。The structure of the present invention for achieving the above object is that an insulating plate is interposed between the sample holding plate and the sample.
絶縁板としては、厚さ0.2〜6mmの板状のものが用
いられる。石英、アルミナ、ガラスなどが用いられるが
、放電における電流を遮断する上からは石英板が最も好
ましい。また、絶縁板は、予め試料台に結合されてあっ
てもよいが、洗浄等の便宜から取り外し可能なものの方
がより効果的である。普通、薄膜を形成される試料は、
Siやその他の半導体基板が用いられるが、これらの試
料にはトランジスタやその他の能動回路素子が設けられ
ている。これらの素子を上記放電による電流又は電圧な
どの不要な電気的作用から破損防止するためには、上記
絶縁板の厚さは0.2〜6mmにしておくことが肝要で
ある。上記範囲を超えるものは、絶縁の効果および薄膜
形成の効率を著しく低下せしめるので好ましくない。以
下実施例を用いて詳述する。As the insulating plate, a plate-shaped one having a thickness of 0.2 to 6 mm is used. Although quartz, alumina, glass, etc. can be used, a quartz plate is most preferable from the standpoint of blocking current during discharge. Further, the insulating plate may be connected to the sample stage in advance, but it is more effective if it is removable for convenience such as cleaning. Normally, the sample on which a thin film is formed is
Although Si or other semiconductor substrates are used, these samples are provided with transistors and other active circuit elements. In order to prevent damage to these elements from unnecessary electrical effects such as current or voltage caused by the discharge, it is important that the thickness of the insulating plate be 0.2 to 6 mm. If it exceeds the above range, it is not preferable because it significantly reduces the insulation effect and the efficiency of thin film formation. This will be explained in detail below using examples.
第1図は本発明の薄膜製造装置の一例を示したものであ
る。1が真空槽でり、2が真空排気口である。真空槽内
には、薄膜用母材のターゲット3と基板ホールダ(保持
板)4が装備されており、この基板ホーシダ4上に本考
案の絶縁板5があり、この上に薄膜堆積用の基板6があ
る。真空槽にはさらに放電ガスを導入するリークバルブ
7があり、このバルブよりガスを流して、 スパッタの
場合には10−3〜10−” Torr台の真空度にし
て放電用の雰囲気を形成する。次に3に接続された電源
8より直流スパッタの場合は数Vまでの電圧を、RFス
パッタの場合には数W / c m 2の範囲内で電力
を供給し、放電状態を形成して薄膜を堆積する。この時
、基板6の下の、絶縁板5のない時はくことにより実効
電流を遮断する。このことにより基板6内での電位降下
が生じていないめ、従って基板中の素子の破壊を防ぐこ
とができる。本発明の絶縁板は実効直流電流を切断する
目的で挿入するので厚さ5mmの石英板、アルミナ板又
は、ガラス板を敷くことによって目的を達することがで
きるが、最も好ましい状態としては約0.5〜1 、5
m m厚の石英板が良好であり、この板を敷くことに
よって、SiのMOS型で構成された撮像用走査回路の
上に非晶質Si膜をスパッタ法で堆積するに際して、大
へん有効であり、この方法によらない場合、走査回路の
p−n接合が破壊される場合が多いのに比べて、この破
壊を防止することができた。FIG. 1 shows an example of the thin film manufacturing apparatus of the present invention. 1 is a vacuum chamber, and 2 is a vacuum exhaust port. The vacuum chamber is equipped with a target 3 for thin film base material and a substrate holder (holding plate) 4, and on this substrate holder 4 there is an insulating plate 5 of the present invention, on which a substrate for thin film deposition is placed. There are 6. The vacuum chamber further has a leak valve 7 for introducing discharge gas, and the gas is flowed through this valve to create an atmosphere for discharge at a vacuum level of 10-3 to 10-'' Torr in the case of sputtering. Next, from the power supply 8 connected to 3, a voltage of up to several V is supplied in the case of DC sputtering, and power is supplied within the range of several W/cm2 in the case of RF sputtering to form a discharge state. A thin film is deposited. At this time, the effective current is cut off by removing the insulating plate 5 under the substrate 6 when there is no insulating plate 5. As a result, there is no potential drop within the substrate 6, so the Destruction of the element can be prevented.Since the insulating plate of the present invention is inserted for the purpose of cutting off the effective direct current, this purpose can be achieved by laying a 5 mm thick quartz plate, alumina plate, or glass plate. , the most preferable state is about 0.5-1.5
A quartz plate with a thickness of mm is suitable, and by laying this plate, it is very effective when depositing an amorphous Si film by sputtering on an imaging scanning circuit composed of a Si MOS type. Yes, and compared to the case where the pn junction of the scanning circuit is often destroyed when this method is not used, this destruction could be prevented.
上記例はMO8型基板の例であるがMO8型以外のCC
D型等の素子より構成された基板を用いる場合にも有効
であり、さらにGaAs系等の化合物半導体基板を用い
る場合にも有効であり、さらにSi基板の表面に形成さ
れる。Afi、多結晶SL、Ta、Mo、Cr等のすで
に接合を形成された後の配線用導電材料をスパッタ法で
堆積する場合、又は、絶縁膜をG−CVD法、スパッタ
法で堆積する場合にも有効である。The above example is an example of an MO8 type board, but CCs other than MO8 type
It is also effective when using a substrate made up of elements such as a D-type element, and furthermore, it is also effective when using a compound semiconductor substrate such as a GaAs-based compound semiconductor substrate, and furthermore, it is formed on the surface of a Si substrate. When depositing a conductive material for wiring such as Afi, polycrystalline SL, Ta, Mo, Cr, etc. by sputtering after a junction has already been formed, or when depositing an insulating film by G-CVD or sputtering. is also valid.
以上詳述したように1本発明は放電を使用する薄膜製造
装置において、試料と試料保持板との間に薄い絶縁板を
介在させることにより、基板表面の素子に損傷を与える
ことなく、良好な薄膜素子を形成することができる点、
工業的利益大なるものである。As detailed above, one aspect of the present invention is to provide a thin film manufacturing apparatus that uses electrical discharge by interposing a thin insulating plate between the sample and the sample holding plate, thereby achieving good performance without damaging the elements on the surface of the substrate. The point that a thin film element can be formed;
The industrial benefits are huge.
第1図は本発明の一実施例としての薄膜製造装置の概略
断面図である。
1・・・真空容器、2・・・真空排気口、3・・・ター
ゲット、4・・・試料保持板、5・・・絶縁板、6・・
・試料(基板)。
7・・・リークバブル、8・・・電源。
第 1 図FIG. 1 is a schematic sectional view of a thin film manufacturing apparatus as an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Vacuum container, 2... Vacuum exhaust port, 3... Target, 4... Sample holding plate, 5... Insulating plate, 6...
・Sample (substrate). 7...Leak bubble, 8...Power supply. Figure 1
Claims (1)
形成手段と、該容器内に設けられた試料保持板と、少な
く共上記保持板の近傍に設けられた放電手段とを備えた
薄膜製造装置において、上記保持板と試料との間に絶縁
板を介在させたことを特徴とする薄膜製造装置。A container, an atmosphere forming means for the container connected to the container, a sample holding plate provided in the container, and a discharge means provided at least in the vicinity of the holding plate. A thin film manufacturing apparatus characterized in that an insulating plate is interposed between the holding plate and the sample.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6355985A JPS60227414A (en) | 1985-03-29 | 1985-03-29 | Manufacturing apparatus of thin film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6355985A JPS60227414A (en) | 1985-03-29 | 1985-03-29 | Manufacturing apparatus of thin film |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60227414A true JPS60227414A (en) | 1985-11-12 |
Family
ID=13232696
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6355985A Pending JPS60227414A (en) | 1985-03-29 | 1985-03-29 | Manufacturing apparatus of thin film |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60227414A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6767429B2 (en) * | 2000-01-12 | 2004-07-27 | Tokyo Electron Limited | Vacuum processing apparatus |
KR100805731B1 (en) | 2006-08-30 | 2008-02-21 | 주식회사 포스코 | Apparatus for surface modification by plasma ion implantation and the method thereof |
-
1985
- 1985-03-29 JP JP6355985A patent/JPS60227414A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6767429B2 (en) * | 2000-01-12 | 2004-07-27 | Tokyo Electron Limited | Vacuum processing apparatus |
KR100805731B1 (en) | 2006-08-30 | 2008-02-21 | 주식회사 포스코 | Apparatus for surface modification by plasma ion implantation and the method thereof |
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