JPS60226069A - Digital audio reproducing device - Google Patents

Abstract

PURPOSE:To reduce the circuit scale of a DAC by applying the period of a half period of a frequency signal of two times of a sampling frequency inputted to the DAC, to an integral capacity discharge period and a sampling signal period, respectively, and inputting a signal of two times or four times of the sampling frequency to the DAC. CONSTITUTION:A DAC110 receives signals of 123-125 from a digital filter circuit 113, sets a discriminating terminal 119 to a GND level when the prestage is inserted into a digital filter, and it is provided with two integrators, executes, integration of one channel in a period in which the signal of 124 is ''LO'', executes integration of the other channel in the period of a half period of ''HI'', and uses two channels in common by providing only one set of current source. Also, an integral capacity discharge period and a sampling period of a sample holding circuit of the post-stage are set to the period of a half period of the frequency signal 125 of two times of right and left discriminating signals, by which it is possible to obtain a system which can always generate easily a suitable integral capacity discharge period and a sampling period, even if a sampling period and a master clock frequency are varied. In such a way, a digital filter LSI and a DACIC small in circuit scale can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a digital recording signal reproducing apparatus for digital audio and the like, and particularly to a signal format of a digital signal processing circuit, a digital filter circuit, and a digital to analog converter system.

[Background of the invention]

FIG. 1 shows a block diagram of a well-known digital audio playback device. 106 is a recording medium on which information signals are recorded as digital signals; 107 is a reading device that reads the recorded signals from the recording medium 106 using light or magnetism; and 108 is a signal read out by the reading device 107. 109 is a digital signal processing circuit that performs decoding, interleaving, error correction, etc.; 110 is a digital/analog converter ( (hereinafter abbreviated as DAC), and 111 is an output terminal for analog audio signals.

Next, the operation of the DAC No. 110 will be explained.

An integral type DAC, as disclosed in Japanese Patent Publication No. 58-4116, integrates a constant current for a period determined by a digital input to obtain an analog voltage output. The integration period is determined using a counter. When simply integrated, the counter clock frequency falk is determined by the DAC conversion time T and the number of quantization bits N, and the conversion time t10μI and the number of quantization bits ? :16, which is a value that is difficult to realize with integrated circuits.

A 16-bit integration type DAC % proposed to lower the clock frequency of this counter is shown in FIG. This example is from Nikkei Electronics' ``Low distortion 16-bit ICA for digital and audio'' dated January 18, 1982.
-D, DA converter". Second
In the figure, 1 is an operational amplifier for integration, 2 is a capacitor for integration, 3 is a switch that discharges the charge of the capacitor, and 4 is an upper 8
constant current source on the bit side, 5 is constant current source on the lower 8 bit side,
6 is the upper 8 which conducts and cuts off the constant current source 4 on the upper 8 bit side.
Current switch on the bit side.

7 is the lower 8 which conducts and cuts off the constant current source 5 on the lower 8 bit side.
A current switch on the bit side, 8 a counter on the upper 8 bit side that determines the conduction period of the current switch 6 on the upper 8 bit side, 9 a counter on the lower 8 bit side that determines the conduction period of the current switch 7 on the lower 8 bit side, 10 is counter 8,9
and a control circuit that determines the control timing of switch 3.

11 is digital, data input, 12 is a-click input,
15 is an analog output. FIG. 5 shows a timing chart for explaining the operation. 14 is the waveform of the analog output which is the output of the integrator, 15 is the conduction period of the discharge switch 3, 16 is the conduction period of the current switch 6 on the upper 8 bit side,
17 is the conduction period of the current switch 7 on the lower 8 bit side; 1
8 is an output period in which a signal converted to analog is output.

First, during the conduction period 15, the switch 5 is closed to discharge the charge charged in the capacitor 2 in the previous cycle. At the same time, the digital data is divided into upper 8 bits and lower 8 bits and set in counters 8 and 9, respectively. Thereafter, current switches 6 and 7 are made conductive for a period corresponding to the data set in counters 8 and 9. The constant current values of the constant current source 4 on the upper 6 bit side and the constant current source 5 on the lower 8 bit side are weighted 28:1, that is, 256:10. Conduction period 16 and lower 8 determined by upper 8 bits of data
During the conduction period 17 determined by the bit data, the capacitor 2 is charged by the constant current sources 4 and 5, respectively, and a waveform 11' is obtained at the analog output 15 which is the output of the integrator. The subsequent analog value is a value obtained by converting digital data into analog data, and is output to the next stage in output period 1B.

By providing two weighted current sources that divide the 16 bits into upper 8 bits and lower 8 bits, the clock frequency f'clk of the counter can be set to ft elk = high middle 2sPI.
The value is set to be achievable at IHz. In this case, the accuracy of the current ratio of the two indoor O and S flow sources should be within 0.2%.

In addition, it is expected that systems in which a digital filter is provided before the DAC will become widespread in the future. This is to avoid deterioration of the high-frequency phase characteristics of the analog filter provided at the output, but in this case the DAC needs to be able to handle a sampling frequency that is two to four times the normal sampling frequency. In other words, the conversion time of the DAC is reduced to 1
/2 to 1/4. If the DAC conversion time is 5 μl, 2 μl is required for capacitance discharge time and data sampling, so the actual time available for conversion is 5 μl.
μI, the required clock frequency is φ85, and it is difficult to integrate it into an IC. To avoid this, if 16 bits are divided into 5 bits, 5 bits, 5 bits, and 6 bits,
The counter only needs to count 6 bits, or 64, and the clock frequency can be lowered to 1/4, or 21 MHz.

In this case, the weighted current sources are 1:52:102
It is necessary to prepare 4-6ai types, and the current ratio accuracy is f
o 5 or ±0.05% is required.

024 FIG. '4 shows a DAC that divides a 16-bit input digital signal into five and integrates them in parallel, and the same symbols as in FIG. 2 indicate the same functions. 27 is the upper 6 bit counter, 2
8 is a middle 5-bit counter.

29 is a counter for the lower 5 bits, 25 is a current source for the upper 6 bits, and 22 is a current source for the middle 5 bits.

21 is a current source for the lower 5 bits, 26 is a current switch for the upper 6 bits, 25 is a current switch for the middle 5 pits, 24 is a current switch for the lower 5 pits, ts,
The current ratio of the current sources 2z and 21 is set to 1024:52:1. 50 is a control circuit that controls a counter and a switch. FIG. 5 shows a timing chart for explaining the operation. 51 is the analog output 15 which is the output of the integrator.
52 is the conduction period of the discharge switch 5, 55 is the conduction period of the current switch 26 for the upper 6 bits, 54 is the conduction period of the current switch 25 for the middle 5 bits, and 55 is the conduction period of the lower 5 bits.
The conduction period 56 of the pit current switch 24 is a period during which a signal converted into an analog signal is output. First, during the conduction period 52, the switch 5 is closed to discharge the charge stored in the capacitor 2. At the same time, the upper 6 bits and middle 5 bits of digital data.

The lower 5 bits are divided into counters 27 and 28°2 respectively.
Set to 9. Thereafter, at the same time as the switches 24, 25, and 26 are closed, a clock is supplied to the counters 27, 28, and 29, and the switches 24, 25, and 26' are opened at the count number set in each counter. As a result, the currents of the current sources 21, 22, and 25 flow into the capacitor 2 during their respective conduction periods, and a waveform 51 is outputted to the output 15 of the integrator 1. After that, the analog value of analog output 13 is! It is a value converted from digital data to analog, and is output to the next stage in an output period 56.

As described above, by dividing the 16 bits into the upper 6 bits, middle 5 bits, and lower 5 bits, the conversion time of 5 μI, which can be accommodated by a digital filter, is 52.5.
If the period of 6 is 1 μS each, the time required for conversion is 3 μS, and the required clock frequency f'clk is f'clk = "- = 21.5M (J'5μ♂, which is a value that can be realized with an IC. The operations of the 2-parallel integration and 6-parallel integration type DACs have been explained above.
Integral type DAC, ' is 2. in FIG. A control signal is required for the switch that discharges the charge of the integrating capacitor 2 shown in 5 in FIG.

Further, although not shown in FIGS. 2 and 6, a sample circuit is required to accompany the converted analog value. Sample as a resample circuit.

This will be explained using a hold circuit as an example. sample.

The hold circuit requires a control signal for outputting the sampling signal (FIG. 5, 18) to FIG. 5, 56. FIG. 6 shows a time chart of a two-parallel integrating DAC using two integrators for left and right channels. Integrator 1.2 is added to the circuit shown in Figure 2.
．． By installing another set of DACs 5 and switching the input of the integrator using the left and right channel identification signals, it becomes possible to perform digital and analog conversion of the left and right two channels with one DAC.

In FIG. 6, 41 is the first left and right channel identification signal output from the digital signal processing circuit, 1LOm is the left channel, and 'HI' is the right channel. 42 is the output waveform of the right channel integrator.

45 is the integral capacitance discharge control signal of the right channel 44 is the signal 4
This is a sampling signal for the right channel created by applying a delay to 44. When 44 is @HI'', sampling is performed, and when 44 is @LO'', it is held. 45 is the output waveform of the left channel integrator, and 46 is the discharge control signal of the left channel integral capacitor. 47 is a sampling signal for the left channel. The sampling signal of 44.47 can be obtained by simply delaying the signal of 41 by a few clocks, but the sampling signal of 45.46
The capacitive discharge signal can be obtained by detecting a change in the signal 41, counting a high-speed four-wheel pulse that counts an integration period, turning it on, and then counting it for a certain period of time and turning it off. In this case, a high-speed counter, a matching circuit, etc. are required, increasing the circuit scale of the IC.

Furthermore, if the sampling frequency of the digital signal and the master clock of the system are constant, the above counter can always count a fixed number to determine the pulse width, but in order to support various digital audio types, the sampling frequency alone is sufficient. SHFPCM (7) case 521G (
ff to 48KI (z, for Koybact disk 44, 110 (unlike f, if a digital filter circuit that doubles the sampling frequency is inserted, respectively 64KHff, 96) to G-1, 88.
It changes to 2KHK. Therefore, if the DAC is configured to support the sampling frequency of 96K) NZ,
Although it will be compatible with all digital audio systems, the clock frequency will also differ depending on each system, so it is not possible to obtain the optimal discharge period with a fixed count number in all cases.It is possible to vary the count number depending on the system. Otherwise, it will further increase the circuit size, power consumption, and input terminals, which is not a good idea when considering IC implementation.

Next, consider the digital filter circuit inserted between the digital signal processing circuit and the DAC. A digital filter circuit that doubles the sampling frequency and attenuates the high-frequency characteristics inputs the left and right channel identification signals and digital data at the original sampling frequency output from the digital signal processing circuit, performs calculations, and then doubles the sampling frequency. Digital data corresponding to double the sampling frequency and left and right channel identification signals with twice the sampling frequency are output, but in order to obtain the left and right channel identification signals with twice the sampling frequency, high-speed clock pulses are used to count the original sampling period. , it is necessary to generate a pulse at 1/2 of the count value to create a signal with twice the frequency. S
To support digital audio systems such as HF and CD, a large-scale high-speed counter is required, and LS
It becomes an obstacle in integration.

[Purpose of the invention]

The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to provide a digital recording or transmission system such as a compact disc, a DAT, a 5HFPL'M, and a PGM audio system with different sampling frequencies and master clock frequencies depending on the presence or absence of a digital filter circuit. It is an object of the present invention to provide a digital recording or transmission signal reproducing device which reduces the circuit scale of a digital filter and DAC and obtains an integral capacitance discharge period and a sampling signal period according to the system.

[Summary of the invention]

In order to always obtain the optimal integral capacitance discharge period and the sampling signal period of the sample and hold circuit in response to changes in the sampling frequency input to the DAC and the master clock frequency, the sampling frequency input to the DAC is The half-cycle period of the doubled frequency signal is used as the integral capacitance discharge period and the sampling signal period, respectively.

Can the problem be solved by inputting a signal with twice or four times the sampling frequency to the DAC? It's about trying.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. 7th
In the figure, 109 is a digital signal processing circuit, 115
1 is a digital/L/filter circuit, 110 is an integral type DAC equipped with a discrimination input terminal 119' for determining the presence or absence of a digital filter, 114 is a sample/hold circuit, 115 is a left channel analog/4G signal output terminal,
116 is a right channel analog signal output terminal. 1
12 is the master offset oscillator of the system;
28 is a four clock signal or a frequency-divided clock signal, which is connected to a digital filter circuit 115 and a DACl 10.
is supplied to. 120 is a digital signal processing circuit 1
09 is the 16-pit digital data output, and 125 is the 16-pit digital data output from the digital filter circuit.
This is 6-bit digital data.

The data transmission method may be parallel or serial, but serial requires a data synchronization clock that is synchronized with the data. 117 is an integral capacitance discharge signal of the left channel integrator, 118 is an integral capacitance discharge signal of the right channel integrator, 129 is a left channel integrator output signal, 130 is a right channel integrator output signal, 126 is a left channel integrator output signal, 127 is a sampling signal for the right channel sample and hold circuit. 121 is the first left and right channel identification signal of the sampling frequency output from the digital signal processing circuit; during the @W'' period, the left channel digital data is output, and during the @HI'' period, the right channel digital data is output from 120. be done. 122 was synchronized to the first left and right channel identification signals. 2nd sampling frequency of 4 times
This is the signal. The digital filter circuit is 120, 12
1°122 signal is received, digital data 125 is generated by doubling the sampling signal, and the second signal 122 is 12402 times in phase synchronized with the fifth left and right channel identification signals 124 and 124 divided by 2. It is output to DACllo along with the frequency signal 125. 1
The relationship between the signals 20 to 125 is shown in the time chart of FIG. By doing the above, even if the sampling frequency and master clock frequency change depending on the system, the digital filter circuit can easily convert the fifth left/right identification signal 124 and the same wave number twice that number without using a large-scale counter. You can get 125 signals.

DAello is a digital filter circuit 115 to 12
When receiving the 5124.125 signal and the front stage of the digital filter is inserted, the discrimination terminal 119 is connected to GND.
level, and two sets of integrators are provided to integrate one channel during the forward period of the fifth left/right discrimination signal, that is, during the period when the signal 124 is @LO''.

Integration of the other channel is carried out during the half period of "HI", and 21 sets of current sources are used in common for the two channels. In addition, by setting the integral capacitance discharge period and the sampling period of the subsequent sample and hold circuit to a period of half a cycle of the frequency signal 125, which is twice the left and right identification signal, D
The AC system is designed to easily create an appropriate integral capacitance discharge period and sampling period even if the system sampling period and master quartz frequency change without using a large-scale counter. The operation of the DAC will be explained using the time chart shown in FIG. 121 in Figure 8
,124,125,160,118.127129.1
Numbers 17 and 126 are the same signals explained in FIG. The first output from the 1z1ty digital signal processing circuit
124°125 is a signal input from the digital filter circuit to the DAC. DAC
When the fifth left/right identification signal 124 is "LO", integration is performed using the digital data of the right channel, and when it is "HI", integration is performed using the digital data of the left channel.

The logical product of the signal 124 and the delayed signal of 125 yields 11B, and the logical product of the negative phase signal of 124 and the delayed signal of 125 yields 117. The signal 126 can be obtained by the logical product, and the signal 127 can be obtained by the logical product of the negative phase signal of 125 and the negative phase signal of 124. 118 right channel.

If 117 is the integral capacitance discharge signal of the left channel and the frequency of the clock 128 for counting the integral period is appropriately selected, the integral output waveforms of the left and right channels can be obtained as shown in FIG. 8 at 150 and 129.

As explained above, in the two-parallel integration method in which 16 bits are divided into 8 pits and 8 bits, the 128-bit frequency becomes too high, so it is A parallel integration method was adopted.

127 in the integrated output signals of 150 and 129, respectively.
, 126, hold when the signals 127 and 126 are "LO", and pass through a low-pass filter to obtain left and right channel analog signals.

In addition, as shown in FIG. 9, when a digital filter circuit is not inserted, the discrimination terminal 119 is set to "HI".
"il," corresponds. All the numbers in FIG. 9 are the same as those shown in FIG.

In this case, the DAC includes the first left/right identification signal 121 and the fourth
Since the second signal 122 with twice the frequency is input, the DA
Determine the phase within C, divide the frequency, and use the same signal as the fifth left/right identification signal.
ACg is operated by the signals 121 and 151. The DAC operation in this case will be explained with reference to FIG. The outline of the operation is the same as that shown in FIG.
is obtained from the 151 signal. These periods are twice as long as in the case of Figure 8. Since the quadrature 128 has the same frequency as in FIG. 8, the integration periods 150 and 129 are the same as in FIG. As shown above, the sampling frequency is 1
/2, the integral capacitance discharge period and sample and hold signals corresponding to the sampling frequency can be obtained in the same way within the DAC.

FIG. 11 shows a first left/right identification signal 121 and a second signal 12.
2 to the fifth signal 11S1' is shown. For simplicity, the circuit will be explained using a general-purpose TTL. 151
,152,155 is 74LS74 and 154,15
5 is 74LSOO, 156 is 74LSOO8, 157 is 7
4LS52.158 is 74LSO4. If a digital filter circuit is inserted, the discrimination terminal 119
;Y "LO", and input the signal 124 to 201 and the signal 125 to 2o5, the signal 125 will be output as is to 201 and 206, respectively. If there is no digital filter circuit, the signal of 121 is placed at 201, and the signal of 2o
Input the signal 122 to 5 and select the discrimination terminal 119 Y @H
202 as I''', a four-channel signal (1
If χ is input (may be 28), the signal 155 will be output at the output <154 as shown in the time chart of FIG. 11, and the signal 155 with the determined phase will be obtained at 206. 20
The signal 1 is in each case half the frequency of the signal 206, and the DAC uses these K to determine the integral capacitance discharge period and sample depending on the frequency of the system.

A hold signal can be obtained.

Furthermore, if there is no digital filter circuit, it is possible to double the integration period. In FIG. 9, the clock signal 128 is 1/! Divide the frequency into DAC and input it to DAC.
, ', the output voltage becomes the same and the integration period can be doubled. FIG. 12 shows an operation time chart.

Figure 12 has a similar relationship trap to Figure 8 on the time axis. By doubling the integration period, it is possible to use 1/2 of the ripple frequency, and the distortion factor degradation due to ripple jitter can be reduced to 1if 1/2. The reason for this is that waveform jitter (time axis fluctuation) caused by frequency division using TTL or the like is sufficiently small, so that the amount of jitter hardly changes before and after frequency division. If there is jitter in the clock pulse, there will be jitter in the integration period, leading to deterioration of linearity.If the clock pulse jitter is the same, the lower the clock pulse frequency, the less the effect.

〔Effect of the invention〕

According to the present invention, as explained above, the DAC is configured as a 5-parallel integration system to lower the required 4-way frequency, and the integration capacity can be increased in a period of half a cycle of a signal with a frequency twice that of the left and right channel identification signals input to the DAC. The digital signal processing circuit outputs a left/right identification signal and a quadrupled frequency signal, and the digital filter circuit divides the frequency of the signal into two. By outputting double and quadruple frequency signals 'Y to the DAC and obtaining a branch signal within the DAC if the digital filter circuit is not maximized, the DAD,
It can easily respond to changes in sampling frequency and master clock depending on the presence or absence of digital audio such as DAT and 5IPHy, and the presence or absence of digital filters.
It has the effect of achieving AC■C.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional digital audio playback device, Figure 2 is a block diagram of a conventional 2-parallel integral type DAC, Figure 5 is an explanation diagram of the operation of Figure 2, and Figure 4 is a block diagram of a 5-parallel integral type DAC. Block diagram, Fig. 5 is an operation explanatory diagram of Fig. 4,
FIG. 6 is an explanatory diagram of left and right channel operation of a conventional integral type DAC, FIG. 7 is a principle diagram showing an embodiment of the present invention, FIG. 8 is a diagram showing the present embodiment, and FIG. 10 is an operation of the DAC of the present invention. An explanatory diagram, Fig. 11 is a frequency division circuit diagram of the DAC, and Fig. 12 is a diagram of the present invention D.
It is an explanatory diagram of the operation of AC,'. '109... Digital signal processing circuit 115... Digital filter circuit 110... Integral method DAC 119... Digital filter discrimination input terminal 121.
...First left and right channel identification signal 122...Second signal 124...Fifth left and right channel identification signal 117...
Left channel integral capacitance discharge signal 118...Right channel integral capacitance discharge signal 126...Left channel sample, hold signal 127...Right channel sample, hold signal 4JF Attorney + Akio Keihashi Figure 1 Figure 2 II +7+ 1 Period 10th Figure 11 12゜5th Figure 6 Figure 17 Figure 20 23 'B Figure 9 Figure 31 Figure 10 Figure 11 Figure ttq -1111------------ --------
33 /31

Claims (1)

[Claims] t Converting a two-channel information signal into a digital signal,
Recording on a recording medium such as a disk or tape using optical or magnetic means, reading signals from the recording medium using optical or magnetic means, or receiving signals transmitted using radio waves or other means. A demodulation circuit that obtains a digital signal using a demodulation circuit, a digital signal processing circuit that performs signal processing such as error detection and correction of the digital signal that is the output of the demodulation circuit, and a digital signal processing circuit that converts the digital signal that is the output of the digital signal processing circuit into an analog/4G signal. In a digital audio playback device consisting of a digital/analog converter, the digital/analog converter divides the digital signal that is the output of the digital signal processing circuit into a plurality of sets in units of bits, and calculates the number of sets. Two sample circuits are provided for separately conducting and interrupting the weighted electric light source and the output of the current source A-F, which is 90% of dazzling, to the next stage. , the current source is integrated by a first integrator of the two integrators for a period corresponding to the digital signal in one half period of a left and right channel identification signal of a sampling frequency that operates the digital signal processing circuit. At the same time, the output of the second integrator is conducted to the second sampling circuit connected to the next stage during the half cycle of the frequency signal twice that of the left and right channel identification signals, and the other half cycle of the frequency signal twice the left and right channel identification signals is conducted. The charge in the integration capacitor of the second integrator is discharged, and the current source is integrated by the second integrator for a period corresponding to the digital signal in the other half period of the left and right channel identification signal of the sampling frequency. At the same time, the output of the first integrator is conducted to the first sampling circuit connected to the next stage during the half cycle of the double frequency signal, and the first integration is performed during the other half cycle of the double frequency signal. The digital to analog converter is driven by a left and right channel identification signal at a sampling frequency and a frequency signal twice as high as the left and right channel identification signals at the sampling frequency so as to discharge the charge in the integrating capacitor of the converter. Digital audio playback device. 2. In claim 1, there is provided a digital circuit that doubles the sampling frequency between the digital signal processing circuit and the digital/analog converter, and performs digital arithmetic processing on unnecessary signals and interrupts the processing; A filter circuit χ is provided, which outputs a signal having a frequency twice as high as the sampling frequency of the system before passing through the digital filter as a left and right channel identification signal of the sampling frequency that drives the digital/analog converter, and also converts the digital/analog converter. A signal with a frequency four times the sampling frequency of the system is outputted from the digital filter as a frequency signal twice the left and right channel identification signal of the sampling frequency that drives the digital converter, and a signal with a frequency four times the sampling frequency of the system is outputted from the digital filter to drive the digital/analog converter. 1. A digital audio playback device, characterized in that a left and right channel identification signal having a system sampling frequency and a signal having a frequency four times the system sampling frequency are outputted from a signal processing circuit to drive the digital filter. s, e Claims 1 or 2, wherein the digital/analog converter is provided with a divider and a digital/filter discrimination input terminal, and the divider is supplied with a frequency signal four times the sampling frequency of the system. In addition, the digital filter discrimination input terminal drives the integrator sampling circuit at a frequency four times that of the vaginal divider input when there is a digital filter, and when there is no digital filter, the divider A digital audio playback device characterized in that the integrator/sampling circuit is driven at a frequency twice the output of the integrator/sampling circuit.