JPS60224325A - Three-state output circuit - Google Patents

Abstract

PURPOSE:To suppress easily the occurrence of an intermediate level and a through current by providing two transistors TRs having opposite polarities whose sources and drains are connected to gates of two complementary output TRs. CONSTITUTION:When a signal A is ''1'' and a signal B is changed from ''1'' to ''0'', outputs O1 and O2 of an NAND gate 1 and an NOR gate 2 are changed from ''0'' to ''1'' after a prescribed time. A prescribed time after this change, a gate potential O2' of a TrQN reaches thresholds of an inverter IV5 and the TrQN. At this time, the IV5 is changed from ''1'' to ''0'', and therefore, a P- channel TrQP' is turned on, and a potential O1' becomes ''1'' quickly, and the TrQP is turned off. Thereafter, though the N-channel TrQN is turnen on, the intermediate level does not appear in an output terminal O3 and the through current is not generated because the TrQP is turned off. When the signal A is changed from ''1'' to ''0'', the intermediate level and the through current are not generated because Trs QN and QP are changed to the turn-off state.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a three-state output circuit having complementary field effect transistors as constituent elements.

(Prior art) Conventionally, 3-state output circuits have been used in bus circuits, etc. because they have advantages such as being able to connect multiple gate outputs at the same time and having extremely low leakage current in a high impedance state. .

FIG. 1 is a schematic diagram of an example of a conventional three-state output circuit.

This circuit is a NAND game)1. NO 几 Gate 2゜Inverter 3. It is composed of a transistor consisting of a P-channel transistor QF and a channel transistor Ql. This circuit takes three states depending on the values of input signals A and B: @1': "" Q ml, "" floating. The truth table is shown in Table 1.

Table 1 When this three-state output circuit is integrated on a semiconductor substrate, resistance and capacitance appear in each part.

FIG. 2 is a schematic diagram of a three-state output circuit integrated on a semiconductor substrate.

As shown in Figure 2, NAND gate 1.2 and 0MO8
) between transistors Qp and QN, respectively.
a2. The capacitance Ci,C, appears. Let's explain the effects of this resistance and Chazuke on signal transmission.

FIG. 3 is an operation timing diagram when the output signal of the NAND gate of the three-state output circuit shown in FIG. 2 is larger than the delay of the NOR gate output signal.

After the first confidence A is a logic value @1' (Vcc level) and the second confidence signal 4B changes from "1" to a logic value "0" (ground level), the output signal is transferred to the output signal 02 at time tA1. is 1
Changes from “0” to “1”.P channel transistor Q
A potential indicated by 0'5 appears at the gate electrode of P, and a voltage potential indicated by O12 appears at the gate electrode of the N-channel transistor QN. O12 is the second signal B @1" to 0"
After changing to , the threshold voltage of the transistor QP is reached after the time ti11, and then it becomes the Vcc level, so that the transistor OP is turned off after the time tB1.

After the second confidence B changes from 11'' to 10'', O12 reaches the threshold voltage of the transistor QN after the to1 time, and then becomes the Vcc level, so the transistor Qski turns on after the to1 time.

As mentioned above, this operation timing is delayed by the resistor R1 and the capacitor C1. Since this is a case where the delay due to the capacitor C2 is greater, t,1 is greater than tol. Therefore, for a period of tBl tol, transistor QP,
Since QN are both turned on, an intermediate level determined only by the sizes of transistors QP and QN is generated at output terminal 03. Normally, the transistors Qp and QN are designed to have the same current capacity, so -;
A value of about cc is an intermediate level. Also, this tBl
During the period tcl, a current (referred to as a through current) flowing through the transistors QP-QN is generated.

When the second trust B changes from @0” to “1”, the signal 01
+o= Changes from "l#" to "0" after n time tD1 time. O12 becomes reliable B due to the influence of resistor 1 capacitor C1.
After 1 changes from 10# to 11#, it reaches the threshold voltage of the upper transistor QP at time t11 and then becomes the ground potential, so after the second signal BI changes from @o# to II I H, tg, time Until then, the transistor QP is in the off state, and then it is in the on state. On the other hand, O12 due to the influence of resistance R2 + capacitance C2 after signal B changes from 1" to 11m,
After the trt time, the threshold voltage of the transistor QN is reached, and then it becomes the ground potential, so the transistor Q remains active until the tF1 time.
N is in the on state and then in the off state. tBl, te
For the same reason as mentioned in section 1, tut is larger than tFl, and since there is no period in which both transistors QP and QN are turned off, there is no intermediate level at the output terminal 03, and no through current is generated.

If the delay in signal transmission is opposite to the example shown in FIG.
FIG. 4 shows an operation timing diagram when the delay of O12 is greater than the delay n of O12 caused by the resistor R1 and capacitor C1 connected to O1. In this example, when the second signal -@-B changes from 10'' to mim, an intermediate level is present at the output p terminal 03, and a through current is generated, but this operation is the same as the operation shown in Figure 3. The same is true.

The intermediate level appearing at output terminal 03 is
In addition, the through current increases the instantaneous power consumption of the integrated circuit, raises the level of the ground terminal of the integrated circuit, and reduces the operating margin.

(Object of the Invention) The object of the present invention is to provide a three-state circuit that eliminates the above drawbacks, easily suppresses the occurrence of intermediate levels and through current, prevents malfunction costs, and reduces power consumption. It's about doing.

(Structure of the Invention) A three-state output circuit of the present invention includes a NAND gate that inputs a first double signal and a second signal, a first inverter that inverts the first signal, and a first inverter that inverts the first signal. A NOR gate inputting the output signal of the first inverter and the second signal; a first transistor of a conductivity type, and a gate of the NOR transistor;
a second transistor of an opposite conductivity type connected to the output terminal of the gate, a source connected to the other potential source of the power supply, and a drain connected to the output terminal; and a second inverter for inverting the output signal of the NAND gate. and a third inverter that inverts the output signal of the NOR gate, and a source (or drain) whose gate is connected to the third inverter.
a third transistor of one conductivity type, which is connected to one potential source of the power supply and whose drain (or source) is connected to the gate of the first transistor; and a third transistor whose gate is connected to the second inverter and whose source (or and a fourth transistor of an opposite conductivity type, the drain (or source) of which is connected to the other potential source of the power supply, and the drain (or source) of which is connected to the gate of the second transistor.

(Example) Embodiments of the present invention will be briefly described with reference to the drawings.

FIG. 5 is an isometric diagram of one embodiment of the present invention.

In this example, - conductivity type is P type, and opposite conductivity type is N type.
Explain as a type.

This embodiment includes a NAND gate 1 which inputs a first signal A and a second signal B, and a first NAND gate which inverts the first signal -SA.
an inverter 3, a NOR gate 2 inputting the output signal of the first inverter 3 and a second signal B, and a gate with NA
ND A first transistor QP of P-channel type connected to the output terminal of gate 1, whose source is connected to the potential source Vcc of the power supply, and whose drain is connected to the output terminal 03, and whose gate is connected to the output terminal of NOR gate 2. a second N-channel transistor QN whose source is connected to the other potential source (ground) of the power supply and whose drain is connected to the output terminal 03;
D Second inverter 4 that inverts the output signal of gate 1
and a third inverter 5 for inverting the output signal of the NOR gate 2, whose gate is connected to the third inverter 5 and whose north (or drain) is connected to a potential source Vcc whose type temperature is constant.
a P-channel type third transistor Q'P whose drain (or source) is connected to the gate of the first transistor QP, and whose gate is connected to the second inverter 4 and whose source (or drain) is connected to the power source. and an N-channel type fourth transistor QN/ connected to the other potential source (ground) and having its drain (or source) connected to the gate of the second transistor QN. Resistance R1, R2
, capacitors C1 and C2 are resistors and capacitors that appear when the three-state output circuit of the present invention is formed on a semiconductor substrate, and are not purposely created and connected.

The threshold voltages of the second and third inverters 4.5 are respectively the same as the first. It is set to be equal to the threshold voltage of the second transistors QP and QN. This can be achieved by appropriately setting the size of the transistor constituting the inverter.

Next, the operation of this embodiment will be explained.

FIG. 6 is an operation timing diagram when the delay of the output signal of the NAND gate of the embodiment shown in FIG. 5 is greater than the output signal delay of the N0fL gate.

It goes without saying that the delay n of each output signal of the NAND gate and the NOR gate is caused by the resistance 1+fL2 and the capacitance C, , C,.

After the first signal is "1m" and the second signal B changes from "l" to "0", after time tA2, both 0□ and 02 are
0" to '12. Q/2 is the third value after time t02.
The threshold voltage of the inverter 50 reaches the threshold voltage of the second transistor QN. At this time, the inverter 5 changes from "l" to "O#", so the third P-channel transistor Q, / turns on, and the signal 01' rapidly changes to 1.
”, and the first transistor Q is turned off.

At time to2, the second transistor Qs is in the on state, but the first transistor QP is in the off state as described above, so no intermediate level appears at the output terminal 03, and the N reverse current does not occur either.

The first credence A is "1" and the second signal B is 10"
When the signal B changes from "0#" to "11" in Figure 3, the operation is the same as when the second signal B changes from "0#" to "1", and no intermediate level appears at the output terminal 03, and the through current does not occur either.

When the first signal A changes from "1" to 0'', the transistors QN and Qp both try to change to the OFF state, so that no intermediate level or through current occurs.

FIG. 7 is an operation timing diagram when the delay of the output signal of the INOR gate of the embodiment shown in FIG. 5 is greater than the delay of the output signal of the NAND gate.

After the first signal A is “l#” and the second signal B changes from @1m to “0”, O1,0, after time tA3 is “O”.
After the change of the second signal -@B, O12 reaches the threshold voltage of the second inverter 4 and the first transistor Q after time tB3, and then the first transistor QP changes from "1" to "1". The output of the second inverter 4 is '''l# until time tB3, so the N-channel type fourth
The transistor QN' is in the on state and the transistor 02' is "O".
becomes #. Since the transistor Qs' is turned off after time tBJ, 02' reaches the threshold voltage of the transistor QN after a delay n1 caused by the resistor R2 and capacitor C2 after time t03. Therefore, the transistor QpH remains on until time ta3, and then turns off.
It remains off until time d to3, and then turns on.

As already mentioned, since tos is larger than tf13, neither transistors QN nor QP are turned on. Therefore,
No intermediate level appears at the output terminal 03, and no through current occurs.

After the second signal B changes from “0” to “1”, tD3
After time ol, o changes from @1'' to 10#, and after time 3 layer O12 becomes inverter 4.transistor Qp
reaches the threshold voltage of Qpn, and the transistor Qpn turns off. Since the output of the inverter 4 changes from 10'' to 11, the transistor QN' becomes off, the signal 02' becomes "O", and the transistor QN becomes off. That is, 01' reaches the threshold voltage of the transistor QP, When transistor QP turns on, transistor QN turns off, so an intermediate level appears at output terminal 03.
Therefore, no through current occurs.

(Effects of the Invention) As explained in detail above, the present invention provides a three-state output that suppresses the occurrence of intermediate levels and through current, prevents malfunctions, and reduces power consumption. The effect that a circuit can be obtained is obtained.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of an example of a conventional 3-state output circuit, and Figure 2 is a schematic diagram of the 3-state output circuit shown in Figure 1 when the output circuit is formed on a semiconductor substrate. Figure 3 is an operation timing diagram when the delay in the output principle of the NAND gate of the 3-state output circuit shown in Figure 2 is greater than the delay in the output principle of the ENOFL gate. The delay of the output signal of the NOR gate of the output circuit is NA.
Greater than the delay of the output signal of the ND gate: An operation timing diagram of the 4-coupled case, FIG. 5 is an isometric circuit diagram of one embodiment of the present invention f11, and FIG. FIG. 7 is an operation timing diagram when the delay of the output signal is larger than the delay of the output signal of the NOR gate.
FIG. 6 is an operation timing diagram when the delay of the output signal of the gate is greater than 1; l...NAND gate, 2...N0I
(Gate, 3, 4. 5... Inverter, A
...First signal, B...Second signal,
cl, c2...capacity, ■...tan J
tli style, 03... Output terminal, QPI QP
'...P-channel transistor, QN, Q
N'...N-channel transistor, R1, R
2...Resistance, VCC...Power supply. −・・−Representative Patent Attorney Susumu Uchihara, −゛, 100 yen 2 figures 40 yen

Claims (1)

[Claims] a NAND gate that receives a first signal and a second signal; a first inverter that inverts the first signal; and a NAND gate that receives the output signal of the first inverter and the second signal. -1-, a first transistor of one conductivity type whose gate is connected to the output terminal of the NAND gate, whose source is connected to the -1 potential source of the power supply, and whose drain is connected to the output terminal; a second transistor of an opposite conductivity type connected to the output terminal of the NOR gate, a source connected to the other potential source of the power supply, and a drain connected to the output terminal; and a second transistor for inverting the output signal of the NAND gate.
an inverter, a third inverter for inverting the output signal of the NOR gate, a gate connected to the third inverter, a source (or drain) connected to the -1 potential source of the power supply, and a drain (or drain) connected to the -1 potential source of the power supply. ) is connected to the gate of the first transistor, a third transistor of one conductivity type, and the gate is connected to the second inverter, the source (or drain) is connected to the other potential source of the power supply, and the drain ( or a fourth transistor of an opposite conductivity type, the source of which is connected to the gate of the second transistor.