JPS60223270A - Automatic gain control circuit - Google Patents

Automatic gain control circuit

Info

Publication number
JPS60223270A
JPS60223270A JP7910984A JP7910984A JPS60223270A JP S60223270 A JPS60223270 A JP S60223270A JP 7910984 A JP7910984 A JP 7910984A JP 7910984 A JP7910984 A JP 7910984A JP S60223270 A JPS60223270 A JP S60223270A
Authority
JP
Japan
Prior art keywords
voltage
agc
transistor
base
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7910984A
Other languages
Japanese (ja)
Other versions
JPH0312830B2 (en
Inventor
Hideo Imaizumi
英雄 今泉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP7910984A priority Critical patent/JPS60223270A/en
Publication of JPS60223270A publication Critical patent/JPS60223270A/en
Publication of JPH0312830B2 publication Critical patent/JPH0312830B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate the need to prepare two AGC circuits independently of the original one by securing a peak AGC circuit function to both NTSC and PAL systems and then a mean value AGC circuit function to an SECAM system with just a single AGC circuit. CONSTITUTION:The 1st and 2nd switches SW2 and 19 are turned on in an NTSC or PAL broadcast reception mode, and a modulated signal Vi is applied to an input terminal 25. The base of a control transistor TR27 is set at an earth potential by the SW2 and kept cut off. Therefore a signal VA underwent the wave detection through a wave detection circuit 23 is supplied to the base of a TR12 of a differential pair 14 via a TR10 for active filter. The collector potential of the TR12 varies in response to the signal VA, and the outut of the TR12 is supplied to the base potential of a TR7. A capacitor 22 is connected to a terminal 26. Thus a current I1 flows to the capacitor 22 when the voltage lower than the voltage V'C set at a point C is applied to the base of the TR12. Then the capacitor 22 is quickly charged. While I1=0 is satisfied when the voltage applied to the base of the TR12 is kept higher than the V'C. Therefore the AGC voltage VB is produced as the peak AGC voltage based on the V'C set at the point C.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は、テレビ受像機の中間周波増幅(IF)系の自
動利得制御回路に係り、特にカラー・テレビ受像機にお
ける音声IF系の同制御回路に関する。
Detailed Description of the Invention (a) Industrial Application Field The present invention relates to an automatic gain control circuit for an intermediate frequency amplification (IF) system of a television receiver, and particularly to an automatic gain control circuit for an intermediate frequency amplification (IF) system of a color television receiver. Regarding control circuits.

(ロ)従来技術 一般にカラーテレビ受像機においては、各種方式部ちN
TSC,PAL及びSECAM方式が各国で採用されて
おり、例えばNTSC方式及びPAL方式の両放送を受
像できるカラーテレビ受像機が提案されている。
(b) Prior art In general, in color television receivers, various system parts and N
The TSC, PAL, and SECAM systems have been adopted in many countries, and for example, color television receivers that can receive both NTSC and PAL broadcasts have been proposed.

その−例として特開昭58−141092号にPAL方
式及びNTSC方式を判別する技術が示されているが、
これはただ単に受信した方式に応じて受像回路を自動的
に切、換える方式自動切換回路が開示されているだけで
ある。
As an example, Japanese Patent Laid-Open No. 58-141092 discloses a technique for distinguishing between PAL and NTSC systems.
This merely discloses an automatic system switching circuit that automatically switches the image receiving circuit according to the received system.

一方同カラーテレビ方式にはNTSC,PAL及びSE
CAM方式の中で、NTSC及びPAI。
On the other hand, the same color television system includes NTSC, PAL and SE.
Among the CAM systems, NTSC and PAI.

方式は音声がFM方式、SECAM方式ではAM方式で
あり、これらのIF回路は各々別個に必要となり、特に
自動利得制御として各々ビー・り(先頭値)AGCと平
均値AGCを採用しなり゛ればならなかった。
The audio system uses the FM system, and the SECAM system uses the AM system, and each of these IF circuits is required separately, and in particular, beagle (leading value) AGC and average value AGC are used as automatic gain control. I had to.

(ハ)発明の目的 本発明はNTSC及びPAL方式に対してはピークAG
Oを、SECAM方式に対しては平均値AGO回路とし
て動作させ得るようにAGC電圧を導出することを目的
とする。
(c) Purpose of the invention The present invention provides peak AG control for NTSC and PAL systems.
The purpose of this invention is to derive an AGC voltage so that O can be operated as an average value AGO circuit for the SECAM system.

に)発明の構成 本発明は、入力信号が加えられる入力トランジスタと、
該入力トランジスタの出力側が第1のトランジスタに接
続されると共に第2のトランジスタのペースが分圧回路
に接続された一対のトランジスタより成る差動増幅器と
、該差動増幅器の第1又は第2のトランジスタの各々の
出力負荷端に設けられた第1の分路及び−第2の分路と
、前記第1の分路に接続された出力端子及び入力端子間
に接続した積分回路と、前記第2の分路の一端とアース
間に接続した開閉手段と、前記出力端子に接続されたA
GC制御回路とより成り、前記開閉手段の開閉により前
記出力端子よりピークAGC電圧又は平均値AGC電圧
を前記AGC制御回路に印加する構成である。
B) Structure of the Invention The present invention provides an input transistor to which an input signal is applied;
a differential amplifier consisting of a pair of transistors in which the output side of the input transistor is connected to a first transistor and the pace of the second transistor is connected to a voltage dividing circuit; a first shunt and a second shunt provided at the output load ends of each of the transistors; an integrating circuit connected between the output terminal and the input terminal connected to the first shunt; A switching means connected between one end of the shunt No. 2 and the ground, and a switching means connected to the output terminal A.
A GC control circuit is configured to apply a peak AGC voltage or an average value AGC voltage to the AGC control circuit from the output terminal by opening and closing the opening/closing means.

(ホ)実施例 図面に従って本発明を説明すると、第1図は本発明の自
動利得制御回路の基本回路図、第2図は同回路の一実施
例を示す回路図、第3図は各点波形図である。
(E) Embodiment To explain the present invention according to drawings, FIG. 1 is a basic circuit diagram of an automatic gain control circuit of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the same circuit, and FIG. 3 is a circuit diagram showing each point. FIG.

第1図において、(1)はAGC制御回路、(2)は第
1のスイッチ、(3H4)は第1の分路として設けたカ
レントミラー(句を構成する第1及び第2のトランジス
タ、(6)(力は第2の分路として設けたカレントミラ
ー(J8を構成する第3及び第4のトランジスタ、(9
)は制御トランジスタ、tiltまアクティブフィルタ
Iを構成する入力トランジスタ、u針■は差動対0を構
成する差動用トランジスタ、H+1抵抗(161(17
>C1秒より成る第1の分圧回路、(tit文第2のス
イッチ、(4)は定電流源、シυ(2壜1積分用コンデ
ンサ、(2)は検波回路、(24)は入力抵抗、(ハ)
(26)は各々入力端子及び出力端子を示す。
In FIG. 1, (1) is an AGC control circuit, (2) is a first switch, (3H4) is a current mirror provided as a first shunt (the first and second transistors forming a clause, 6) (The force is transmitted through a current mirror provided as a second shunt (the third and fourth transistors forming J8, (9
) is the control transistor, the input transistor that constitutes the tilt active filter I, the u needle ■ is the differential transistor that constitutes the differential pair 0, and the H+1 resistor (161 (17
>C1 second voltage divider circuit, (tit statement second switch, (4) is a constant current source, υ (2 bottles 1 integrating capacitor, (2) is a detection circuit, (24) is an input Resistance, (c)
(26) indicate an input terminal and an output terminal, respectively.

第2図において、(4)(5)はダーリントン接続され
第1図における第1のトランジスタ(4)に相当するト
ランジスタ、シeは電流供給用トランジスタ、121(
7)は定電流トランジスタ、I3卸s(至)はバイアス
回路(ロ)を構成する抵抗及びダイオードである。
In FIG. 2, (4) and (5) are Darlington-connected transistors corresponding to the first transistor (4) in FIG.
7) is a constant current transistor, and I3 is a resistor and diode that constitute a bias circuit (b).

次に第1図を用いて本発明を説明すると、先ず平均値型
によるAGC電圧を導出するとき、即ち音声信号がAM
方式のSRCAM放送受信時、第1のスイッチ(2)及
び第2のスイッチQlをオフにしておくと入力端子(ハ
)に印加される入力信号■iが第3図(イ)又は(ロ)
に示すようにAM波は信号(キャリア)の大小によって
変化する。検波回路(ハ)の出力(vA)は信号(キャ
リア)の大小に変化する復調された信号が第3図(ハ)
又はに)に示すように検波回路(ハ)の出力側(現われ
、入力抵抗(ハ)に加わる。
Next, the present invention will be explained using FIG. 1. First, when an average value type AGC voltage is derived, that is, when an audio signal
When receiving SRCAM broadcasting using the SRCAM method, if the first switch (2) and the second switch Ql are turned off, the input signal ■i applied to the input terminal (c) will be as shown in Figure 3 (a) or (b).
As shown in the figure, the AM wave changes depending on the size of the signal (carrier). The output (vA) of the detection circuit (c) is a demodulated signal that changes in magnitude of the signal (carrier) as shown in Figure 3 (c).
As shown in (2), it appears on the output side of the detection circuit (C) and is applied to the input resistor (C).

このとき前記第2のスイッチillがオフであるから分
圧回路によって得た分圧電圧(V、)により差動対0の
一方のトランジスタα漕がオンになる。
At this time, since the second switch ill is off, the divided voltage (V,) obtained by the voltage dividing circuit turns on the transistor α of the differential pair 0.

、:、: テ!PK:(ll(17)(1M値ヲR1、
Rt 、 R3トt ルと、vc=v、c (R2+R
,)/(RI+R2+R,)となっているので、前記ト
ランジスタa暗1オン、(15はオフとなってトランジ
スタ(450ベースはほぼアース電位となって該トラン
ジスタ(4′)はオンになり、これと同時に制御トラン
ジスタ07)のペース電位も高く、従って該制御トラン
ジスタ(27)もオンとなって、電流工、二■、から、
出力端子(261における電圧(V、)は差動対Qll
の一方のトランジスタ(131のペース電位(VC)を
中心にして、前記電圧vAが抵抗c39及びコンデンサ
an123によって積分された値(平均値)として直流
分が取出されるうこのとき大振幅時は第3図(イ)及び
(ハ)、小振幅時第3図(ロ)及びに)に示す波形とな
る。
, :, : Te! PK: (ll (17) (1M value wo R1,
Rt, R3 tor, vc=v, c (R2+R
,)/(RI+R2+R,), so the transistor a dark 1 is on, (15 is off and the transistor (450) is at almost ground potential and the transistor (4') is on. At the same time, the pace potential of the control transistor 07) is also high, so the control transistor (27) is also turned on, and from the current
The voltage (V,) at the output terminal (261) is the differential pair Qll
When the voltage vA is integrated by the resistor c39 and the capacitor an123 and the DC component is taken out as a value (average value) centered on the pace potential (VC) of one transistor (131), when the amplitude is large, the When the amplitude is small, the waveforms are as shown in FIGS. 3(a) and 3(c), and as shown in FIGS. 3(b) and 2).

第3図(ハ)及、びに)における破線は前述の平均値と
して現われるAGC電圧のレベルを示す。
The broken lines in FIGS. 3(c) and 3(c) indicate the level of the AGC voltage appearing as the above-mentioned average value.

次に本発明回路をピーク(先頭値)型によるAGC電圧
を導出するとぎ、即ち音声信号がFM方式のNTSC又
はPAL放送受信時、第1のスイッチ(2)及び第2の
スイッチ四をオンにする。入力端子Q1には第3図(ホ
)に示すように変調された信号■iが加わる。
Next, when the circuit of the present invention is used to derive the peak (leading value) type AGC voltage, that is, when the audio signal is an FM system NTSC or PAL broadcast, the first switch (2) and the second switch (4) are turned on. do. A modulated signal ■i is applied to the input terminal Q1 as shown in FIG. 3(E).

このとき制御トランジスタシηのペースは、第1のスイ
ッチ(2)がオンとなっているため、アース電位となつ
てカットオフになっており、従って前記検波回路(ハ)
にて検波された信号(V、)は、アクティブフィルタ用
のトランジスタ(10)を介して差動対Qj)のトラン
ジスタa2のベースに加わり、前記信号vAK:応じて
トランジスタa4のコレクタ電位が変化し、トランジス
タ(7)のペース電位に前記トランジスタα2の出力が
加わる。ここで端子弼にはコンデンサ0りが接続されて
いるため、前記0点の電圧■。
At this time, since the first switch (2) is on, the pace of the control transistor η is at the ground potential and is cut off, so that the pace of the control transistor η is cut off.
The signal (V,) detected at is applied to the base of the transistor a2 of the differential pair Qj) via the active filter transistor (10), and the collector potential of the transistor a4 changes accordingly. , the output of the transistor α2 is added to the pace potential of the transistor (7). Here, since a capacitor 0 is connected to the terminal 2, the voltage at the 0 point is ■.

’a ”” VccRt / (R+ + R2)にな
って、該電圧■。より低い電圧がトランジスタ(14の
ベースに加わったとき、電流■。が前記コンデンサ(2
21に流れて急速に充電される。
'a '''' VccRt / (R+ + R2), and the voltage ■. When a lower voltage is applied to the base of the transistor (14), the current ■.
21 and is rapidly charged.

一方前記トランジスタ@のベースに加わる電圧が前記電
圧ぬより高いときI、=0 となる。従ってAGC電圧
(Vl)は0点の電圧(V、)を基準にして同期先端で
AGCがかかるようなピークλGC電圧として現われる
ことになる。
On the other hand, when the voltage applied to the base of the transistor @ is higher than the voltage N, I=0. Therefore, the AGC voltage (Vl) appears as a peak λGC voltage such that AGC is applied at the synchronization tip with reference to the zero point voltage (V, ).

なお前記0点の電圧(VL )が平均値AGC電圧と等
しいと、検出レベルが小さいため釦、前記第2のスイッ
チ四をオンにして、前記0点の基準電位を変化させてい
る。
Note that when the voltage (VL) at the 0 point is equal to the average AGC voltage, the detection level is small, so the button and the second switch 4 are turned on to change the reference potential at the 0 point.

次に第2図は第1図の具体的な構成を示す一実施例で、
定電流源(イ)を抵抗ell)3Lダイオード(至)及
びトランジスタ(至)で構成してあり、平均値AGC電
圧を得る場合は、前述の第1図と同様に第1のスイッチ
(2)及び第2のスイッチ11をオフにしておき、I、
 = I、に設定してあり、入力抵抗(至)及びコンデ
/サシ1)(社)より成る積分回路で検波出力が積分さ
れた平均値の電圧が導出される。
Next, FIG. 2 is an example showing the specific configuration of FIG. 1,
The constant current source (a) is composed of a resistor (ell), a 3L diode (to), and a transistor (to), and when obtaining the average value AGC voltage, the first switch (2) is used as in Fig. 1 above. and the second switch 11 is turned off, I,
= I, and the average value of the voltage is derived by integrating the detection output with an integrating circuit consisting of an input resistor (total) and a Conde/Sashi 1) (Company).

このとき電流工、はほぼ零(II ” I2 >> I
s )となっている。
At this time, the electrical current is almost zero (II ” I2 >> I
s).

一方ピーク型A cx c 電圧を導出するときは、第
1のスイッチ(2)及び第2のスイッチIをオンに設定
するので、前述の第1図と同様に0点の電圧(Vc )
より低い電圧が差動トランジスタu2のベースに加わっ
たとき、電流■1はコンデンサー4に流れ込み、急速に
充電する。これとは逆に前記トランジスタa2のベース
に加わる電圧が前記電圧■。
On the other hand, when deriving the peak type A cx c voltage, the first switch (2) and the second switch I are set to ON, so the voltage at the 0 point (Vc
When a lower voltage is applied to the base of differential transistor u2, current 1 flows into capacitor 4 and charges it quickly. On the contrary, the voltage applied to the base of the transistor a2 is the voltage (2).

より高いときは、I、=0 となって、電流工、がコン
デンサ四に流れ込む。
When it is higher, I=0, and the current flows into capacitor 4.

ところがこのときの電流工、は前述の如く微小電流化さ
れているため、はぼ零となっているので、0点の電圧(
Vc)を基準にして同期先端でAGC電圧が現われる。
However, since the electric current at this time is reduced to a minute current as mentioned above, it is almost zero, so the voltage at the 0 point (
The AGC voltage appears at the synchronization tip with reference to Vc).

なお前述の説明で、前記AGC制御回路<1)の入力イ
ンピーダンスは充分太きいものとする。
In the above description, it is assumed that the input impedance of the AGC control circuit <1) is sufficiently large.

(へ)発明の効果 本発明の自動利得制御回路によれば、テレビ放送信号に
おける音声変調方式がFM即ちNTSC及びPAL方式
と、AM即ちSECAM方式のいずれに対しても、平均
値AGCとピークAGC電圧を切換え手段により導出で
き、特に第2図の実施例をIC化した場合、該ICを併
用できるので、従来のように各々のAGC方式に適合す
るICを用意することなく、所期の目的が達成できる。
(F) Effects of the Invention According to the automatic gain control circuit of the present invention, the average value AGC and the peak AGC can be adjusted regardless of whether the audio modulation method in the television broadcast signal is FM, that is, NTSC and PAL method, or AM, or SECAM method. The voltage can be derived by a switching means, and especially when the embodiment shown in FIG. can be achieved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の自動利得制御回路の基本回路図、第2
図は同回路の一実施例を示す回路図、第3図は各点波形
図である。 主な図番の説明 (1)・・・AGC制御回路、 (2)・・・第1のス
イッチ、(紡8)・・・カレントミラー、 (9)・・
・制御トランジスタ、I・・・アクティブフィルタ、 
σ\・・差動対、 01・・・第2のスイッチ、 Qυ
@・・・積分用コンデンサ、(231・・・検波回路。 出願人 三洋電機株式会社 外1名 代理人 弁理士 佐 野 靜 夫
Figure 1 is a basic circuit diagram of the automatic gain control circuit of the present invention;
The figure is a circuit diagram showing one embodiment of the same circuit, and FIG. 3 is a waveform diagram at each point. Explanation of main drawing numbers (1)...AGC control circuit, (2)...First switch, (Spinning 8)...Current mirror, (9)...
・Control transistor, I...active filter,
σ\...Differential pair, 01...Second switch, Qυ
@...Integration capacitor, (231...Detection circuit. Applicant: Sanyo Electric Co., Ltd. and 1 other representative: Patent attorney: Yasuo Sano

Claims (1)

【特許請求の範囲】[Claims] (1)入力信号がペースに加えられる入力トランジスタ
と、該入力トランジスタの出力側が第1のトランジスタ
に接続されると共に・第2のトランジスタのベースが分
圧回路に接続された一対のトランジスタより成る差動増
幅器と、該差動増幅器の第1又は第2のトランジスタの
各々の出力負荷端に接続された第1の分路及び第2の分
路と、前記第1の分路に設けられた出力端子及び入力端
子間に接続した積分回路と、前記第2の分路の一端とア
ース間に接続した開閉手段と、前記出力端子に接続され
たAGC制御回路とより成り、前記開閉手段の開閉によ
り前記出力端子よりピークAGC電圧又は平均値AGC
電圧を前記AGC制御回姑に印加することを特徴とした
自動利得制御回路。
(1) An input transistor to which an input signal is applied to the pace, and a pair of transistors, the output side of which is connected to a first transistor, and the base of a second transistor connected to a voltage divider circuit. a dynamic amplifier, a first shunt and a second shunt connected to the output load end of each of the first or second transistor of the differential amplifier, and an output provided in the first shunt. It consists of an integrating circuit connected between the terminal and the input terminal, a switching means connected between one end of the second shunt and the ground, and an AGC control circuit connected to the output terminal, and the switching means Peak AGC voltage or average value AGC from the output terminal
An automatic gain control circuit characterized in that a voltage is applied to the AGC control circuit.
JP7910984A 1984-04-19 1984-04-19 Automatic gain control circuit Granted JPS60223270A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7910984A JPS60223270A (en) 1984-04-19 1984-04-19 Automatic gain control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7910984A JPS60223270A (en) 1984-04-19 1984-04-19 Automatic gain control circuit

Publications (2)

Publication Number Publication Date
JPS60223270A true JPS60223270A (en) 1985-11-07
JPH0312830B2 JPH0312830B2 (en) 1991-02-21

Family

ID=13680731

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7910984A Granted JPS60223270A (en) 1984-04-19 1984-04-19 Automatic gain control circuit

Country Status (1)

Country Link
JP (1) JPS60223270A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4812908A (en) * 1985-10-21 1989-03-14 U.S. Philips Corporation Automatic gain control circuit having a control loop including a current threshold circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4812908A (en) * 1985-10-21 1989-03-14 U.S. Philips Corporation Automatic gain control circuit having a control loop including a current threshold circuit

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JPH0312830B2 (en) 1991-02-21

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