JPS60223174A - Semiconductor photoelectronic compound element - Google Patents

Abstract

PURPOSE:To produce the titled semiconductor photoelectronic compound element with high performance and excellent yield by a method wherein at least one layer of multiple epitaxial semiconductor is made into a semiinsulating semiconductor layer to form an impurity introducing region reaching the depth at least exceeding the semiinsulating semiconductor layer. CONSTITUTION:A tin doped n type InP 12, an undoped InGaAsP 13, another tin doped n type InP 14, a cobalt doped semiinsulating InP 15 and the other InP 16 are successively liquid-epitaxially grown (LPE) on a (001) plane of tin doped n type InP substrate 11. Firstly a p type zinc diffused region 17 (oblique lined) is formed. Secondly another p type diffused region 18 is formed between a photodiode 27 and an FET26. This p type diffusion region 18 around 10-20mum wide and around 400mum long reaching the semiinsulating InP 15 but not penetrating the same fills the role of electrically separating the FET26 from the photodiode 27. Thirdly a gate groove 25 of FET26 is formed by etching process. Finally an SiO2 insulating film 19 may be formed by CVD process on the gate groove 25.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor opto-electronic composite device in which a semiconductor optical device and a semiconductor electronic device are formed on one semiconductor substrate.

(Prior art and its problems) In light emitting elements and light receiving elements necessary for optical fiber communication, it is important to monolithically integrate semiconductor optical elements and semiconductor electronic elements in order to increase speed and reliability.

For example, Electronics Letters magazine (1983 Vo119, NO, 22), 905-90
On page 6, a semiconductor opto-electronic composite device in which a PIN photodiode and a MISFET are integrated is shown as shown in FIG.

1 is a PIN photodiode, 2 is a MISIT.

3 is an n-type InP substrate, 4 is an n-type InP, 5 is an undoped InGaAsP, 6 is a P-type InP, 7 is an n-type InP (
or n-type InGaAsP), 8 (shaded area) is a P-type impurity diffusion region, 9 is a Fin side electrode, 19 is an 8 i 02 insulating film, 20 is a P-side electrode, 22 is a drain electrode, 23 is a source electrode, 24 is a gate The electrode 30 is an M line. FIG. 1 is a cross-sectional view of the P-type impurity diffusion region 8 and the electrode 9.
20. Hatching is applied only to 22 to 24, and I/hatching is omitted from other parts.

In the conventional semiconductor optoelectronic composite device shown in FIG.
In order to carry out the photoresist process for forming FET 2 with high precision, it is necessary to make a
It is necessary that the heights from the bottom surface of the substrate 3 are the same as the top surface of the substrate 7).

Therefore, in the conventional device shown in this figure, a step is provided on the semiconductor substrate 3 in order to compensate for the difference in height between the photodiode 1, which is a semiconductor optical device, and the FET 2, which is a semiconductor electronic device. However, with this method of providing steps, there are limits to the controllability of etching depth and epitaxial growth, making it difficult to compensate for differences in device height to the electrocardiographic range. Reeds and fine patterns, such as Fh:T2 gates with a length of 1 μm or less, cannot be formed with high precision and good reproducibility. Therefore, conventional semiconductor composite devices have poor manufacturing yields. Furthermore, in the conventional structure, as the number of elements with different heights increases, different steps must be created on the board by that number, making the manufacturing process complicated and requiring a large number of steps, which also reduces the manufacturing yield. It was low.

As mentioned above, the semiconductor optoelectronic composite device with the conventional structure is
It has been difficult to manufacture with high yield and high performance.

(Object of the Invention) An object of the present invention is to provide a semiconductor optoelectronic composite device with high performance and good manufacturing yield.

(Structure of the Invention) The structure of the present invention is that in a semiconductor opto-electronic composite device including a semiconductor optical device and a semiconductor electronic device formed on the same semiconductor substrate, the semiconductor substrate is of a conductive type, the semiconductor optical device and the A multilayer epitaxial semiconductor including a semiconductor element of a semiconductor electronic device is formed on the semiconductor substrate, at least one layer in the multilayer epitaxial semiconductor is a semi-insulating semiconductor layer, and the multilayer epitaxial semiconductor layer is substantially parallel to the surface of the multilayer epitaxial semiconductor. An impurity-introduced region extending in a perpendicular direction to a depth exceeding at least the semi-insulating semiconductor layer is formed, and the impurity-introduced region serves as a current path for the semiconductor optical device.

(Example) The present invention will be described in detail below with reference to Examples.

FIG. 2 is a sectional view showing an embodiment of the present invention, and 11 is (0
01) tin-doped n-type InP substrate, 12 has a thickness of 1/
jm tin (8n) doped n-type InP.

13 is undoped InGaAsP with a thickness of 1.5 μm (
14 is a tin (8n)-doped n-type InP with a thickness of 1 μm.

15 is a 1 μm thick cobal (Co) doped semi-insulating InP116 is a 1 μm thick tin (Sn) doped n-type I
It is nP. Although FIG. 2 is a cross-sectional view, only the P-type Zn diffusion region and the electrode are hatched, and the hatching is omitted in other parts.

To fabricate this example, first a flat surface (001
) on the tin-doped n-type InP substrate 11.
type InP12, undoped In-GaAsPl3,
Tin-dawg n-type I n P l 4 , cobalt-doped semi-insulating I n P 15 , tin-doped n-type InP
16 are sequentially formed by liquid phase epitaxial growth (LPE). Next, a p-type zinc diffusion region 17 (shaded area) is formed by ordinary selective diffusion using the insulating film as a mask. This P type diffusion region 17 has a diameter of 100 μm and a depth of n type I.
It has reached nP14. Next, a second P-type zinc diffusion is performed to form a P-type zinc diffusion region 18 between the photodiode 27 and the FET 26. This P-type diffusion region 18 has a width of about 10 to 20 μm and a length of about 400 μm, and the diffusion depth reaches the semi-insulating InP 15 but does not penetrate through it. P-type diffusion region 18 serves to electrically isolate FET 26 and photodiode 27. Next, FET
26 gate grooves 25 are formed by etching. The direction of the gate groove 25 is the (110) direction, and the gate length is 1 μm.
The width of one gate is 400 μm. Next, goo) #125
8 i 0 on top! An insulating film 19 is formed by the CVD method.

Its layer thickness is 0.08-0.1 μm. Next, the P-side electrode (Au
Zn/Au) 20 is formed. Next, the n-side electrode (Au G e N i /Au) 2 of the photodiode 27
1 and the source electrode of FET 26 (AuGeNi/Au) 2
3 and a drain electrode (AuGeNi/Au) 22 are formed, and then a gate electrode (Al) 24 is formed.

N-side electrode 21 and gate electrode 24 of photodiode 27
A! (This embodiment is a circuit that amplifies the output of the photodiode 27 using a t-FET 26.)

This embodiment has been described in detail above. Although the liquid phase epitaxial growth method has been described in the manufacturing method of this example, this example can also be manufactured using a vapor phase growth method.

The present invention can also be realized by modifying this embodiment as follows. For example, tin-doped n-type InP 12.14°16 may be replaced with tellurium (Te)-doped n-type InP. In addition, the P-type zinc diffusion regions 17 and 18 are made of P-type cadmium (C
d) It may be replaced by a diffusion region.

In addition, Gopalt-doped semi-insulating InP15 is made of iron (Fe).
) Doped semi-insulating InP or chromium (Cr)-doped semi-insulating InP may be substituted. Further, the same effect can be obtained even if the n-type InP 16 in the epitaxial layer is replaced with P-type InP, and the P-type diffusion region 18 is replaced with an n-type region.

This P-type diffusion region 18 is connected to the photodiode 27 and the FE.
The purpose is to electrically isolate T26. Therefore,
Even if the structure is such that a groove is formed by removing the P-type diffusion region 18 by etching, the present invention has the same effect as the embodiment. In the manufacturing method of the above-described embodiment, the P-type diffusion region 17
．． Although the regions 17 and 18 were formed by a normal thermal diffusion method, in this embodiment, the same effect can be obtained even if the regions 17 and 18 are formed by ion implantation.

In the above embodiment, since the InP substrate 11 does not require a level difference corresponding to the elements of different heights, the InP substrate 11 is
Since there is no photoresist process or etching process for the substrate 11, it can be manufactured with fewer man-hours than the conventional composite element shown in FIG. Furthermore, since epitaxial growth is performed on a flat InP substrate, reproducibility and controllability are good, and there is little variation in the growth layer thickness within the growth plane, and errors in the growth layer thickness from a predetermined value affect device characteristics. Not at all.

These advantages have greatly improved manufacturing yields, which are twice as high as conventional methods.

Furthermore, since the semiconductor layers of the FET 26 and the photodiode 27 in the embodiment shown in FIG.
In the photoresist process for forming the gate electrode 24 and the gate electrode 24, a photoresist mask and a semiconductor layer (I
nP16) can be completely adhered to. Therefore, even an FET with a gate length of 1 μm can be formed with good reproducibility within an error of ±0.1 μm, making it possible to achieve an accuracy 92 times higher than that of the conventional method. In this way, the short gate length provides high sensitivity, and the good reproducibility leads to high yield.

Further, since there is little variation in the pattern within the plane, the yield is also good from this point of view as well. Furthermore, since photoresist can be formed with high precision, it is now possible to attach the gate electrode 24 only to the bottom of the gate trench 25, reducing the parasitic capacitance between the gate and source much more than before. D 0.1PF less o, spF'
We were able to reduce it to This improved reception sensitivity.

As described above, the composite element of the FET and photodiode according to the embodiment has a high manufacturing yield and high performance.

Although this embodiment shows a composite element of one FET and one photodiode, the present invention can also be applied to a composite element of a large number of semiconductor optical devices and semiconductor electronic devices. Further, although this embodiment shows a composite element of an FET and a photodiode, the structure of the present invention can also be used for a composite element of a semiconductor optical element such as a light emitting diode or a semiconductor laser, and a semiconductor electronic element such as an FET. In addition, in this example, InGaAsP
/InP-based material was used, but other materials such as AlGa
A similar effect can be obtained using As/GaAs.

(Effects of the Invention) According to the present invention, as described in detail above, a semiconductor opto-electronic composite device with high performance and good manufacturing yield can be provided.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a conventional semiconductor optoelectronic composite device, and FIG. 2 is a sectional view of an embodiment of the present invention. l...Photodiode, 2...FE
T, 3... Semiconductor substrate, 4... N-type I
nP, 5...Undoped InGaA'sP, 5
-=-・-P type InP, 7・・−・−n type InP, 8・
...P type impurity diffusion region, 9...n type electrode, 11...n type InP substrate, 12...
・N-type I n P. 13... Undoped InGaABP, 14...
...N-type InF%15...Semi-insulating InP
, 16... n-type InP. 17.1B...P-type diffusion region, 19...
・Sioz insulating film, 20...P side electrode (Au
Zn/Au), 21... n-side electrode (AuGe
Ni/Au)% 22...Drain electrode (Au
GeNi/Au), 23... Source electrode (A
uGeNi/Au), 24-------gate electrode (1
). 25...Ge-) Groove, 26...F'ET
, 27...Photodiode. 'V-1 clause 2/ )) ζshi 2 1shi and I

Claims (1)

[Claims] A semiconductor opto-electronic composite device including a semiconductor optical device and a semiconductor electronic device formed on the same semiconductor substrate, wherein the semiconductor substrate is of a conductive type, and a multilayer epitaxial semiconductor including the semiconductor elements of the semiconductor optical device and the semiconductor electronic device. is formed on the semiconductor substrate, at least one layer in the multilayer epitaxial semiconductor is a semi-insulating semiconductor layer, and the semi-insulating semiconductor layer extends substantially perpendicularly from the surface of the multi-layer epitaxial semiconductor. An impurity-introduced region is formed to a depth at least exceeding
A semiconductor optoelectronic composite device characterized in that the impurity-introduced region serves as a current path for the semiconductor optical device.