JPS60217705A - Power amplifier - Google Patents
Power amplifierInfo
- Publication number
- JPS60217705A JPS60217705A JP59074165A JP7416584A JPS60217705A JP S60217705 A JPS60217705 A JP S60217705A JP 59074165 A JP59074165 A JP 59074165A JP 7416584 A JP7416584 A JP 7416584A JP S60217705 A JPS60217705 A JP S60217705A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- pulse
- drain voltage
- circuit
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【発明の詳細な説明】
(技術分野)
本発明は電力増幅器に係シ、特に高出力トランジスタを
増幅素子として用いた電力増幅器に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a power amplifier, and particularly to a power amplifier using a high-output transistor as an amplifying element.
(従来技術)
最近、高出力、高周波におけるトランジスタが多数開発
され、その応用が研究されている。これらのトランジス
タの中でもGa As電界効果トランジスタ(以後FE
Tという)は、高出力、高周波化に最も適した増幅素子
と言える。従来のこのFETを多段縦続接続した電力増
幅器の回路を第1図に示す。同図において、ゲート電圧
端子4およびドレイン電圧端子5から各々に一定の電圧
値に常にバイアスされたFETIが多段縦続接続され、
このうち第1段の電力増幅器の入力端子2に高周波信号
が入力され、所望のレベルまで多段増幅され、出力端子
3から出力される。(Prior Art) Recently, many high-output, high-frequency transistors have been developed, and their applications are being studied. Among these transistors, GaAs field effect transistors (hereinafter referred to as FE)
T) can be said to be the most suitable amplification element for high output and high frequency. FIG. 1 shows a conventional power amplifier circuit in which multiple stages of FETs are connected in cascade. In the figure, FETIs each always biased at a constant voltage value from a gate voltage terminal 4 and a drain voltage terminal 5 are connected in cascade in multiple stages.
A high frequency signal is input to the input terminal 2 of the first stage power amplifier, multi-stage amplified to a desired level, and output from the output terminal 3.
このような従来の電力増幅器では、高周波入力信号がパ
ルスであっても各々のFB’I’のゲート、ドレイン電
流は一定状態の値となるため、高周波入力信号がない時
でも直流電力が無駄になシ、電力の利用効率が低いと言
う欠点があった。一方、高周波入力信号のパルスに同期
してFETのゲート電圧およびドレイン電圧をON10
F Fするようにゲート電圧端子4およびドレイン電
圧端子5に電源を供給することで電力増幅器の消費電力
を改善することができる。しかし、この場合も電力増幅
器の出力電力を上げるためにドレイン電圧を定格まで上
げ、大電流のピークドレイン電流を流すと、各々のFE
Tの平均チャネル温度が周囲温度によって定格温度近く
壕で上昇することがおる。In such conventional power amplifiers, the gate and drain currents of each FB'I' remain constant even when the high-frequency input signal is a pulse, so DC power is wasted even when there is no high-frequency input signal. However, it had the disadvantage of low power usage efficiency. On the other hand, in synchronization with the pulse of the high frequency input signal, the gate voltage and drain voltage of the FET are turned ON10.
The power consumption of the power amplifier can be improved by supplying power to the gate voltage terminal 4 and the drain voltage terminal 5 in such a manner that the gate voltage terminal 4 and the drain voltage terminal 5 are FF. However, in this case as well, if the drain voltage is increased to the rated value and a large peak drain current is passed in order to increase the output power of the power amplifier, each FE
The average channel temperature of T can rise near the rated temperature in the trench due to ambient temperature.
このような電力増幅器では入力パルスのくシ返し率の増
加、またはパルス幅が広くなった時には、前記の平均チ
ャネル温度がさらに上昇するため、電力増幅器の信頼性
が低下すると言う欠点があった。In such a power amplifier, when the repetition rate of the input pulse increases or the pulse width becomes wider, the above-mentioned average channel temperature further increases, resulting in a decrease in the reliability of the power amplifier.
(発明の目的)
本発明の目的は、これらの欠点を除き、低消費電力にて
、入力パルスのくシ返し率およびパルス幅の変動があっ
てもFETの平均チャネル温度を一定に保ち、信頼性を
低下させ7−7″−とのない電力増幅器を提供すること
にある。(Objective of the Invention) An object of the present invention is to eliminate these drawbacks, maintain a constant average channel temperature of the FET even with variations in the input pulse repetition rate and pulse width, and achieve reliability with low power consumption. The object of the present invention is to provide a power amplifier that does not have 7-7''-
(発明の構成)
本発明の電力増幅器の構成は、高周波入力信号を2分配
する分配器と、2分配された一方が入力される増幅回路
と、他方が入力される検波器と、ここで検波された信号
から前記高周波入力信号のパルスのくシ返し率およびパ
ルス幅を検出する検出回路と、前記パルスのくシ返し率
およびパルス幅が変動しても前記増幅回路に使用されて
いるFETのチャネル温度が一定となるように前記検出
回路からFETのドレイン電圧が常に最適状態となるド
レイン電圧を発生させる信号発生回路と、前記高周波入
力信号のパルスに対応して前記ドレイン電圧を前記増幅
回路に使用しているFBTに供給する制御回路とを含み
構成される。(Configuration of the Invention) The configuration of the power amplifier of the present invention includes a divider that divides a high-frequency input signal into two, an amplifier circuit to which one of the two divided signals is input, a detector to which the other is input, and a detector that detects the signal. a detection circuit that detects the pulse repetition rate and pulse width of the high-frequency input signal from the input signal, and a detection circuit that detects the pulse repetition rate and pulse width of the high-frequency input signal; a signal generating circuit that generates a drain voltage from the detection circuit that always brings the drain voltage of the FET to an optimum state so that the channel temperature is constant; It is configured to include a control circuit that supplies the FBT in use.
(実施例) 次に図面を参照しながら本発明の詳細な説明する。(Example) Next, the present invention will be described in detail with reference to the drawings.
、第2図は本発明の一実施例の電力増幅器を示すブロッ
ク図である。同図において、増幅回路11は第1図の従
来例の電力増幅器と略同様であってよい。今、入力端子
12から入力された高周波入力信号は、分配器16にて
2分配され、一方は増幅回路11に入力され、他方は検
波器17に入力され、検波された信号は検出回路18へ
送られる。, FIG. 2 is a block diagram showing a power amplifier according to an embodiment of the present invention. In the figure, an amplifier circuit 11 may be substantially the same as the conventional power amplifier shown in FIG. Now, the high frequency input signal input from the input terminal 12 is divided into two by the divider 16, one is input to the amplifier circuit 11, the other is input to the detector 17, and the detected signal is sent to the detection circuit 18. Sent.
この検出回路18では、検波信号からパルスのくシ返し
率およびパルス幅を検出し、各々の検出データは次の信
号発生回路19に供給される。信号発生回路19では、
前もって増幅回路11に使用しているFETの平均チャ
ネル温度をある設定した温度にするパルスくシ返し率お
よびパルス幅と第3図に示すドレイン電圧の値を記憶し
ておき、前記パルスくシ返し率及びパルス幅の検出デー
タから、平均チャネル温度を一定にするに最適なドレイ
ン電圧を信号発生回路19にて発生する。この信号発生
回路19で得られた最適ドレイン電圧は、制御回路20
において、前記高周波入力信号のパルスに強大り奔パル
スj書場六七−鮨V慟幅回路11のFETにパルス状の
最適ドレイン電圧が印加される。This detection circuit 18 detects the pulse repetition rate and pulse width from the detected signal, and each detected data is supplied to the next signal generation circuit 19. In the signal generation circuit 19,
The pulse repetition rate and pulse width and the value of the drain voltage shown in FIG. Based on the detected data on the rate and pulse width, the signal generating circuit 19 generates the optimal drain voltage to keep the average channel temperature constant. The optimum drain voltage obtained by this signal generation circuit 19 is determined by the control circuit 20.
, a pulsed optimum drain voltage is applied to the FET of the high-frequency input signal pulse and the pulse width circuit 11.
尚、前記実施例では、入力パルスの状態を検出するのに
電力増幅器の高周波入力信号の一部をとシだして検出し
たが、この他に高周波入力信号のパルスに同期したパル
スを外部から受けてこのパルスからくり直し率およびパ
ルス幅を検出する回路を用いてもよい。In the above embodiment, a part of the high-frequency input signal of the power amplifier is emitted and detected to detect the state of the input pulse, but in addition to this, a pulse synchronized with the pulse of the high-frequency input signal is received from the outside. A circuit that detects the repetition rate and pulse width from the lever pulse may be used.
(発明の効果)
以上説明したように、本発明によれば、高周波入力信号
のパルスのくシ返し率およびパルス幅を検出し、検出結
果からFETの平均チャネル温度が一定になるようにド
レイン電圧を自動的に変化させ、前記高周波信号のパル
スに対応したパルスに前記ドレイン電圧を0N10FF
した後に、各々0FETのドレインに供給することから
、低消費電力となシ、また前記パルスのく)返し率、バ
ルル温度を最適の状態に保つことができ、信頼性を損な
うことなく増幅でき、従来の一定バイア方式よシ温度が
低くなるので従来時と同じ温度まで上昇することが許さ
れるのであればさらに高電力を出力することができる等
の効果が得られる。(Effects of the Invention) As explained above, according to the present invention, the pulse repetition rate and pulse width of a high-frequency input signal are detected, and the drain voltage is adjusted based on the detection results so that the average channel temperature of the FET is constant. automatically changes the drain voltage to a pulse corresponding to the pulse of the high frequency signal.
After that, the pulses are supplied to the drains of the respective 0FETs, resulting in low power consumption, the repetition rate of the pulses, and the valve temperature can be maintained at optimum conditions, and the pulses can be amplified without impairing reliability. Since the temperature is lower than in the conventional constant via method, effects such as higher power output can be obtained if the temperature is allowed to rise to the same level as in the conventional method.
第1図は従来の電力増幅器を示す回路図、第2図は本発
明の一実施例の電力増幅器を示すブロック図、第3図は
入力パルスのくシ返し率、パルス幅とPETの最適ドレ
イン電圧との関係を示す特性図である。尚、図において
1・・・・FB’l’、 2.12・・・・・入力端子
、3.13・・・・・出力端子、4.14・・・・・・
ゲート電圧端子、5.15・・・・・ドレイン電圧端子
、11・・・・・・増幅回路、16・・・・・・分配器
、17・・・・・・検波器、18・・・・・・検出回路
、19・・・・・・信号発生回路、20・・・・・・制
御回路。
¥−2−倒
蓼3@Fig. 1 is a circuit diagram showing a conventional power amplifier, Fig. 2 is a block diagram showing a power amplifier according to an embodiment of the present invention, and Fig. 3 shows input pulse repetition rate, pulse width, and optimum drain of PET. FIG. 3 is a characteristic diagram showing the relationship with voltage. In the figure, 1...FB'l', 2.12...Input terminal, 3.13...Output terminal, 4.14...
Gate voltage terminal, 5.15...Drain voltage terminal, 11...Amplifier circuit, 16...Distributor, 17...Detector, 18... . . . detection circuit, 19 . . . signal generation circuit, 20 . . . control circuit. ¥-2-Toppling 3@
Claims (1)
の一方の信号を増幅する高周波電力増幅素子を有する増
幅回路と、前記分配器からの他方の信号を検波する検波
器と、この検波器で検波された信号から前記高周波入力
信号のパルスのくシ返し率およびパルス幅を検出する検
出回路と、この検出回路からの前記パルスのくシ返し率
およびパルス幅のデータをもとに前記高周波電力増幅素
子に印加されるべき最適バイアス電圧を発生する信号発
生回路と、前記バイアス電圧を前記高周波入力信号のパ
ルスに対応して前記高周波電力増幅素子に供給する制御
回路とを具備していることを特徴とする電力増幅器。a divider that divides a high-frequency input signal into two; an amplifier circuit having a high-frequency power amplification element that amplifies one signal from the divider; a detector that detects the other signal from the divider; a detection circuit that detects the pulse repetition rate and pulse width of the high-frequency input signal from the signal detected by the high-frequency input signal; A signal generation circuit that generates an optimal bias voltage to be applied to a power amplification element, and a control circuit that supplies the bias voltage to the high frequency power amplification element in response to pulses of the high frequency input signal. A power amplifier featuring:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59074165A JPS60217705A (en) | 1984-04-13 | 1984-04-13 | Power amplifier |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59074165A JPS60217705A (en) | 1984-04-13 | 1984-04-13 | Power amplifier |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60217705A true JPS60217705A (en) | 1985-10-31 |
JPH0311683B2 JPH0311683B2 (en) | 1991-02-18 |
Family
ID=13539265
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59074165A Granted JPS60217705A (en) | 1984-04-13 | 1984-04-13 | Power amplifier |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60217705A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01321704A (en) * | 1988-06-24 | 1989-12-27 | Japan Radio Co Ltd | Radio frequency power amplifier |
JP2014017624A (en) * | 2012-07-06 | 2014-01-30 | Japan Radio Co Ltd | Amplifier control device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5863202A (en) * | 1981-10-13 | 1983-04-15 | Toshiba Corp | High frequency pulse power amplifier |
-
1984
- 1984-04-13 JP JP59074165A patent/JPS60217705A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5863202A (en) * | 1981-10-13 | 1983-04-15 | Toshiba Corp | High frequency pulse power amplifier |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01321704A (en) * | 1988-06-24 | 1989-12-27 | Japan Radio Co Ltd | Radio frequency power amplifier |
JP2014017624A (en) * | 2012-07-06 | 2014-01-30 | Japan Radio Co Ltd | Amplifier control device |
Also Published As
Publication number | Publication date |
---|---|
JPH0311683B2 (en) | 1991-02-18 |
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