JPS60214121A - Analog-digital converter - Google Patents

Analog-digital converter

Info

Publication number
JPS60214121A
JPS60214121A JP6996184A JP6996184A JPS60214121A JP S60214121 A JPS60214121 A JP S60214121A JP 6996184 A JP6996184 A JP 6996184A JP 6996184 A JP6996184 A JP 6996184A JP S60214121 A JPS60214121 A JP S60214121A
Authority
JP
Japan
Prior art keywords
converter
subtraction
analog
level
analog value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6996184A
Other languages
Japanese (ja)
Inventor
Masakazu Kitajima
北島 正和
Keiichi Okamoto
岡本 敬一
Mikio Sato
佐藤 三喜夫
Makoto Watanabe
真 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP6996184A priority Critical patent/JPS60214121A/en
Publication of JPS60214121A publication Critical patent/JPS60214121A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12Analogue/digital converters
    • H03M1/18Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To attain the processing exceeding the rated resolution of an A/D converter by providing a subtraction circuit and a subtraction deciding means deciding that a digital signal data exceeds a prescribed level. CONSTITUTION:Since an input analog value to a sensor or the like is lower than a prescribed level (a) at the initial state, the subtraction circuit 12 is not activated. Thus, relation of x=c is obtained at an operating means 14 for the data (x) desired to be obtained. When the analog value reaches the prescribed level (a), a subtraction deciding means 15 is activated and an analog value reaches a level (b). Thus, the operation at (c) in Fig. is obtained as x=a+(c'-b). When the analog value is decreased and the level (c) is lower than the level (b), the operation of the deciding means 15 is stopped and the operation of the data to be obtained restores to the relation of x=c. Thus, the processing exceeding the rated resolution of the A/D converter is attained.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、多種のセンサー等よシ出力されるアナログ信
号をデジタル化し、デジタル表示・判定等に利用するた
めのアナログ−デジタル変換回路に関するものである。
[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to an analog-to-digital conversion circuit for digitizing analog signals output from various types of sensors, etc., and using the digitized signals for digital display, judgment, etc. It is.

(従来例の構成とその問題点) この発明に最も近い従来技術について、図面を用いてそ
の構成および問題点を述べる。
(Constitution of Conventional Example and its Problems) The constitution and problems of the prior art closest to the present invention will be described with reference to the drawings.

第1図は従来のアナログ−デジタル変換装置を示してい
る。第1図において1は、センサー等入力、2は増幅器
、3はΦ変換器、4は表示等を制御する制御手段、5は
表示器等の端末であり、このアナログ−デジタル変換装
置において、A/D変換器3の持つ分解能と表示等を制
御する制御手段4の分解能との関係は、制御手段4はい
変換器3の持つ定格分解能以上の働きはできない。
FIG. 1 shows a conventional analog-to-digital converter. In FIG. 1, 1 is an input such as a sensor, 2 is an amplifier, 3 is a Φ converter, 4 is a control means for controlling a display, etc., and 5 is a terminal such as a display. The relationship between the resolution of the /D converter 3 and the resolution of the control means 4 that controls display etc. is such that the control means 4 cannot function beyond the rated resolution of the converter 3.

たとえば、8ビツトめ変換器では、256ステツプの分
解能を持っていて、センサー等の入力1を細部検出が必
要となった場合、定格の256ステツプの分解能での検
出しかできない。
For example, an 8-bit converter has a resolution of 256 steps, and if detailed detection of input 1 of a sensor or the like is required, detection can only be performed with the rated resolution of 256 steps.

また、表示器等の端末において“8ビツト′もしくは、
“256″以上の表示機能は、持っていない。
In addition, in terminals such as displays, "8 bits" or
It does not have a display function of "256" or more.

(発明の目的) 本発明は、上記従来例の欠点を除去するものであシ、φ
変換器の定格分解能以上の処理能力を有し、センサー等
の入力変化を細部検出するととを目的とするものである
(Object of the invention) The present invention eliminates the drawbacks of the above-mentioned conventional example.
It has a processing capacity that exceeds the rated resolution of the converter, and is intended to detect detailed input changes from sensors, etc.

(発明の構成) 本発明は、センサー等の入力の減算回路とアナログ入力
をデジタル化するヤφ変換器と、デジタル信号データの
1定レベルを越えたことを判定する減算判定手段と、前
記減算判定手段の信号に基いて、め変換器のデジタル信
号を演算する演算手段とを備え、の変換器の定格分解能
以上の処理を可能としたアナログ−デジタル変換装置で
ある。
(Structure of the Invention) The present invention comprises a subtracting circuit for an input such as a sensor, a φ converter for digitizing an analog input, a subtraction determining means for determining whether digital signal data exceeds a certain level, and a This analog-to-digital conversion device is equipped with arithmetic means for calculating the digital signal of the converter based on the signal of the determination means, and is capable of processing at a resolution higher than the rated resolution of the converter.

(実施例の説明) 本発明の一実施例の構成について第2図以下の図面とと
もに説明する。
(Description of Embodiment) The configuration of an embodiment of the present invention will be described with reference to the drawings from FIG. 2 onwards.

第2図は、機能!ロワ2図であシ、センサー等の入力1
1から得られるアナログ信号は、減算回路12を通じて
、め変換器13でデジタル化される。デジタル信号は、
演算手段14及び減算判定手段15へ送られ、減算判定
手段15からの信号は、減算回路12ヘフイードバツク
される。演算手段14を通った信号は、表示器等の端末
制御手段16で処理された後表示分鷲の端末←争へ送ら
れる。
Figure 2 shows the function! Lower figure 2, sensor input 1
The analog signal obtained from 1 is digitized by a subtractor 13 through a subtraction circuit 12. The digital signal is
The signal is sent to the calculation means 14 and the subtraction judgment means 15, and the signal from the subtraction judgment means 15 is fed back to the subtraction circuit 12. The signal passed through the calculation means 14 is processed by a terminal control means 16 such as a display, and then sent to a display terminal.

本発明は、上記の構成をもつもので、その要部の回路図
を、第3図に示す。マイクロコンビー−タA内に前記の
演算手段14、減算判定手段15、表示器等の端末制御
手段16が収納される。減算回路12は、増幅器を応用
した回路で構成される。
The present invention has the above-mentioned configuration, and a circuit diagram of the main part thereof is shown in FIG. Inside the microcombinator A, the above-mentioned calculation means 14, subtraction determination means 15, and terminal control means 16 such as a display are housed. The subtraction circuit 12 is constructed of a circuit using an amplifier.

具体的動作説明を第4図のセンサー等の入力のアナログ
値変化及び第5図のフローチャートを用いて説明する。
The specific operation will be explained using the analog value change of the input of the sensor etc. in FIG. 4 and the flowchart in FIG. 5.

センサー等の入力のアナログ値は初期状態において、一
定レベルaよシ低く、減算回路12が動作していないの
で請求めようとするデータXは、演算手段14でX=“
C″となる。一定レベル“a′にアナログ値が到達する
と減算判定手段15が動作し、アナログ値は、”ビレペ
ルとなる。この“b”が演算パラメータに決定され、“
C″における演算は、x = a十(c’−b )とな
ってめられる。
In the initial state, the analog value of the input of the sensor, etc. is lower than a certain level a, and since the subtraction circuit 12 is not operating, the data X to be requested is calculated by the calculation means 14 as
C". When the analog value reaches a certain level "a", the subtraction determination means 15 operates, and the analog value becomes "Birepel". This "b" is determined as the calculation parameter, and "
The operation in C'' can be expressed as x=a0(c'-b).

またアナログ値が降下して、”ビレペルよシ“C#レベ
ルが小さくなると(演算0 ) c ’−bが成立する
)減算判定手段15の動作が停止され請求めるデータの
演算はX=”c″にもどる。
Also, when the analog value decreases and the "C# level becomes smaller (calculation 0) c'-b", the operation of the subtraction judgment means 15 is stopped and the calculation of the data that can be requested is X = "c". Return to ″.

次にこの実施例を、8ピツ)(255ステツプ)め変換
器を用いた電子血圧計において、0〜300Wff+I
Hgにわたって断続指示間隔IWrInHpを表示する
ものに使用した例について説明する。
Next, this example was applied to an electronic blood pressure monitor using an 8-pin (255-step) converter.
An example in which the intermittent instruction interval IWrInHp is displayed over Hg will be described.

第6図は血圧値(アナログ値)が8ビット分解能を越え
たときにも、減算が行なわれることによって、め変換器
の処理可能レベルで表示が行なわれることを示している
FIG. 6 shows that even when the blood pressure value (analog value) exceeds the 8-bit resolution, subtraction is performed so that the display is performed at a level that can be processed by the converter.

この例では、8ピツ)(255ステツf)内に250ス
テツプに1定レベル判定値(第6図のa)を持つ。この
レベルは、め変換器13によって処理されたデータをマ
イクロコンビーータA内の減算判定手段15によって判
定されるレベルである。
In this example, there is one constant level judgment value (a in FIG. 6) in 250 steps within 8 steps (255 steps f). This level is the level determined by the subtraction determining means 15 in the micro converter A on the data processed by the converter 13.

上記減算判定手段15によって、マイクロコンビーータ
Aから信号出力され、減算回路12が動作する。
The subtraction determining means 15 outputs a signal from the microconbeater A, and the subtraction circuit 12 operates.

減算回路動作後のレベル(第6図のb)は、〜生変換器
を通してマイクロコンビーータに記憶され以後(減算回
路動作中)は、次式によってC点(第6図のC)の圧力
を演算する。
The level after the subtraction circuit operates (b in Figure 6) is stored in the micro converter through the ~ raw converter, and thereafter (during the subtraction circuit operation) the pressure at point C (C in Figure 6) is determined by the following formula: Calculate.

x=c’+ (a−b ) c’=220 、a=250 、b=200とするとx
 = 220 + (250−200) =、 270
 wnHllとなシ、この演算によシ従来255 ta
nHfjまでしか表示できなかったものが300 tt
anHgまで表示が可能となる。
x=c'+ (a-b) If c'=220, a=250, b=200, x
= 220 + (250-200) =, 270
wnHll, this operation is conventionally 255 ta
The one that could only display up to nHfj was 300 tt.
It is possible to display up to anHg.

(発明の効果) 以上の通シであるから、本発明によれば、め変換器の定
格分解能を越えた処理を可能とし、め変換器の分解能を
越えたアナログ入力の細部変化を検出表示することがで
きる効果が得られる。
(Effects of the Invention) As described above, according to the present invention, processing exceeding the rated resolution of the converter is possible, and detailed changes in analog input exceeding the resolution of the converter can be detected and displayed. You can get the desired effect.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のアナログーデノタル変換装置による例え
ば表示装置のブロック回路図、第2図は本発明のアナロ
グ−デジタル変換装置による例えば表示装置のブロック
回路図、第3図は同表示装置の実施例の回路図、第4図
は同表示装置の減算判定手段が動作したときの演算手段
の動作を説明するだめの図、第5図は本発明装置の演算
手段および減算手段の機能を示すフローチャート、第6
図は、本発明装置を8ビット分解能のめ変換器を電子血
圧計に使用したときの動作の説明図である。 11・・・士ンヤー等の入力、12・・・減算回路、1
3・・・アナログ−デジタル変換器、14・・・演算手
段、15・・・減算判定手段、16・・・端末制御手段
、17・・・表示器、A・・・マイクロコンビーータ。 第1図 第2図 第3図 第4図 地馴m OFF ’ ON ’ OFF第5図
FIG. 1 is a block circuit diagram of, for example, a display device using a conventional analog-to-digital converter, FIG. 2 is a block circuit diagram of, for example, a display device using the analog-to-digital converter of the present invention, and FIG. 3 is a block circuit diagram of the same display device. The circuit diagram of the embodiment, FIG. 4 is a diagram for explaining the operation of the calculation means when the subtraction determination means of the same display device operates, and FIG. 5 shows the functions of the calculation means and the subtraction means of the device of the present invention. Flowchart, No. 6
The figure is an explanatory diagram of the operation when the device of the present invention is used as an 8-bit resolution converter in an electronic blood pressure monitor. 11...Input of operator etc., 12...Subtraction circuit, 1
3... Analog-digital converter, 14... Arithmetic means, 15... Subtraction determination means, 16... Terminal control means, 17... Display, A... Microconbeater. Figure 1 Figure 2 Figure 3 Figure 4 Familiarization OFF 'ON' OFF Figure 5

Claims (1)

【特許請求の範囲】[Claims] センサー等の入力の減算回路とアナログ入力をデジタル
化するアナログ−デジタル(A/1))変換器と、デジ
タル信号データの1定レベルを越えたことを判定する減
算判定手段と、前記減算判定手段の信号に基き、アナロ
グ−デジタル(pv’D )変換器のデジタル信号を演
算する演算手段とを備えたことを特徴とするアナログ−
デジタル変換装置。
A subtraction circuit for an input such as a sensor, an analog-to-digital (A/1) converter for digitizing an analog input, a subtraction determination means for determining whether digital signal data exceeds a certain level, and the subtraction determination means. an analog-to-digital (pv'D) converter for calculating a digital signal based on the signal from the analog-to-digital (pv'D) converter.
Digital conversion device.
JP6996184A 1984-04-10 1984-04-10 Analog-digital converter Pending JPS60214121A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6996184A JPS60214121A (en) 1984-04-10 1984-04-10 Analog-digital converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6996184A JPS60214121A (en) 1984-04-10 1984-04-10 Analog-digital converter

Publications (1)

Publication Number Publication Date
JPS60214121A true JPS60214121A (en) 1985-10-26

Family

ID=13417756

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6996184A Pending JPS60214121A (en) 1984-04-10 1984-04-10 Analog-digital converter

Country Status (1)

Country Link
JP (1) JPS60214121A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51129131A (en) * 1975-05-01 1976-11-10 Omron Tateisi Electronics Co Analog-digital conversion circuit
JPS5440549A (en) * 1977-09-07 1979-03-30 Yasuda Denken Kk Ad converter rated range expanding system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51129131A (en) * 1975-05-01 1976-11-10 Omron Tateisi Electronics Co Analog-digital conversion circuit
JPS5440549A (en) * 1977-09-07 1979-03-30 Yasuda Denken Kk Ad converter rated range expanding system

Similar Documents

Publication Publication Date Title
JPH03229124A (en) Pressure transmitter
JPS6238062A (en) Method and apparatus for detecting binary signal
JPS60214121A (en) Analog-digital converter
JP2644742B2 (en) Composite transmitter
US6567756B1 (en) Portable pressure measuring apparatus
JP2924166B2 (en) Signal transmitter
JPS6136648B2 (en)
JPH0261518A (en) Analogue/digital conversion system
JPH1021001A (en) Coordinate input device
JP3191247B2 (en) Signal processing device
JPS5850434A (en) Vibration monitor
JPS6042378Y2 (en) waveform storage device
JP2795260B2 (en) Waveform drawing device for patient monitoring system
JPH0581590A (en) Signal transmitter
JPH01254995A (en) Display control device
JPH0631826Y2 (en) 2-wire signal transmitter
JPH04312021A (en) Analog data output circuit
JPH09304122A (en) Waveform recorder
JPS6136649B2 (en)
JPS61125601A (en) Controller with potentiometer
JPH02147909A (en) Gain control for pressure sensor
JPH0458615A (en) Device for adjusting zero point and span of analog signal
JPH04113221A (en) Sensor-measuring device
JPH0463006A (en) Signal level detection circuit
JPS60100614U (en) Physical quantity measurement circuit