JPS6021093A - Semiconductor integrated circuit having liquid crystal driving circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor integrated circuit having a liquid crystal drive circuit that can directly drive a liquid crystal display device.

BACKGROUND ART In general, it is known that liquid crystal driving methods include a static method, a bias bias maximum data type (so-called da-plex method), a feedback bias data type, a noise bias ξ data type, and the like. In addition, in recent years, many LSIs (integrated circuits) for electronic watches and LSIs for desktop computers have built-in one of the above-mentioned liquid crystal drive methods. Products with built-in circuits have been developed.

However, in conventional semiconductor integrated circuits having liquid crystal drive circuits, the liquid crystal drive method is determined to be one method, and the usable liquid crystal display devices are also limited. Therefore, when using liquid crystal display devices of different types, it is necessary to develop and manufacture many types of semiconductor devices that have the same other functions but differ only in the liquid crystal drive circuit, which reduces development time and costs. This has led to considerable manufacturing disadvantages.

(c) Purpose of the Invention The present invention has been made in view of the above-mentioned points, and has a liquid crystal drive circuit that can select any method from among a large number of liquid crystal drive methods by changing the wiring pattern mask. The purpose is to obtain semiconductor integrated circuits.

B) Structure of the Invention The present invention provides a semiconductor integrated circuit having a plurality of segment output terminals and a plurality of common output terminals for directly driving a liquid crystal display device. A plurality of segment drivers, a display switching circuit that selectively applies one of a plurality of display data to the segment drivers using a plurality of timing signals, and a frequency dividing circuit that divides a frequency signal from an oscillation circuit or the like. a timing generation circuit that generates a timing signal of the number of values based on the frequency-divided output and applies a liquid crystal drive frequency signal to the plurality of component drivers; and a timing generation circuit provided at each of the common blade terminals; a common driver to which a timing signal and a liquid crystal drive frequency signal are selectively applied, switching connections between the plurality of segment drivers and the segment output terminal, switching the period or fixed signal of the timing signal,
Further, by selecting the switching connection between the common driver and the timing signal using a wiring pattern mask of the semiconductor integrated circuit, different liquid crystal driving methods can be selected.

((E) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention, and is a block diagram of a main part of a semiconductor integrated circuit incorporating a liquid crystal drive circuit.The semiconductor integrated circuit is, for example, a 9-chip It is a microcomputer.

In Figure 1, the semiconductor integrated circuit has 42 segment output terminals (1) for driving the liquid crystal and three common output terminals (2) connected to the common electrode of the liquid crystal display device. Each of the segment output terminals (1) is provided with three segment drivers (3), (4), and (5), and each of the common output terminals (2) is provided with a common driver (6). ) are connected. The segment drivers (3) (4H5) are each driven by different power supplies and generate selected voltages based on the display data applied from the display signal switching circuit (power) and according to the timing signal from the timing generation circuit (8). Segment output terminal (1
). The output of the segment driver (4) is directly connected to the segment output terminal (1), but the output of the segment driver (3) (51) is selected by a switching means CH13 that is switched by a mask when manufacturing a semiconductor integrated circuit. Segment output terminal (1)
connected to. In this embodiment, the liquid crystal driving method can be switched between a static method, a maximum bias station duty method, a range bias b duty method, and a noise bias duty method, and the switching means CH13 is used for the 5 bias station duty method. is switched to A, and in other systems it is switched to B.
can be switched to

The display signal switching circuit (power is controlled by timing signals TMG1 to TMG3 from the timing generation circuit (8), and is controlled by the memory or latch circuit (
The display data 81-1+2+3 to 842-1+2+1 corresponding to the segments stored in
(Apply to 51.

The timing generating circuit (8) is a frequency dividing circuit (
The frequency division output of tI is 0. , Olo, the switching means CH
The display signal switching circuit (7) and the common driver (6)
timing signals TMG1 to TMG3 for synchronizing the segment drivers (3), (4) and common driver (6), a timing signal TMGB for applying the K liquid crystal drive frequency to the segment driver (5), and a timing signal TMGB for applying the liquid crystal drive frequency to the segment driver (5) A timing signal CHGVS for selectively applying a drive voltage is generated. The timing signals TMG1 to TMG3 are generated by a timing generation circuit (described in detail later).
8) The output form of the signal differs depending on the switching means in
The output form is determined by the liquid crystal driving method. In addition, the switching means CHI selects A1 bias in the case of the static method, B in the case of the data method, and C in the case of the current bias data method and the direct bias data method. is switched by the mask.

The common driver (6) receives timing signals TMG 1~
3, and based on the timing signal TMGB, selectively output different voltages, create a liquid crystal drive signal that sequentially selects the common electrode of the liquid crystal display device in a time division manner, and output it from the common output terminal (2). This is a common driver (6
) The timing signal T is controlled by the switching means provided with internal pressure.
The voltages selected by M01-3 and the timing signal TMGB are switched, and the liquid crystal driving method is selected. Details will be described later.

The power supply circuit Ql) boosts or steps down the voltage of the connected battery α based on the frequency divided output y4 from the frequency divider circuit Q@, and obtains a plurality of voltages V, , V, , ■. be.

For example, if the battery (12) is a silver oxide battery with an electromotive force of 1.5 V, the battery is 0, and the grounded power supply ■flD
A voltage (2) is connected between the line and the power supply line and is doubled by the power supply circuit (11).

(-3, OV) and the voltage Vs (4,
5■) is obtained. Also, the battery θ gong is the electromotive force 3. In the case of an OV lithium battery, the battery Q is connected between the power supply vDf+ line and the power supply ■8□ line, and the voltage V, (-1, A voltage V3 (-4.5 V) which is boosted by 5% is obtained. In addition, the power supply vDI+ line is grounded, and the power supply ■8B
, the line has a voltage V, (-1,5V), but the power supply V8s!
Voltage ■ (-3, OV) is supplied to the line, □Power supply■. , the voltage VsC-4,5V) is supplied to the switching means CH14.
When B(7), lc&'i[pressure v2 (-3, OV) is supplied. Here, the switching means CH14 is for switching the voltage supplied to the power supply 883 according to the liquid crystal driving method, and in the case of the 5-bias delivery method,
In the case of other methods, it is connected to B.

Further, the switching means CH14 is connected to the power source 1 as a mask during the manufacture of a semiconductor integrated circuit, or as a terminal for externally connecting a capacitor for boosting the voltage. , and power supply V. , terminals are provided, so switching can be performed by connecting these externally.

Furthermore, the explanation will be made using FIG. 2 (al (bl). FIG. 2 (at is the segment driver (3)
(4H51, a specific circuit diagram of the display signal switching circuit (force and timing generation circuit (8)), and FIG. 2(b) is a circuit diagram of the common driver (6).

FIG. 2(a) At K, the segment driver (3) is P (-MOS F E To, 31 (141 to N-M
OS FET (15) is a so-called clocked inverter consisting of a P-MO8FETαηH and a segment driver (4).
This is a clocked inverter consisting of T (19121). P-MO8FETQ of segment driver (3)
3) Source is power supply VT, connected to D line, N-M
/-2 of the OSFET (16) is connected to the power source v, , line, and the output is connected to the terminal B of the switching means CH13. On the other hand, the P-MOSFET of the segment driver (4)
(The source of lη is connected to the power supply VDD line,
The source of the OSFET (a) is connected to the power supply -1, and the output is connected to the segment output terminal (1). The segment driver (5) is an N-MO8FETC! whose drain is connected to the terminal A of the switching means CH13. I) and N-M
OS F E TCi! ]) whose source is connected to the substrate of N-MO8FETCI! Thirst and N-MOS
It consists of N-MO8FETC231 whose drain is connected to the substrate of N-MO8FETC231
MO8FBTO! I) (') Source and N-MOSFET
The timing output CHGVS of the timing generation circuit (8) is applied, and the drain pressure at the time is N-MO8F, ET.
The sources of (c) are power supply v, 1. connected to the line.

Here, N-MO3I"ET (2) is N-MOSFE
When T (21) is on, the potential of the substrate becomes the source potential, and the N-MOSFET (c) becomes the N-MOSFE.
It biases the power supply v,,3 so that the substrate potential does not go in the forward direction when T (21) is off, and the voltage is actually supplied to the segment output terminal (1) by the N-MO8FET QI. ).

In addition, the display signal switching circuit (output of power, that is, display data is output via a level shifter)
Q4), N-MO8FETQI, and N-MOSF
The display data inverted by the inverter (c) is applied to the N-MO8FET.
Q-type P-MOSFET0gI, N-MOSFET (2
]) is applied to the gate of (company). Furthermore, P-MOSFETQ71 and N-MOS of the segment driver (4)
A timing signal TMGB is applied to the gate of the FET [, while the P-MOSF of the segment driver (3)
A timing signal inverted by an inverter (4) is applied to the ETQ3) and the N-MOSFET (gate of 161) K. Therefore, the displayed data is at ■□ level (
(hereinafter referred to as "1"), P-MOSFETα4
andhiN-MOSFE'r(t5)c,t7
Therefore, P-MOSFETα and N-MOSFETα
Since the scratch is turned on, the timing signal TMGB is inverted at the output of the segment driver (4), and the amplitude is the same as the power supply ■
The drive signal between □ and ■8.3 is output, while the display data is between ■3. level (hereinafter referred to as "0"), P-MOSFETQ4) and N-Mo5FETQ! 1
9 is turned off, the timing signal TMG is output from the segment driver (3), and the P-MOSFET (18) and the N-MOSFETal are turned off.
It is in phase with B and the amplitude is the power supply■. A drive signal between 6° and 6° is output. On the other hand, N − of the segment driver (5)
MOS F E TCI'l), the display data is '0'
It turns on when , and outputs the voltage generated by the timing signal CHGVSIC.

The display signal switching circuit (7) receives timing signals TMG1.
2.3 and inverter CI! ? ) @ (To) A transmission gate (To) consisting of C31C (1) C3a, which is controlled by a timing signal inverted at (To)), is provided with display data Sn-+ corresponding to the segment at the input of the transmission gate (To) C3]) C321. ,5B-t,5
n-ss are respectively applied, and each output is wired-OR connected. That is, when the timing signal TMG1 is 1", the display data Sn-+ is switched and output; when the timing signal TMG2 is 1", the display data 3n-t is switched and output; 1'', display data 5n-s is switched and output.

In addition, the power supply of the display signal switching circuit (7) is vDD and 1. □
It operates by

The timing generation circuit (8) includes a D-FF (C) (incorporated) and a D-FF (C) which constitute a counter that further divides the frequency divided output Oa of the frequency divider circuit a selected by the switching means CHI. )
(2) Based on the output of timing signal TMGI, 2.3
Create NOR Goo) 051 (31'OC3η (To)
and inno(-ta) 431, and the timing signal CHGVS
selectively supplying the power supply V,... and Vaaz to N-
M OS F E T (41 (41) and each N - M
N-MOSFET (4:l (44)) connected to the substrate of OS FET<41<41
It consists of 451.

The branch output S- is applied to the clock input 0 of the I)-FF (c), and the output Q of the T)-FF (c) is applied to the NOR gate 0, as well as the D-FFC34). is applied to the input of Furthermore, the output Q of the D-FFC (3) is connected to the terminal B of the switching means CH3, and the terminal A is connected to the D-FF
It is connected to the output Q of c3a, and either one is connected to D-
The human power DIC of FF (g) is applied. Furthermore, D-FF (
2) reset terminal R1 and terminal B of switching means CH2
The initial clear signal MR is connected to the terminal A, and the output ζ of the D-FFC (3) is connected to the terminal A, and one of them is applied to the reset terminal H of the D-FF (Incorporated). In addition, the output Q of D-FF (B) is connected to the terminal A of the switching means CH4, and the terminal B is connected to the power source ■8□ line, and either one is NOR (G5)C'1C
37). The output of the NOR gate (to) is applied to the NOR gate (36), and the initial clear signal MR is applied to the input of the NOR gate (to). The timing signal TMGI is the switching means CI.
- NOR gate 0 connected to terminal A by I 6
Either the output of the NOR gate connected to the terminal A or the power supply vDD connected to the terminal B is selected, and the timing signal TMG2 is switched to the output of the NOR gate (to) connected to the terminal A or the Connected power supply ■,
One of □ is selected, while the timing signal TMG
3, the output of the NOR gate 07) is inverted by the inverter clLJ and output. Here, the switching means CH2
, CH3, and CH4, terminal B is selected in the case of the static method and maximum bias maximum duty method, and terminal A is selected in the case of the feedback bias duty method and the included bias duty method. When terminal B is selected, D
The output Q of -FF (G) is an output that divides the frequency-divided output by &voltage, and the output Q of D-FF (Found) is not used.On the other hand, when terminal A is selected, D-FF@ 3 forms a ternary counter, and the output of the NOR gate 0ω (to) and the output of the inverter are cyclically sequentially converted into pulses of "1" in synchronization with the cycle of the branch output Oa. Become.

Further, in the switching means CH5 and CI-I6, terminal B is selected only in the case of the static method, and terminal A is selected in the case of other methods.

On the other hand, the branch output Oa is applied to the gate of N-MOS FET (4m) (43 (44)) via the level shifter (46), and the branch output inverted by the inverter @η is applied to the N-MOS FET (4m) (43 (44)). (40θ2 (40θ2) is applied to the gate of 4-powder and output as timing signal TMGB. Therefore, N-MOSFET song (41) alternately turns on and off in synchronization with branch output Oa, so the timing signal CHGVS is the timing signal T
At the same frequency as MGB, it becomes an alternating signal between power supplies η,1 and ■□.

In addition, the common driver (6) has its source connected to the power supply vDD line and its drain connected to the common output terminal (2).
C frame and each source is the power supply■8. ．． Line, ■8゜2
N-MO8FET connected to the line s vsss line and whose drains are commonly connected to the common output terminal (2)
4 ahaυ and an N-MOSFET (4g1 connected to each substrate of the ring, N-MO8FET1 to prevent the substrate from being forward biased).
13 & 164) ei! 19, and timing signals TMG1, TM01.7MG3, T
NAND gate (a) 6 to which MGI3 is selectively applied
′? ), AND gamegoo59031(',1), and
The decoder section includes a NOR gate Ia 13. P-MOSFET (NAND for 4 camphor gates)
The gate side output is applied, and the N-MOSFET (416
The output of the NOR gate is connected to the level shifter I at the gate 2.
4) and an inverter, and the output of the level shifter is further applied to the gate of N-MO8FETf5 (to). Also, N-MOS F E TRI
) is applied with the NAND game H goo output via a level shift inverter can, and the N-MOSFET51
The output of the NOROR gate is applied to the gate of 54) via a level shifter IT) and an inverter. ) output is N-MOSFET5
Also applied to the first gate. In addition, in FIG. 2 (bl), since the voltage selection section connected to the common output terminal (2) is completely the same for each of the common drive signals COMI, C0M2, and C0M3, the common drive signal C0M2 ,
The voltage selection section of C0M3 is omitted.

Further, a timing signal TMGB is applied to one input of the NAND gate (a) via an inverter,
One input of the AND game) has a timing signal T.
MGB is applied, and common drive signals COMI and C0M2 are applied to the other inputs of the NAND gate 7), respectively.
, C0M3, the timing signals TMGI, TM
01.7MG3 is applied. On the other hand, AND Gamegoo E
The timing signal TMGB connected to the terminal A and the power supply ■ connected to the terminal B are selectively applied to the switching means CH7, CH9, and CHII to the AND gate (to) 6D, and the switching means CH7, CH9, and CHII are selectively applied to the AND gate (to) 6D. Means CH8, CHIO1CH1
2&C Therefore, the timing signal TM connected to terminal A
GB or one of the power supply VDD connected to the terminal B is applied via the inverter ff (II).

In addition, the AND game 6'1lIlυ corresponding to the common drive signal COMIK has a timing signal TMG2.
and 7MG3 are applied, and corresponding to the common drive signal C0M2) 686910) If) K is applied with the timing signals TMG1 and TM01, while,
ANDNO gate 6 corresponding to common drive signal C0M3
60) II) includes timing signals TMG1 and TM0.
1 is applied. Also, all AND gates ff1
lH5! An initial clear signal MR is also applied to the terminal (Jllll).

Here, in the switching means CH7 to CH12, terminal A is selected in the case of the 3-bias noise duty method, and terminal B is selected in the case of other methods. When terminal A is selected, P -MOSF E T (a9, N -
MOS FET (4150eiυ) ON and OFF are controlled based on timing signals TMG1-3 and TMGB, but when terminal B is selected, the output from the first floor of the NOR gate is always "1". So, N-MO8FETe
i(It is always off.

As described above, in the embodiments shown in FIGS. , the connection state of the terminals of the switching means CH1 to CH14 in each method is
As shown in the figure.

Each method is selected by preparing a plurality of masks for wiring each element, etc. when manufacturing a semiconductor integrated circuit, and switching the wiring of switching means CHI to CHI 4 as shown in FIG. .

Next, the operation of each system in the embodiment shown in FIGS. 1 and 2 (al(b)) will be described below.

(1) Static method FIG. 4 shows a waveform diagram of each part in this method.

As shown in FIG. 3, in the case of the static method, the switching means CHI is connected to the terminal A, and the frequency division output Oa is the output of the frequency division circuit a. , for example, a 32 Hz signal is generated. On the other hand, since the switching means CH14 is connected to the terminal B, the power supply ■. The 3rd line is supplied with the same voltage as the power supply vs s 2nd line. In addition, the switching means CH4, CH5
, CH6 is connected to terminal B, so the timing signal T
MG1 is 1", timing signal TMG2 is 60", and timing signal TMG3 is initial clear signal '
0", it is fixed at s+ On, and the timing signal TMGB becomes an inverted signal of the frequency-divided output that alternates between the power supply VDI and the voltage v2. Therefore, the common drive signal C
In the common driver (6) that outputs OMI, switching means CH7 and CH8 are terminals B, and timing signals TMG2 and TM01 are both 0'', so NO
The output of the N-MOSFET is 1".
(4!1 Jat) is always off.

On the other hand, the output pressure of the NAND gate (A) to which the timing signal TMGl at the 1" level is applied is the timing signal T'MGn, and the output of the NAND gate 67) is the timing signal TMGB, -MO3
FETl! i+) is a level shift inverter 16)K
Therefore, since the inverted timing signal TMGB is applied, the P-MO8I"ET decoy and the N-MO8FET6υ alternately turn on and off, and the common drive signal C0M
1 is in phase with the timing signal TMGB, and is a signal that alternates between the power supply VD+ and the power supply ■, l13, that is, the voltage V2. On the other hand, in the common driver (6) that outputs the common drive signals C0M2 and C0M3, the switching means C)I9
and the power supply selected by CHll. In other words, since the output of the AND game is 1'' and the timing signal TMGI is applied with ``1'', NOR is applied.
Only the gate output is 60″, other NAND
The output of gate (to) 67) and NOR gate 6 is 61
”, only the N-MOS FET (4910) is turned on, and the common drive signals C0M2 and C0M
3, power supply ■s8□ is output.

On the other hand, since the switching means CH13 is connected to the terminal B, the output of the segment driver (5) is connected to the segment output terminal (
1). Further, the i signal switching means (7) outputs the display data Sn-+ by the timing signal TMG1.
is selected and output. This display data 3n-+
When is '1', the P-MO8FETQ4) and the N-MOSFET (L!19 is t), and the segment driver (3) becomes inoperative. On the other hand, the segment driver (4) inverts the timing signal TMGB and outputs a segment drive signal Segn that alternates between the power supply vDD and the power supply V, . . . (ie, voltage V2). In addition, when the display data 3n-+ is 0'', the segment driver (4) is inoperative, and the segment driver (3) is in phase with the timing signal TMGB, and the power supply VD+ and the power supply V
,. (ie, voltage V2), the segment drive signal Segn is outputted alternately.

(2)''/2 Bias Station Datey Method FIG. 5 shows the waveforms of various parts in this method.

As shown in FIG. 3, in the case of the current bias station date system, the switching means CHI is connected to the terminal B, and the divided output 96
A frequency-divided output y0, for example, a 64 Hz signal is generated at a. In addition, the switching means CH14 is connected to the terminal B, and the power supply
,,3 line has power supply v0. The same voltage ■2 is supplied. Further, switching means CH2, 3, 4 are connected to terminal B, and CH5, 6 are connected to terminal A. Therefore, the timing signal TMG1 is an inverted signal of the output Q of I)-FFp31, and the timing signal TMG2 is an inverted signal of the output Q of I)-FFp31.
The output Q of c) is output, and the timing signal TMG
3 becomes 0''. Furthermore, the timing signal TMGB becomes an inverted signal of the level-shifted frequency-divided output.

For common driver (6), switching means CH7 to CH
12 is connected to terminal B. Therefore, common drive signal C
In the common driver (6) that outputs OMI, when the timing signal TMGI is 1'', the output of the NOR gate 1313 is 1'', and the N-MOS F E
T (496 chants are turned off. On the other hand, NAND gate (
b) Timing signals TM-σ1 and TMGB are output to the outputs of 6η, so the P-MOSFETs (4 frames and N-MO8FETeil) are turned on and off alternately, and the common drive signal COMI is the power supply vDD and the power supply V,, s (ie, voltage ■) are generated alternately.

At the timing when the timing signal TMG2 is "1", N
AND gate (4) 6? ) output becomes 1”, and P −
MOS FET (48 and N-MOS FET
Since Te1ll is turned off and only the output of NOR game'li becomes '0', N-MOS FET (41) is turned on and the common drive signal COMI becomes the power supply ■68.

On the other hand, in the common driver (6) that outputs the common drive signal C0M2, the operation is completely opposite to that described above, and when the timing signal TMGI is '1'', the NOR
Only the output of Gamegoo 3 becomes 0", and N-N08FE
T(41 is turned on, power supply V, □ is output, and
At the timing of the timing signal TMG2 1", N
The AND gate (a) also outputs η as the timing signal f.
Since it is f1-van and TMGB, P-MOS F
E T (4119 and N-MO8FET51) are turned on and off alternately, and the power supply ■D0 and the power supply V=-sc, that is,
voltage Vt ) are output alternately.

Furthermore, in the common driver (6) K that outputs the common drive signal C0M3, the output of the NAND gate (a) 6η to which the timing signal TMG3 is applied is always 11", and the power supply VDD is switched by the switching means CH12. Since it is selected, the output of NOR game 3) is also '1'. On the other hand, the output of the NOR gate 13 is always ["0" at the timing of the timing signal TM01hz"1" and the timing when the timing signal TMG2 is "1".
”, N-MO8FETG19 is turned on,
The common drive signal C0M3 becomes the power supply ■8□.

In addition, the display signal switching circuit (the power is the timing signal TMG)
When 1 is '1', display data 3B-+ is selected and output, and when timing signal TMG2 is '1', display data 3n-t is selected and output, but since timing signal TMG3 is '0', , display data 3
H-s is not output.

At the segment output terminal (1), since the switching means CH13 is connected to the terminal B, the output of the segment driver (5) does not appear as the segment drive signal SegnK. When the output of the display signal switching circuit (7) is 1", P-MO
8FET Q4) and N-MOS FET (+51 are off, the segment driver (3) is inactive,
The segment driver (4) inverts the timing signal TMGB and outputs the power supply vtlD and the power supply Vs-s (i.e., the voltage Vt
), and outputs an alternating signal between the display signal switching circuit (when the force output is 0", the P-MO8FET α mark and the N-
MO8FETal is turned off and the segment driver (
4) is inoperative, while the segment driver (3) inverts the timing signal TMGB and connects the power supply VDD and the power supply V
-st (ie, voltage Vt).

The segment drive signal Segn shown in FIG. 5 is when the display data 56-t is 1", the display data 5n-t is 0", and the timing signal TMGI is 1".
When the timing signal TMG2 is '1', the signal is in phase opposite to the timing signal TMGB, and when the timing signal TMG2 is '1', it is a signal in phase with the timing signal TMGB.

(3) Civilian duty method FIG. 6 shows waveforms at various parts in this method.

As shown in FIG. 3, in the case of the bias bias data type, the switching means CHI is connected to the terminal C and the divided output Oa is connected to the terminal C.
For example, a frequency-divided output signal of 128 Hz is generated. In addition, the switching means CH14 is connected to the terminal B, and the power supply ■,...
The line is supplied with the same voltage ■2 as the power supply ■, s2.

Furthermore, the switching means CH2-C) (6 is connected after the terminal AK. Therefore, the timing signal TMGI is connected to the D-FF (C)
The timing signal TMG2 becomes the AND signal of the inverted signal of the output Q of the D-FF and the inverted signal of the output Q of the D-FF.
It becomes an AND signal of the output Q of FF (13) and the inverted signal of the output Q of D-FF (b), and furthermore, the timing signal TMG
3 is the output Q of the D-FF (b), which has the waveform shown in FIG. Further, the timing signal TMGB is a signal obtained by level-shifting and inverting the frequency-divided output z8.

Therefore, the common driver (6) that outputs the common drive signal C0M1 is powered off at the timing when the timing signal TMGI is 1'', as in the case of the rare bias maximum control system. is outputted alternately, and the voltage v, II 1 is outputted at other timings.

In addition, the common driver (6) that outputs the common drive signal C0M2 also outputs the power supply ■DD and the power supply v0. (i.e., the voltage V2) at the timing when the timing signal TMG2 is 1'', similarly to the progress bias & data system. is output alternately, and at other timings, outputs the power supply V.. On the other hand, the common driver (which outputs the common drive signal C0M3)
6) is NAN when timing signal TMG3 is “1”
Since the timing signals TMGB and TMGB are respectively output to the output of the D gate (A) 6η, at this timing, the power supply ■. and power supply V,. (that is, the voltage Vt) is outputted alternately, and at other timings, only the output of the NOR game 3 becomes '0', so the power supply V. is outputted.

In addition, the display signal switching circuit (the power is the timing signal TMG)
When 1 is 1”, display data “”F3n r
When the timing signal TMG2 is '1', the display data 5n-t is selected and output, and when the timing signal TMG3 is '1', the display data 5n-s is selected and output.

As in the case of the bias progress data system, when the output of the display signal switching θ control force is 1", the segment driver (3) is inactive, and the segment driver (4) inverts the timing No. 46 TMGB. Outputs alternating signals of power supplies v, , D and power supplies V, , (that is, voltage Vt), and displays display signal switching 1 omitted (when the force output is 0'', the segment driver (4) is inactive E) Then, the segment driver (3) inverts the timing signal TMGB and turns on the power supply ■.

and the power supply Vs-z (ie, the voltage Vt). Segment drive signal Segn shown in FIG.
is the waveform when the display data 3n-+ and 5n-t are 0'' and the display data Sn-s is 11'', and when the timing signals TMGI and TM01 are 1'', the segment drive signal Segn is Signal T
The signal is in phase with MGB, and is in opposite phase with timing signal TMGB at the timing when timing signal TMG3 is 1''.

(41" 6 bias ξ date system FIG. 7 shows waveforms at various parts in this method.

As shown in FIG. 3, in the case of the ξ bias midity method, the switching means CHI is connected to the terminal C and the frequency divided output Oa
A frequency-divided output 08, for example, a 128 Hz signal is generated. Moreover, since the switching means CH14 is connected to the terminal A,
Unlike the above, voltage ■8 is supplied to the power supply ■1.3 line. Therefore, power supply ■8. ．． Different voltages V+, V2, and ■ are supplied to the line, power source ■1, line, and power source Vsss line. Further, the switching means CH2 to C)16 are connected to the terminal A, and the timing signals TMG1, TM01, TM01 and TMGB are connected to the seventh
As shown in the figure, the signal is the same as that of the progress bias/data system described above.

Therefore, in the common driver (6) to which the switching means CH7 to CH12 are connected to the terminal AK, the common drive signal CO
In the common driver (6) that outputs MI, when the timing signal TMGI is 1'', the output of the NAND gate η has the timing signals TMGB and TMG.
B are output respectively.

Therefore, when the timing signal TMGB is 1'', P-
MOSFET (N-MO8FET when Tsukuda is turned on and outputs the power supply VDD, and the timing signal TMGB is 0")
6υ turns on and outputs power supply VI1.3. At the timing when the timing signal TMG2 is 1'', the output of the NOR gate 621 becomes the timing signal TMGB due to the AND gate to which the timing signal TMGB is applied, and the AND gate to which the timing signal TMGB is applied becomes the output of the NOR gate 621.
Therefore, the output of the NOR gate l1l) is the timing signal T
Becomes MGB. Therefore, the timing signal TMGB is g″
When it is 1", N-MO3I"ET (to) is turned on, the power supply ■o is output, and the timing signal TMGB is 0".
When , N-MO8FET191 is turned on and the power supply V,
, , is output. Also, the timing signal TMG3 is 1
” timing signal TMGB is similarly generated at the output of VcNOR gate 6, and NOR game 13)
Since the timing signal rMan is generated at the output of , the common drive signal COMI is similarly generated by alternating the power supplies ■s, 2 and ■s□.

Common driver (6) that outputs common drive signal C0M2
) is also busy, and when the timing signal TMG2 is "1", it alternately outputs the power source V and the power sources 6 and 3, and at other timings, the power source V. , and Vol are output alternately. Similarly, the common driver (6) that outputs the common drive signal C0M3 also outputs the timing signal TMG3.
The power supplies VDD and Vsss are alternately output at the timing when is 1'', and the power supplies V□2 and ■.1 are alternately output at other timings.

Display signal switching circuit (the power is the timing signal TMGI, 1MG2, TMGB as in the most biased Tododay system)
At the timing when becomes 1'', display data 3n-+, Sn-
output w, 5n-s.

In the case of the direct bias duty system, the output of the segment driver (5) is connected to the segment output terminal (1) by the switching means CH13. In addition, when the timing signal TMGB is 1'', the timing signal CHGVS is connected to the N-MOSFET (411), which is turned on and the power supply V turns on and the power supply 'vI1
．． ．． is output.

Therefore, in the case of the display signal switching circuit (force output car 1"),
N-MOS FET (21) is turned off and P −
MOS FET(tllD and H-MOS F
E T (1m year old 7t) segment driver (4
J inverts the timing signal TMGB and outputs the power supply VD+,
and Vs s s, and on the other hand, the display signal switching circuit (when the power output is
FET (l mallet and N-MO8FETQI are turned off and the segment driver (4) is inactive, but N-
MOSFETCI! I) is turned on, the segment output terminal (1) is connected to the power supply ■o1 and V8. , a timing signal CHGVS is output that alternates between .

The segment drive signal Segn shown in FIG.
When GI and TM G2 are “1”, the power supply V
It is an alternating signal between 11 and V8112, and when the timing signal TMG3 is "1", it becomes an alternating signal between the power supplies V, 9□ and ■□3.

As described above for each liquid crystal driving method, one of the liquid crystal driving methods can be selected by selectively connecting the switching means CHI to CH14 as shown in FIG.

(F) Effects of the Invention As described above, according to the present invention, when manufacturing a semiconductor integrated circuit, a plurality of masks are prepared for wiring each element, and the connections of each switching means are selectively connected using the masks. By doing so, various liquid crystal drive methods can be selected, which has the advantage of enabling rapid production in response to the demands of semiconductor integrated circuit users and greatly reducing development and design costs.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 (a
) (bl is a circuit diagram showing the main parts of the block diagram shown in FIG. 1, FIG. 3 is a diagram showing the connection of the switching means when selecting the liquid crystal drive method, FIGS. 4, 5, and 5. Figures 6 and 7 are waveform diagrams showing the operation of each liquid crystal drive method. Explanation of main figure numbers (1)...Segment output terminal, (2)...Common output terminal, (3) ) f4) (51...Segment driver, (6)...Common driver, (Power...Display signal switching circuit, (8)...Timing generation circuit,
(9)...Oscillation circuit, 00)...Frequency dividing circuit,
01)...Power supply circuit, (121...Battery. 7th tA Dibias 'Af''x-T method (Voo=O, Vss
+=V+, Vss2=V2. Vss3=V3) 6th

Claims (1)

[Claims] 1. In a semiconductor integrated circuit having a plurality of segment output terminals and a plurality of common output terminals for directly driving a liquid crystal display device, a plurality of segment drivers provided for each of the segment output terminals, and a plurality of segment drivers provided for each of the segment output terminals; A display signal switching circuit that selectively applies one of the plurality of display data to the plurality of segment drivers according to a timing signal, and a frequency division output output from a frequency division circuit that divides the frequency signal from an oscillation circuit or the like. a timing generation circuit that generates the plurality of timing signals based on the timing signal and applies a liquid crystal drive frequency signal to the plurality of segment drivers; a common driver to which a driving frequency signal is selectively applied; switchable connection between the plurality of segment drivers and the segment output terminal; switching between the cycle of the timing signal or fixing the signal; and the common driver and the timing. A semiconductor integrated circuit having a liquid crystal drive circuit that enables selection of different liquid crystal drive methods by selecting signal and switching connections using a wiring pattern mask of the semiconductor integrated circuit.