JPS60209792A - Alloter for musical sound generator in electronic keyed instrument - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an L consonant system synthesis device;
In particular, the present invention relates to a device for allocating a limited number of tone generators to iυ keyboard switches.

Description of the Prior Art c ↑ The current trend in using microelectronic tone generators for keyboard-operated instruments is to use fewer tone generators than the number of keyboard switches in an h-switch keyboard arrangement. This has led to the development of systems that provide some savings. Assignment logic is implemented to assign a tone generator among the available tone generators to the key switch when the key switch is pushed into its activated key switch state. An inevitable resource availability problem arises when all tone generators are assigned to key switches and additional key switches are activated.

There are several allocation systems in place to address resource availability issues. One of the earliest allocation systems was US Pat. No. 2.57 entitled "Electronic Chestnut Machine."
No. 7.493. In this disclosed system, multiple analog oscillators are activated to connect a multicontact set to a hammer switch.
5et) by the snake switch contacts. This assignment operation also introduces a preselected capacitor so that the assigned oscillator generates a signal whose fundamental frequency corresponds to the assigned and actuated key switch. The assignment system disclosed in this patent, mentioned by reference, does not teach any means for dealing with the situation where all tone generators are assigned and additional key switches are activated.

A musician has 10 fingers, so if you consider -1
It seems that 10 tone generators for each 5B are sufficient.Modern keyboard instruments have two or more tone generators assigned to each finger movement. This musical sound effect has been given the general name ``sustain.'' Unfortunately, this terminology has caused some confusion. That is, the current usage of envelope modulation refers to the ADSR (Attack/Decay/Sustain/Release) time envelope modulation function. More properly, °´Sustain″
The old term for ``longrel'' is now ``longrel''.
With a long release, you can release one key switch with one finger.
lease)L activate another key switch,
On the one hand, it is much easier to leave the first tone generator activated and automatically reduce the volume by means of its ADSR envelope modulation function.

A tone generator allocation system intended to solve resource availability problems when long release modes are implemented for specific keys is disclosed in U.S. Pat. .61
No. 0,806.

In the disclosed system, the tone generators follow the normal assignment order of attack, decay, and release as long as unassigned tone generators are idle and available for assignment. Once all the tone generators have been assigned, the system automatically enters the adaptive Zasudin mode, in which the hand CM M' with a long release effect is assigned a note associated with one hammer of the earth. ) (note) A tone generator that is supplying a waveform with the longest duration of its envelope modulation release phase will have a relatively similar release from long release while still using exactly the same predetermined envelope modulation function. immediately switched to

The inherent problem with the tone generator assignment logic system is that
1) in a way where the allocation logic is inconsistent with the way the musician expected.
Their tone generator allocation logic system is ideal in the sense that a fairly general music system created by i1 appears.

Summary of the Invention U.S. Patent No. 4,085,044 (Specifically, 1
1-093519), calculation cycles and data transfer cycles are performed repeatedly and independently to provide data that is converted into musical waveforms. A transfer cycle is started after each individual word count cycle and the stored main data set is transferred to the number of note registers (no.
te registers). There is one note register associated with each of q4'It occurrence 2:÷. These tone generators are assigned to activated keyboard switches.

The data stored in the note register corresponding to one musical tone generator is read out repeatedly at a memory advance rate corresponding to the fundamental frequency of the musical note associated with the actuated keyboard switch.

The tone generator assignment subsystem operates in the normal manner of assigning tone generators to actuated keyboard switches until all available tone generators have been assigned. Once all tone generators have been assigned and additional keyboard switches have been activated, the assignment system enters the kill operating mode (ki
during this mode, the most previously assigned tone generator is assigned to the most recently actuated keyboard switch, and at the same time this tone generator is placed in the zero tone output state. . This kill mode is automatic and is independent of any previously actuated switch openings. Tone reduction is performed by a phase cancellation process in which each data point in the main data set pool for the most previously assigned tone generator is reduced to a small constant value.

3. DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to a tone generator in a multitone generator to prevent loss of tone when all available tone generators are assigned and a new keyboard switch is actuated. This musical tone generator uses a discrete Fourier transform algorithm (algorithm).
hm) is incorporated into a type of musical instrument that synthesizes musical sound waveforms by implementing. This type of musical tone generation system is disclosed in U.S. Pat.
It is described in No. 085, No. 644 (Japanese Patent Application No. 51-093519). This patent is hereby provided for reference only. In the following discussion, all elements of the system described in the patents mentioned by reference are identified by two-digit numbers that correspond to identically numbered elements appearing in the patents mentioned by reference. Ru. System element blocks identified by three-digit numbers correspond to system elements added to a polytone synthesizer, or to combinations of several elements that appear in the patents mentioned by reference.

Figure 1 shows U.S. Patent No. 4,085,644 (%
Figure 1 illustrates an embodiment of the invention described as a modification and addition to the system described in US Pat. The polytone synthesizer described in the patent to which reference is made includes an array of keyboard switches 12. When one or more status board switches are actuated to change the switch state (into the switch position of "PON"), the tone detection and assignment device 14 changes state to the activated state. ::j encodes the switch and stores the corresponding note information for the actuated switch. Of a set of tone generators included in the system block labeled Tone Generators. One is assigned to each station switch created using the 1-1"j-information generated by the tone detection and assignment device 14.

A suitable tone detection and assignment subsystem is described here for reference in the United States 4.022.
It is described in No. 098 (Japanese Patent Application No. 51-110652).

When one or more key switches are actuated, the execution control circuit begins a repeating series of calculation cycles. During one part of each calculation cycle, a main data set containing 64 data words is calculated and stored in main register 34. The 64 data words of the main data set correspond to the 64 data words of one period of the audio waveform for a musical tone generated by the corresponding one of the musical tone generators included in the system block labeled musical tone generator 100. Corresponds to the amplitude of equally spaced points. The general principle is that the harmonic maximum θ of an audio tone spectrum is only the number of data points in one complete waveform period. Therefore, a main data set containing 64 data points corresponds to a maximum of 32 data points.

U.S. Pat. No. 4,085,644, which is mentioned for reference.
As described in Japanese Patent Application No. s1-093519, the occurrence of the problem occurs while the activated key remains in the activated or pressed state on the salmon board. It would be desirable to be able to continuously resubtract and store the main data set during a series of repeating calculation cycles and load this data into a note register associated with the tone generator.

U.S. Pat. No. 4,085,644, which is mentioned for reference.
By the method described in Japanese Patent Application No. 51-093519, the harmonic counter 20 is initialized to its minimum or zero count state at the beginning of each calculation cycle. Each time word counter 19 is incremented by execution control circuit 16 and returns to its initial or minimum counting state due to its modulo counting implementation, execution control circuit 16 generates a signal that increments the counting state of harmonic counter 20. let The word counter 19 is implemented to count modulo 64, which is the number of data words of the main data set. The harmonic counter 2o is implemented to count modulo 32 1, this number corresponding to the maximum harmonic number consistent with the main data set containing 64 data words.

At the beginning of each 13'' cycle, the accumulator of adder-accumulator 21 is initialized to a zero value by execution control circuit 16. Every time word counter 19 is incremented 4σ, adder-accumulator 21 is Add the current state of counter 2o to the total value contained in the accumulator, this addition being carried out modulo 64.

The contents of the accumulator of adder-accumulator 21 are used by memory address decoder 23 to access trigonometric sinusoidal function values from sinusoidal function table 24. The sine wave function table 24 is 0 in the interval θ<64
Advantageously, it is implemented as a fixed memory storing the value of the trigonometric function 5in (2πθ/64) for . D is a table analysis constant.

The multiplier 28 multiplies the trigonometric function value read from the sine wave function table 24 by the harmonic coefficient read from the harmonic coefficient memory 26. Memory address decoder 25
reads the harmonic coefficient from the harmonic coefficient memory 26 in response to the count state of the harmonic counter 20. The product value created by the multiplier 28 is given to the adder 33 as a single-handed operation.

The contents of main register 34 are initialized to a zero value at the beginning of a calculation cycle. Each time the word counter 19 is incremented, the contents of the main register 34 at the address corresponding to the count state of the word counter 19 are read and provided as input to the adder.

The sum of the inputs to adder 33 is stored in the main register at a memory location equal to or corresponding to the count of word counter 19. As word counter 19 cycles through a total of 32 cycles with 64 counts per cycle, main register 34 contains the main data set.

After each computation cycle of the repeating series of n cycles, a transfer cycle is initiated and executed. During the transfer cycle, please refer to U.S. Pat.
．． The main data set is transferred from the main register 34 to the note register associated with the tone generator in a manner similar to that described in Japanese Patent Application No. 085.644 (Japanese Patent Application No. 51-093519). The main data set stored in the note register is read out repeatedly at a memory advance rate determined by the associated note clock.

The read data value is converted into an analog signal by the D-=A converter 47 and provided to the audio system 11.

Sound system 11 includes a conventional amplifier and speaker combination arrangement.

Figure 2 is “for reference only, U.S. Pat.
2.098 (Japanese Patent Application No. 51-110652) shows the logic added to this panel switch detection/allocation device 14. Blocks marked with a two-digit number correspond to blocks marked with the same number in the patent mentioned for reference. Note detection and encoder 300
is the state in which a mysterious switch state change is detected and a newly activated key switch is assigned, @! Assignment word including board number, octave number and note number within the octave
Contains subsystem logic encoded in The encoded assignment word is stored in assignment memory 82 in response to data provided by memory address/data write circuit 83.

When an assigned data word is read from assigned memory 82 in response to address data provided by memory address/data input circuit 83, event sequencer 115 determines whether the assigned data word has been assigned to the one switch activated. Arrange the assigned data in a time order corresponding to the time order. This order provides immediate access to the oldest assigned data word corresponding to the oldest actuated direction switch. Each assigned data word corresponds to a corresponding tone generator contained in the system logic block labeled tone generator 100. A detailed description of the operation of the event sequencer is provided below.

Event sequencer 115 determines when the assigned data word is assigned in response to actuation of a key switch included in the system block labeled instrument keyboard switch 12.
The allocated data words read from allocated memory 82 are stored in a memory arrangement that is ordered by a time history. Time is counted from the moment the assigned data word is encoded into the assigned state. All tone generators are assigned and additional kills (K
ILL) signal is generated. In response to the generation of the kill signal, the assigned data word corresponding to the oldest assigned tone generator becomes available to tone generator 100 for assignment to the most recent additional key switch. When a kill signal is generated, the tone generator corresponding to the oldest assigned data word is rapidly brought to a zero tone output state. This operation occurs even if the corresponding row switch remains depressed in its activated key switch state.

Furthermore, the corresponding note cannot be replayed until the hold switch is first released and then activated again.

FIG. 3 illustrates a method for reducing the tone output from a selected tone generator in response to a kill signal. The volume reduction is achieved by pointwise addition (POI) of two identical waveforms that are out of phase with each other.
nt wise addition). The phase difference between these two waveforms changes until complete waveform cancellation occurs. When the complete state of cancellation is changed, essentially the tone generator ceases to function to generate output tones. With this method, a clicky click (1<ey click) caused by a sudden stop of a musical tone
” can be avoided.

The main data set is calculated in the manner described above and the main register 3
4 is stored. During a transfer cycle, the primary data set is transferred to note register 35 and transferred to subordinate note register 104. Each tone generator includes both a note register and a subordinate note register. FIG. 3 explicitly shows the logic for one tone generator. It is understood that this logic is also replicated for each of the other tone generators.

The main data set is read from the note register 35 at a memory address rate determined by the frequency of the associated note clock 37. The memory address decoder 102 reads the main data word in response to timing information provided by the note clock 37. Address out.

If there is no kill signal, then data selection circuit 1
06 adds any of the data words read from the dependent note register 104 to the adder 105 . or other similar adders associated with each of the tone generators.

The generated address ranges from its maximum decimal value of 64 (binary logic state 63) to its minimum 1 (decimal value 1 (binary logic state O)).
, the address decoder 102 adds (A
DD) signal. In this manner, the first main data set word of the stored main set is stored in the note register 35.
An addition signal is generated every time an address is output from the address.

In response to the kill signal, the contents of the accumulator of phase adder-accumulator 107 are reset to a zero initial value. Each time address decoder 102 generates a sum signal, phase adder-accumulator adds the phase constant provided by phase constant generator 108 to the contents of its accumulator. Phase generator 108 may be implemented as a fixed memory containing preselected constants.

Phase adder 103 generates a memory address number equal to the address produced by address decoder 102 plus an offset number that is the current value of the contents of phase accumulator 107 .

When a kill (n'-Q occurs), the tone generator explicitly shown in FIG.
The main data Serato word read from 4 is transferred to adder 105. Adder 105 performs point-wise addition of the main data word read from note register 35 and the main data word transferred by data selection circuit 106 . The net result is that the input catator to the DA converter 47 contains the sum of two out-of-phase identical waveforms. Therefore, the maximum image width of the resulting waveform is from note register 35 to NIi,
The issued main data set word remains unchanged\D-A
The width is smaller than the maximum width that occurs only when the image is transferred to the converter 47.

Phase Adder - If the value contained in the accumulator of accumulator 107 is equal to or less than the bow of the number of main data set points defining one complete period of the musical waveform, then A redundant cancellation occurs, and literally only the data value is added.
Occurs in the output of xos. At this time, a DONF signal is generated and sent to the transliteration detection/allocation device 14.

Phase Adder - When the output of the accumulator first reaches the number h of data points in the main data set that defines one complete period of the musical waveform, or exceeds the number of data points i for the first time, Dan No. 48 uses the comparator Created by 109.

Figure 4 is for reference only, U.S. Patent No. 4.022.0.
98 (Japanese Patent Application No. 51.-110652) shows a system logic block added to the system logic block for the tone detection/allocation device 14 described in Japanese Patent Application No. 51.-110652. The purpose of the added logic is that when a DONE signal occurs and a newly actuated key switch can be immediately assigned to an available tone generator, the oldest assigned tone generator is This is to make it unallocated.

In the absence of the DONE signal, note generator removal circuit 110 transfers the assigned data word provided by memory address/data write circuit 83 to assigned memory 82.

When the dan signal is present (in the binary to 1 tr 16 state), the note generator removal circuit 110 outputs the comparator 1
11 (CLEAR) (Since it changes the input assigned data word in response to g, it is assigned to the assigned memory 82.
It is encoded and unassigned before being stored in the .

When the kill assigner 101 generates a kill signal, the assigned data word corresponding to the oldest assigned tone generator is provided to the kill assigner 1i 101 by the event sequencer 115. This time, the kill allocation device 101 transfers this allocation data order to the comparator 111. When the 611 data word provided by the kill allocator 101 is equal to the current allocated data word read from the allocation memory 82, a clear signal is generated by the comparator 111. U.S. Patent No. 4.022.098 stating
As described in the issue (!IH Tsume Sho 51 110652), the jjjI1 of the tone detection/assignment device i'114
(Even if the oldest activated σ1! switch is pressed open 1\, the same award will be given even after the kill allocation device has made the musical tone generator previously assigned to ^11 unassigned. Since musical tone generators are not assigned to switches,
It operates so that the musical tone generator cannot be assigned to a newly activated dance switch. This i3 product was published in U.S. Patent No. 4,022,098 (!1
Glands 86 and 87 shown in Figure 2 of 0652)
This is done according to the system layout shown above. signal 8
7 also appears in FIG. 2 of the present invention. To make a new assignment of tone generators, the signals on both lines ``line'' and 87 must be in the '1' binary logic state.

When it is detected that one key switch has changed its switch state since the previous data scan of the keyboard, line 8
6 has a binary logic state of "P1". This key switch changes from a deactivated state (mystery "off") to an activated state, indicating that an unassigned tone generator is currently present. When an allocated data word encoded for is read from allocation memory 82, line 87 has a P1'' binary logic state.

When the oldest heel switch remains pressed,
Because heald 86 has a '0' binary state, the assignment system will not assign a tone generator to its oldest stray switch.

FIG. 5 shows an alternative embodiment of the invention. In this alternative system arrangement, one step is required to phase cancel any one of a set of tone generators 100 designated to be released by operation of kill allocator 101.
Only one waveform register is used.

The address signal provided by kill assignment device 101 is used by data selection circuit 115 to select address decoder 102 or the output of address decoder 112 and provide the selected address to phase adder 103 . Fifth
Although the figure explicitly shows two tone generators, the system can be easily extended to any desired number of tone generators with one. The address signals from the kill allocator 101 are also used by the data selection circuit 113 to select the main data set words read from the note register 35 or the note register 36 and add those main data set words.
): Power the vessel 105. The main data set input to data selection circuit 113 that is not selected for transfer to adder 105 is provided to DA converters 47 and 48. If a kill signal is not generated by the kill allocator 101, the data selection circuit 113 operates in the normal manner and transfers the main data set read from the note register 35 to the D- converter 4.
7, and the main data set read from the note register 36 is transferred to the DA converter 48.

The phase data read from the slave register in response to the address data provided by phase adder 103 is added to the selected note register data by adder 105. The summed data is converted into an analog tone waveform by a DA converter.

Removing the oldest assigned tone generator in response to a new activated key switch when all available tone generators have been assigned is an ADSR (Attack/Decay/Sustain/Release) envelope. This is done without interference by or interaction with the modulation function generator. If the oldest assigned tone generator is reassigned to a new key switch by the method described above, that tone generator is immediately assigned to the newly actuated key switch. At this time, the ADSR generator associated with the newly assigned tone generator will be activated once the oldest assigned tone generator has been "killed" (made available for reassignment) and newly activated. It simply begins a new attack phase independent of the ADSR envelope modulation phase that may have existed when the key switch was reassigned.

FIG. 6 shows another alternative embodiment of the invention. In this example, first things first! If all available tone generators are currently assigned without reducing the loudness of the old assigned tone generator by 1'L, a new assignment will be made to the newly actuated Z switch. It is done against. Figure 6 is a reference to U.S. Patent No. 4.022.
098 (Japanese Patent Application No. 51-110652) (1 block is shown).

U.S. Patent No. 4,022,098 (Japanese Patent Application No. 51-110
652) and is mentioned for this reference.
As shown in FIG. 1 of FIG.
t; A logic state occurs. 1: J! so is °゛1″′1″
'When state 42 becomes "1"state;1], state F/
F118 is set. When the upper NR'L division bell switch is being scanned, the memory 42 is in the °゛1''1'' state. Although the description of system operation is given for a single keyboard, expansion of the system to multiple keyboards does not result in duplication of the same system logic functions.

Status F/1"118 is set and its output state is Q="
1”, the musical tone generator counter 117 is activated by the division decoding circuit (division decode).
116 can be counted.

The signal on line 42 goes from an "O" binary logic state to a "1"
Upon changing to a binary logic state, the tone generator counter 117
is reset to zero initial value.

Division decoding circuit 116 decodes the allocated data words as they are read from allocation memory 82. When the assigned data word corresponds to a 1 for the upstream Tivision (corresponding to the "1" state on line 42), a signal is sent to increment the count state of the tone generator counter.

If the signal on line 87 is in the 'O' binary logic state, no operation will be initiated by the assignment subsystem shown in FIG. 6. When it is detected that the needle has changed to the needle switch state, approximately 187 becomes the binary injection state "°1'".The line 87 becomes 1" in the binary logic state and the foot line 42 becomes "'1".
When in a binary logic state, andcate 120 is t 1
z+ logic signal is generated and this signal is applied to comparator 119.

Once the tone generator counter 117 has been incremented to the maximum number of tone generators available assigned to the upper keyboard (corresponding to the signal on nff 142), the comparison is made in response to the I l +l logic signal from the AND gate 120. 119 generates a kill signal. The comparator 119 generates a kill signal by comparing the count state of the tone generator counter 117 with the number of internally stored musical tone generators that are available to the maximum number of tone generators assigned to the upper keyboard. A kill signal in the "1" binary logic state means that it has been detected that all available tone generators have been assigned to the bank keys and a new lock switch has been activated.

In response to the "1" logic state for the kill signal, the event sequencer 115 sends the assigned data word for the oldest assigned note generator for the upper keyboard to the note generator removal circuit (
note generator remove ) 1
Give to 10. Note generator removal circuit 110 temporarily stores all assigned data words provided by event sequencer 115 in response to a kill signal in a register.

The same assigned data word as the assigned data word stored in the note register 110 is stored in the memory address/data write circuit 83.
The next time the DONg signal is present, the status bit changes to the unassigned state before the assigned data word is stored in the assigned memory 82. Therefore, the next time the upper ridge or upper keyboard is scanned, the tone generator can be assigned to the newly activated key.

It should be noted that this allocation system does not require modification of the ADSR envelope function generator.

The newly assigned tone generator has its ADSR envelope function starting at the normal attack phase.

As long as the oldest activated key switch remains stuck in its activated state, no mor111'f generator is applied to it.

This behavior has already been explained. When this blunt switch is opened and the key is pressed 11 times, the tone generator cannot be assigned to this C+ switch.

Another alternative embodiment of the present invention is to have the ADSR redundant immediately open the oldest tone generator in response to a kill (n). This same concept is carried out by using a kill signal to advance the speed at which the last digit or release phase is coupled for the oldest assigned note occurrence z:;.This same concept can be applied to any It is also easily implemented for tone generators that are 1% associated with other keys. It is used to create the signal caused by the switch function and the activation signal.

In FIG. 7, there is a label labeled ADSR generator 121.
AI) S shown in the system logical block
3 shows a system allocation logic using the allocation concept of the present invention in conjunction with an R generator; A suitable embodiment for ADSR generator 121 is disclosed in U.S. Pat. No. 4,075,650 entitled 'ADSR Generator'.
It is described in This patent is mentioned here for reference.

Musical tone generator counter 17 is up “1” ff1i! When incremented by the number of system sound generators available for assignment to the board,
Comparator 119 generates a kill signal in response to a "1" binary logic state signal from 120, the presence of which causes all available tone generators to reproduce on the upper keyboard. 1j and a new hammer switch was activated.

In response to the kill signal, the event sequencer 115 sends the assigned data word of the oldest assigned note generator on the upper keyboard to the note generator removal times 1lli' 1110 and A.
It is given to the DSR generator 121. Note generator removal circuit 1
10 temporarily stores the assigned data word provided by the event sequencer in response to the kill signal.

In response to the kill signal, ADSR generator 121 immediately places the envelope generator corresponding to the assigned data word provided by event sequencer 115 into release envelope transformation 1 phase. ADS corresponding to this assigned data word
If the R generator has previously been assigned a long I/IJ-time, the release time will be short M. When this tone generator completes its A]) S R envelope pre-release phase, the release time will be cleared. A signal is generated.

When both the kill signal and the clear 1 word occur, AND gate 122 generates a binary "i"fji'l:l state signal. The output from 122 is i
T? fi”:: “1” state, no l-
Generator removal circuit 110VLc The same allocated data word as the stored allocated data word is memory address/data: 1;
The next time the data word is returned to the embedding circuit 83, it is encoded to indicate the unallocated status and stored in the allocation memory 82. In this way, the next time the upper keyboard is scanned, the tone generator will be available to assign to the Xl'r-actuated key switch.

FIG. 8 shows the detailed logic of event sequencer 115. For illustrative purposes, this subsystem is described for the case where four tone generators are available for assignment to the upper keyboard. This does not represent a limitation of the invention, as it is easily extended to any desired number of tone generators.

A new assigned data word is written to the assigned memory 8 by the data word given by the memory address/data write circuit 83.
2, the new word is provided as an input to gate 210.

The mode signal consists of 2 bits. m, is the MSB (most significant bit), and m2 is the LSB (rl), the lower bit). The mode signal has the following control states: m1m2 +111 creation 0 0 No action 0 1 Add new data word.

1 0 Release existing data words.

U.S. Pat. No. 4,022,098, which is mentioned for reference.
As described in Japanese Patent Application No. 51-110652, when a new musical tone generator is assigned, the tone detection/assignment device 14 generates a 1'' (cj) on the line 87. signal can be used for the LSB m2 of the mode signal. Also, as described in the same patent mentioned above, when the tone generator assignment is revoked, a signal appears on line 86. The signal on 86 can be used for the MSBm+ of the mode signal.

When note generator removal circuit 110 determines that a previously allocated tone generator has been released (left in an allocated state and encoded into a corresponding allocated data word), the corresponding allocated data word is released. It is transferred to the gate 201 as a data signal labeled data.

As discussed below, the oldest assigned data word after the sorting operation appears in the first word position of data shift register 202 and the most recent assigned data word is stored in register 205.

Clock 211 generates timing signals, these timing signals are used to increment a counter;
It is also used to shift data out of the data shift register. Data shift 1/register and register 205 essentially operates as a circular shift register that reads data from one end and reinserts it at the other end. Data is data shift register 20
2, a new assigned data word is read into data shift register 202 by gate 1-204 in response to an add (ADD) signal on line 241 and a release signal on line 242.

Addition of allocated data words also decreases (depletion)
If neither occurs, a zero signal is sent to both gates 201 and 210. A zero signal is a data word that can be provided by a signal line in which all bits are zero and placed at a "0"' binary state level.

As each assigned data word is read from data shift register 202, that assigned data word is compared with the assigned data word transferred by gate 201.

This comparison is performed by comparator 203. If the input assigned data words are equal to each other, the comparator 203 outputs an equal value (EQ
UAL) signal.

In response to the binary "1" logic state for the enable signal, seven lip-flop F/F2O3 is set so that its output signal Q is placed in the binary logic state "i".

Each time counter 407 returns to its minimum counting state due to its modulo counting implementation, flip 70 tube F/F 208 is reset. Counter 207 is implemented to count modulo 4, which is the number of tone generators used to indicate the operation of event sequencer 115.

Details of the logical operation unit 209 are shown in FIG. The logical operation unit 209 calculates an equal value (EQU) according to the following logical relationship.
RELEASE= which generates an add (ADD) signal on line 241 and a RELEASE signal on line 242 in response to the AL) signal and flip-flop 208.
(m1m2 equivalent value (m1m2 (equal f[+Q)) Equation 1
Add n-ml m2 (equal value + Q) Equation 2 Table 1 shows that the old assigned data words are N1 and N2 and the new assigned data word N8 is assigned and stored corresponding to mode signals m1=0 and m2-1. It describes system operation for illustrative examples that may be included in the device.

Table 1 Counter 207 Status ab Shift Register Register 205 E Ql 01 NINgo 0 00 2 01 N200 N1 00 3 00 0ONI N2 10 4 0 1 0NIN2 N8 01 1 01 NlN2N3 0 00 1lii% Fa used in the above table Ha a
- Addition, b = Nirelise E = ■ value. counter 20
It should be noted that in fk state 4 (highest number of 7) a new assigned data word is stored in register 205.

Also, each time the counter 207 reaches its minimum count state, the oldest assigned data word is stored in the data register 2.
Appears in the output of 02. In this case, Nl is the oldest assigned data word.

Table 2 shows that the assigned data words are for mode signals = 1 and m2.
-0 indicates system operations that are initiated after the operations listed in Table 1 are removed from event sequencer storage.

Table 2 Counter 207 Status ab Shift Register Register 205EQ1 01 NlN2N3 0 00 2 01 N2N11ONl 10 3 1ONaON1 0 01 4 11 ON+Na O01 1, 01N+Ns0 0 00 When the counter 207 reaches its count state 2, the assigned data word N2 data shift 1 / comes to the first word position of register 202. In count state 3, allocation data fR
7N2 is read from data shift register 202 and is found to be equal to the data transferred by game 1-201 which is destined to be removed from event sequencer 115 memory. When the count state 4 of the counter 207 is reached, the addition on line 241 =, ``1'' weight scale responsively the assigned data word N8 is inserted by the gate 204 into the last position of the data shift register. When a period starts or a count state of 1 is reached, the assigned data words recorded in the register 1. are in the correct order for the assigned time. The assigned data word N2 has been removed, filling the gap in the register storage sequence. is closed.

The allocation data Wt (number expansion is the expansion of the count state for the counter 207 and the data shift register 20
This is done by simply having a corresponding number of memory storage locations in 2.

Embodiments of the present invention will be listed below.

1. The tone generator state means includes a tone generator counter that is incremented by each detected data word, and responsive to the counting condition of said tone generator, and generating additional data when said counting condition reaches a prespecified maximum value. and comparator means for generating a kill signal in response to a detected word.

2. The tone generator removal circuit comprises: a data detection memory means; and a data detection memory means which stores each of said detected data words in a chronologically ordered arrangement in which a key switch corresponding to each of said detected data words is actuated. said arrangement includes event sequencer means for identifying an oldest detected signal; and, responsive to said kill signal, replacing said oldest data detected signal stored in said data detection memory means by an additional data selection word. and theta substitution means.

3. having a keyboard arrangement of key switches, calculating a plurality of data words corresponding to the amplitudes of points defining the musical sound waveform during each of a series of calculation cycles, and calculating a plurality of data words corresponding to the amplitudes of points defining the musical waveform during each of a series of calculation cycles; a key switch state detection means for generating a detection signal in response to each actuated key switch in said keyboard array of needle switches, said key switch state detection means being associated with a keyboard instrument for transmitting to said plurality of musical tone generators; encoding means for encoding the signal and generating detection data words identifying each said actuated key switch corresponding to a generated detection signal; and said plurality of data words corresponding to amplitudes of points defining a musical waveform. a plurality of musical tone generators each generating a musical sound waveform in response to the plurality of data words calculated by the calculation means; assigning device means for assigning one of the musical tone generators to generate the musical sound waveform at a frequency associated with a corresponding key switch included in the keyboard arrangement of key switches; tone generator state means for generating a kill signal when all of the tone generators of the tone generators are assigned and an additional data detection word occurs; and a detection data word responsive to said kill signal and provided to said allocator means; tone generator removal means for replacing the plurality of tone generators by said additional data selection word; A device for assigning the tone generator of the instrument to the actuated key switch.

4. The tone generator status means is responsive to the count status of a type generator counter incremented by each detected data word and the nineS tone generator counter;
ff1iJ Paragraph 3, above, comprising comparator means for generating said kill signal in response to said additional theta calculation (81) when said count state reaches a prespecified maximum f'Z.

5. The musical tone generator removing means removes each of the detected data words in an arrangement arranged in order of 1V1 voltage (time Qjl) when the '0 switch corresponding to each detected data word is activated. memorize the arrangement 1
'C is an event sequencer means for identifying the oldest data detection signal; and phasing means for reducing the width of the waveform to 1 and generating a done signal when said waveform reaches a minimum value.

6. Said tone generator removal means is responsive to said kill signal and responsive to said dump means for transmitting said data detection signal older than 17 to said stored and ordered data in said event sequencer means. The musical instrument according to item 5, further comprising data removing means for deleting data from the first order and adding the additional data detection word to the stored order H;

7. Each of the note generators includes: note memory means for storing the plurality of data words subtracted by the weighing means; subordinate memory means for storing the plurality of data words calculated by the calculating means; a note clock for applying a timing signal at a rate determined by allocator means; responsive to said timing signal, generating a repeating series of memory address numbers; and responsive to said memory address number, generating data from said note memory means; 21S2 memory addressing means for accessing data words from said subordinate memory means in response to said series of memoriat 1/snumbers; an adder for adding the data words read from the source and the data words read from the dependent memory means to form a summed series of data m; and converting the summed series of data words into an audible musical tone. and converting Toekki means.

8. The musical tone generator removing means further responds to the kill signal, generates the addition signal, and applies a musical tone to one of the plurality of musical tone generators associated with the oldest data detection signal. 8. A musical instrument according to clause 7, including generator selection means.

9. The second memory addressing means successively applies a preselected phase constant to the contents of the accumulator each time one of the series of memory address numbers of the first memory addressing means has a preselected value. an adder-accumulator for adding the contents of the accumulator of the adder-accumulator to each of the series of memory address numbers to create a phase sequence of memory address numbers; memory access means for reading the data word from the dependent memory means in response to the phase sequence; and in response to the contents of the accumulator of the adder-accumulator, when the contents of the accumulator reach a predetermined phase cancellation value. and comparator means for generating said dun signal.

1(), wherein said predetermined phase cancellation value corresponds to a number of data points stored in said note memory means.

1J-9rail i'my own words τy's hand is a waveform memo 7, a harmonic memory that stores one set of harmonic coefficients, a logic clock that provides a logic timing signal, and a musical waveform f: a point to be defined. A1'1 wave counter is incremented every 16iJ records corresponding to the wave 1'5'1 of the wave, and iiiI P
tc: fi: the high R in response to the injection timing signal
computer adder-accumulator means for initializing the contents of said accumulator directly to zero at the beginning of each of said series of automatic cycles; a sine wave function table for recording a set of trigonometric function values; and computer addressing means for extracting trigonometric function values from the sine wave function table in response to an internal bound of an accumulator of the computer adder-accumulator means. and harmonic addressing means for reading out harmonic coefficients from the harmonic memory in response to the counting state of the harmonic counter; and a trigonometric function value stored in the waveform memory at an address corresponding to the data stored in the waveform memory, and storing the summed value in the waveform memory to produce the point defining a musical sound waveform. A musical instrument according to paragraph 3 above.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of one embodiment of the invention. FIG. 2 is a schematic diagram of the sweat tone detection/allocation device 14. As shown in FIG. FIG. 3 is a schematic diagram of a tone level reduction system. FIG. 4 is a schematic diagram of the logic added to the tone detection and assignment device 14. FIG. 5 is an alternative embodiment of the invention. No. 6M is yet another alternative embodiment of the present invention. 7. [M+ is a schematic diagram of a combination of an ADSR generator and a Tl-tuning allocator. FIG. 8 is a schematic diagram of event sequencer 115. FIG. 9 is a logic diagram of the logic unit 209. In FIG. 1, 11 is an acoustic system, 12 is a musical instrument keyboard switch, 14 is a tone detection/allocation device (j, 16 is an execution i:i control circuit, 1
9 is a word counter, 20 is a harmonic counter, 21 is a caro-accumulator, 22 is a gate, 23 is a memory address decoder, 24 is a sine wave function table, 25 is a memory address decoder, 26 is a high-order '.] wave coefficient memory, 2
8 is a multiplier, 33 is an adder, 34 is main register 1, 17
is a D-A converter, and 100 is a musical tone generator.

Claims (1)

[Scope of Claims] 1. The keyboard arrangement of a large number of lock switches is combined with a percussion instrument having a plurality of tone generators smaller than the number of needle switches in the keyboard arrangement, and the keyboard arrangement of the key switches is d-switch status detection means for generating a detection signal in response to each actuated key switch; and encoding each said detection signal to identify each said actuated key switch corresponding to the generated detection signal. encoding means for generating a detected data word; and a plurality of musical tone generators configured to generate a musical tone associated with a corresponding key switch operated in the keyboard arrangement of key switches in response to each of said detected data words. allocating device means for allocating one of the plurality of musical tone generators to generate all musical tones, and musical tone generator status means for generating a kill signal when an additional data detection word is generated; tone generator removal means responsive to a kill signal to replace detected data words provided to said allocator means with said additional data selection words. Apparatus for assigning a tone generator of said plurality of tone generators to an actuated U-switch in such a way that it is always assigned to an activated key switch.