JPS60208145A - Data decision circuit - Google Patents

Abstract

PURPOSE:To attain accurate decision by selecting a threshold value for data discrimination based on the result of discrimination of the past data train of an input signal and changing properly each threshold value to the level fluctuation of the input signal so as to correct the value. CONSTITUTION:A signal from an input terminal 1 is compared with a threshold value selected (7a) of a comparator 2, outputted (3) and inputted to a shift register 4 so as to form a present data a(t) and past data a(t-1)...a(t-3) trains. The data a(t)-a(t-3) are inputted to a control circuit 5b and its output controls a switch 7b and a signal delaying (9) an output of a subtractor 8 so as to correct a threshold value generated by threshold value generating circuits 6a-6d. Furthere, the signals a(t-1) and a(t-2) are inputted to a control circuit 5a, one of threshold value generating circuits 6a-6d is selected and fed to a comparator 2 and the substructor 8. Then the threshold value is corrected corresponding to the fluctuation of the input signal level, the result is compared (2) normally so as to output (3) the result to accurate decision.

Description

[Detailed Description of the Invention] [Techniques of GT Mei (Fi field)] This invention provides a method for stably determining data of 7 digital transmissions 8 due to code amount interference due to band limitation. Related to circuits.

[Technical burial mounds of the 11th Ming period and their problems] In mobile communications (!) From the viewpoint of effective use of power resources, the narrowband Fhl system is being actively studied as a digital signal transmission system.
The demodulated waveform of the signal causes a large amount of code interference due to band limitation. Therefore, the error rate becomes large for a constant 87·'N. One way to solve this problem is to use the multi-threshold identification method (Reference 1: Technical Report of the Institute of Communication Engineers C382-
89p105-112 are known. This method prepares the threshold values of the primitives corresponding to different discrimination IQ phase differences, selects the optimal one threshold value based on the pattern information from the past discrimination results, and uses it as the judgment@value of the input signal data. The judgment, that is, the judgment of ``1'' and ``O'' is (j) method.

FIG. 1 shows the structure disclosed in Document 1. An example of setting the input signal trajectory and multiple threshold values #1 to #4 according to the contents of each data string is shown below. The threshold value is selected based on the determination results of the past two data strings. For example, the past two data string judgment results a (t-2) and a (t-1) are °
In the case of 11°', as shown in Fig. 2(a), the locus of the input signal is the judgment result a (t-2>, a (t-1 ), a (t>
, a(t+1> is '1111', '1110', '1
101” or “1100” as shown in the figure. In this case, threshold #1 is optimal for determining a (t). Even when the judgment results a(t-2), a(t-1) are 'oi', the same fil, -a(t2), a(t-1), a
(t) and a (t+1), the locus of the input signal changes as shown in FIG. 2(b), and threshold #2 becomes optimal. Similarly, a(t 2), a < t-1) is ' 10 ''
In the case of open chain #3. Also, in the case of 'o o', the threshold #
4 is optimal.

As a circuit that determines the data of an input signal using such a principle, Document 2: Institute of Electronics and Communication Engineers Technical Report C883
-7 As shown in p47 to p57, the determination result a(t-2) of the past 2-bit data string.

a(t-1), and based on this, four Plf
A circuit is known that selects one threshold value from ii11 to #4 and compares it with an input signal using a comparator to determine whether the data is '1' or 'O'.

However, when such a data determination circuit is applied to the determination of a received signal in a mobile radio communication device as described above, the following problem occurs.

However, on the transmitting side, the transmitted data is passed through a low-pass filter (
After narrowing the band through Lr'F), FM modulation is applied and transmitted, and on the receiving side, a frequency discriminator performs FMtl modulation,
Consider the case where a signal as shown in FIG. 1 is obtained by further integrating the 111M output, and the data is determined as described above. As a result, the error rate of the determination result obtained by 1q is significantly reduced compared to the case of determination using the A-threshold value as shown in Document 2. However, in reality, there are changes in the transmitted data on the transmitting side, fluctuations in the gain of the PF, and fluctuations in the demodulation sensitivity of the frequency discriminator on the receiving side.

The alternating current level of the signal fluctuates due to factors such as variation in the gain of the integrator. In addition, the i:i flow rate of the signal also fluctuates due to fluctuations in the transmission frequency on the transmitting side, fluctuations in the local oscillation frequency on the receiving side, and DC drift of the frequency discriminator. FIG. 3(a) shows the trajectory of the signal level when the AC level fluctuates, and FIG. 3(b) shows the trajectory of the signal level when the DC level fluctuates.

When the signal level fluctuates in this way, the margin between the thresholds becomes smaller, resulting in erroneous judgments due to small M sounds, increasing the error rate. As a result, correct transmission of data and audio signals becomes difficult. If you try to stabilize the frequency or keep the gain constant as a countermeasure to this,
There is a problem in that the hardware becomes large-scale and a large cost burden is imposed.

[Object of the Invention] The object of the invention is to stably and accurately determine the data of an input signal that has been subjected to code amount interference due to band limitation, such as a digital transmission signal using a narrowband FM method, regardless of level fluctuations. The object of the present invention is to provide an arc determination circuit that enables the following.

[Overview of Komei] This invention selects a threshold value for data judgment from a plurality of threshold values based on the judgment results of past data strings of the input 1, and selects each of the threshold values according to input signal level fluctuations. By adaptively changing and correcting the data, accurate data judgment can be made.

That is, in the data determination circuit according to the present invention, each of the plurality of threshold generation means each generating a different 1llll11 determines the input signal when the determination result when the input signal is determined using the respective generation threshold as the determination threshold is the first state. a calculation means for outputting a difference signal between the average value of the difference signal between the signal and the determination threshold and the average value of the difference signal when the determination result is in the second state as an error signal of the generation threshold; The present invention is characterized by having a correcting means for correcting the occurrence threshold in a direction that minimizes the occurrence threshold value.

[Effect of explanation] According to the present invention, even if the judgment threshold deviates from the optimum threshold due to fluctuations in the AC level or DC level of the input signal, the judgment threshold is corrected every time data arrives and converges to the optimum value. After convergence, it becomes possible to stably perform correct data judgment.

As a result, errors are significantly reduced and data transmission (
j The reliability of data is improved, and very high quality transmission of audio and image signals can be performed.

[Embodiment of the Invention] FIG. 4 is a diagram showing the configuration of a data determination circuit according to an embodiment of the invention. In the figure, a signal having a level locus as shown in Figure 1, which is obtained by FMII tuning and integrating a digital transmission signal based on a narrowband FM system on the receiving side, is input to terminal 1 as an input signal. . This input signal is supplied to the comparator 2, and its level is compared with the determination B value obtained as described later, thereby determining the data, and outputting the data signal 21i1 to the output terminal 3.

The judgment result of comparator 2 is further processed by 3 to select the judgment threshold.
It is supplied to the shift register 4 of the stage. If the input of this shift register 4 is a (t), shift 1 - register 4
In each row, the judgment result a (
t-1>, a(t-2), and a(t-3) are stored. Among these determination results, a (t-1), a
(t-2) is given to the first control circuit 5a, and a (t
), a (t-1).

a(t~2>, a(t-3) is given to the second control circuit 5b. The control circuit 5a has four threshold generation circuits 6a
Threshold 1aTH11, THIO where ~6d occurs.

The first switch 7a for selecting one threshold value from T H01 and T I-100 is controlled, and υ11i111i
1 corresponds to a second switch 7 b 8 IIJ which supplies a signal for threshold value correction to the threshold value generating circuits 6 a to 6 d. In other words, the output of the subtracter 8 for obtaining the difference signal between the input signal to the 1j terminal 1 and the determination threshold is supplied to the switch circuit 7b via the delay circuit 9 at an appropriate timing.

It is assumed that the polarity of the difference signal output from the p reducer 8 is positive when the input signal level is higher than the judgment threshold, and negative when the input tg''4 level is smaller than the judgment threshold (16).

Here, each of the threshold value generation circuits 6a to 6d is configured as shown in FIG. 5, for example. That is, the threshold 111R raw circuit has two input terminals 118.11b, and averaging circuits 12a and 12b average each input signal to obtain a temporal average value, and a subtracter 13 calculates the average value of both. Obtain the difference signal. Then, this difference signal is multiplied by 6 by the ¥1 picker 14, and then supplied to the adder 15 and added to the previous threshold 1111 which is the output of the delay port 2816, thereby outputting a new corrected threshold. It is configured to output to a terminal 17.

Next, the operation of this solid line example will be explained. Now, the judgment result a(t-2) for the past 2-bit data string.

Assuming that a(t, -1) is '11'', #1 out of @values #1 to #4 in the first diagram is optimal for one city between determinations, so the switch circuit 7a is connected to the control circuit 5a. By!
, +1 is controlled to select the 1dlf city Tl-111 of the 8 1111 generation circuit Oa corresponding to #1. This threshold value T + -111 is given to the comparator 2 as a determination threshold value.

Here, if this threshold value THII deviates from #1 in Fig. 2(a), for example, if it is at the position shown in Fig. 3(a) or (b), the deviation is detected and the threshold value 7H14 is set to the external pressure. be done. That is, the subtracter 8 sets the threshold 1 [Tl-111
A difference signal between the input signal and the input signal is detected, and this difference signal is delayed by a delay circuit 9 for a certain period of time. This delay time is the threshold 11
After 1THII is set as the determination threshold, this rA
lil! The judgment result for the 2-bit data string following the 2-bit data string corresponding to THII is a ratio of 1.2! ! l 2
This is set to the time required to obtain the output of the input signal, that is, the time approximately 1.5 times the data rate of the input signal. The switch 7b is controlled by the control circuit 5b so that iI! The difference signal of the output of the extension circuit 9 is applied to the two input terminals 11a of the threshold generation circuit 6a in response to the determination result of the data of two successive bits 1 to 1.

11b. For example, a(t~3).

a (t-2), a (t-1), a (t) is 1
When the signal becomes 110°', the switch 7b supplies the difference signal to the terminal iia, and when the signal becomes '1101', the switch 7b supplies the difference signal to the terminal 11b.

The difference signals thus supplied to the input terminals 118 and 11b are averaged by averaging circuits 12a and 12b, and a subtracter 13 roughly detects the difference between the two average values. That is, when the input signal is subjected to data judgment using the equivalence value TH11 as the judgment equivalence value, a(t-1> is the judgment result, and the following <a (t
) is '10' (first state).The average value of the difference signal between the input signal and judgment 1IiiiIiTH11 and its judgment #!5 East is '01°' (second state). .The average value of the difference signal between the input signal and the judgment all direct TH11 is detected.This difference signal is detected by the multiplier 1.
4 is multiplied by Δ, for example, 1, , / 2 (After being Qed, the interval 111iTH11 is corrected by being input to the adder 15. For example, as shown in FIG. 3(a), the threshold value #1 corresponding to THll is is above the optimal value, the average value (negative polarity) obtained at the output of the averaging circuit 12b is larger than the average value (positive polarity) obtained at the output of the averaging circuit 12a, so the subtracter 13 The difference signal of the output becomes negative polarity and is supplied to the adder 15 via the multiplier 14 and added to the previous threshold value, so that the level of the threshold value Tl-IN decreases and approaches the optimum value. By returning Ii! every time the same value TH11 is selected as the determination threshold, the threshold 1!Tl-111 is successively corrected and approaches the R appropriate value, and eventually converges.

Similarly, the difference signal obtained by the subtracter 8 is transmitted through the delay times n 9
a (t-3), a (t-2>
, a(t-1), a(t) is '0110'.

In the case of "0101", it is supplied to the input terminal 118.11b of the threshold generation circuit 6b, and "1010", "1o o"
i'', the input terminal 118.1 of the threshold generation circuit 6C
1b, "OO10", "oo.

In the case of 1'°, the input terminal 11a of the threshold value generation circuit 6d.

11b, the threshold generation circuits 6b to 6
Similarly, in d, the threshold values TH10 and THOI.

Make a correction of T+-100.

In this way, each of the threshold generation circuits 6a to 6d uses each generation threshold as a determination threshold when the determination result obtained when the input signal data is determined by the comparator 2 is in the first state and in the second state. The input signal and the judgment threshold in the case of the state
The average value of the two difference signals is determined, the difference signal between these two average values is determined, and the threshold value is adaptively varied in the direction in which the difference signal is minimized. This will optimize the decision equivalence.

That is, even if the level of the input signal fluctuates due to fluctuations in the DC level or AC level, the threshold generation circuits 6a to 6d correct the ldl value in accordance with the fluctuation, so that the same value can be determined. Since it is set optimally for the input signal level, stable and accurate data judgment is possible.

In addition, since noise components are removed by averaging the difference signal between the input signal and the judgment equivalency in the averaging circuit, stable judgment is possible even with respect to noise.

The present invention is not limited to the above-mentioned examples, and various modifications can be made without departing from the spirit of the invention. For example, although the data determination circuit shown in FIG. 4 is constituted by an analog circuit, a sample hold circuit and an A/D converter may be placed after the input terminal 1, and all subsequent processing may be performed by digital signal processing 11. In that case, the averaging circuit inputs N samples of the input digital difference signal to an N-stage shift register, adds the output values of each stage of this shift register, and divides by N to obtain an average value. be able to. Also, digital signals! In the case of Ill theory, it is also possible to perform averaging processing within each @@R regeneration white path on R11a8 with one averaging circuit, and transfer the two series digital difference signals to a 2NlllN shift register with N samples. All you have to do is input the value in minutes and divide the output value of each stage by the sum of t12N. In this way, a device corresponding to the subtracter 13 in FIG. 5 is also unnecessary. Another method of averaging is to add the samples of the input digital difference signals and calculate
New addition 1i by adding a new sample to multiplication (α 1)
It is also possible to divide 1s(t) by N and use it as an average value. Further, an O-bus filter can generally be used for averaging.

Roughly speaking, in the actual M example above, for example, the l1llIiR raw circuit 6a
) ↑, the occurrence m1liiTl-111 is judged as a (t-3), a (t-2), a (t-1)
, the average of the difference signals when a(1) is '1110' and '1101°' (corrected based on the direct difference, but '1111
Even if the threshold value T+-111 is modified based on the difference in the average value of the difference signal between ° and '1100', exactly the same result is obtained.
“To” 1111” and “1100”! The threshold ITH11 may be modified based on the difference in the e-fold signal average value,
In the case of , the averaging process will increase, but since more detailed corrections can be made, convergence to the optimal value will be faster.

Furthermore, due to the hardware modification, the judgment result is ゛111''
Calculate the difference between the average values of the difference signals when and '110' and calculate a(i
Even if IITHII is corrected, convergence will be slightly delayed, but once convergence is achieved, correct judgment will be possible.

Occurrence 8t in other threshold generation circuits 6b, 6c, 6d!
A similar modification is possible for the correction of 1TH10, THOI, and THOO.In short, the input signal data is judged by 11 at the judgment time tδ using each light body threshold as the judgment threshold.
In the case where the state of one to several bits of the judgment result is the first state, and in the 19th case of the second state. The @ value may be corrected by calculating the average value of the difference signal between the input signal and the determination threshold value, and then calculating the difference signal between these two average values.

Note that the value Δ multiplied by the multiplier 14 in FIG. 5 is 1, /
It is not limited to 2 and can be arbitrarily selected. If the value of
! The fluctuation of 111m will be less.

In the explanation above, the case where four atias are prepared is described, but the threshold value correction means of the present invention can be similarly applied even when there are more or fewer atias. For example, #1 and #2 in FIG. And the threshold values corresponding to #3 and #4 may be combined into one.

[Brief explanation of drawings]

Figure 1 shows digital transmission l! using the narrowband FM method. Figures 2(a) and (b) are diagrams showing examples of setting the determination thresholds, and Figures 3(a) and (b) are diagrams showing the level trajectory of the received signal III waveform and four types of threshold values used for data judgment. ) is a diagram showing the level locus when the AC level and DC level fluctuate, Figure 4 is a configuration diagram of the data judgment circuit of one embodiment for this light, and Figure 5 is the inside of the threshold generation circuit in the same embodiment. FIG. 3 is a diagram showing the configuration. 1... Input terminal, 2... Comparator (judgment means), 3.
...Output terminal, 4...Shift register, 5a, 5b.
...Control p circuit, 6a to 6d...Threshold value generation circuit, 7a
, 7b...Switch, 8...Subtractor, 9...Delay circuit, 12a. 12b...Averaging circuit, 13...Subtractor, 14...
- Multiplier, 15...adder, 16...delay circuit. Applicant's agent Patent attorney
)cl(t-2), d(t-f), act), a(
t+f) Figure 8 Figure 4 Figure 5 1.2゜Procedure Amendment (Method) % formula % Incident display IP! f Kensho No. 59-62124 Name of Invention Data Judgment Circuit RIA related to the person who makes corrections Patent Applicant (4221 Japan - Fake II Story Public Corporation (and 1 other person) Agent 〒105 Tokyo-to Port 1st Shibaura-j No. 11NI June 26, 1982 (shipment date) Drawings subject to correction Engraving of content map (2) of surface correction (Contents Kfj! Sushi)''■ That's all

Claims (2)

[Claims] (1) Continuous past data of input signals that have suffered from intersymbol interference due to band limitation from multiple @value light cow means that generate different threshold values, and threshold values that can be generated by these multiple threshold value generation means. An f-event consisting of a threshold selection means for selecting one threshold value corresponding to the judgment result of the column, and a judgment means for judging the data of the input signal using the open chain selected by the fil value selection means as the judgment amount 1. In the judgment review, the above? The input signal is determined by the determination means to determine the input signal by determining the value of each light 1; 1g, the judgment IIl value, the average value of the difference signal, etc., when the judgment result is in the second state, a calculation means for outputting a difference signal from the average value of 3 days as an error signal of the generation threshold; , and correction means for correcting the occurrence threshold value by 1 m in the direction in which the error signal outputted from the calculation means is at its minimum. (2) In the first state, 1 bit of the determination result is "1"
”, and the second state is a state in which the bits of the determination result are O'°. (3) The first state of rIff is a state in which two successive bits 1 and 1 of the determination result are 10', and the second state is a state in which successive two bits l of the judgment tl!i East are '0 1'. Ta judgment time 2/! .