JPS6020783B2 - information reproducing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information reproducing apparatus that reads and reproduces information from a magnetic card, such as a commuter pass, having an information track and a timing track.

Generally, in a magnetic card such as a commuter pass, as shown in FIG. 6, a timing track TT and an information track DT are provided almost parallel on a card C by magnetic recording.

The timing track TT is provided to set the timing for reproducing the information recorded on the information track DT, and normally, signals of logical value "1" are recorded at equal intervals.

Then, when the information reproducing device reads the signal "1" from the timing track TT, it determines whether the signal read from the information track DT is "1" or "0" and reproduces the information. It has become. Therefore, in an ideal case where signals are correctly recorded on the information track DT and the timing track TT and are correctly negotiated, the signal 0 obtained from the timing track TT as shown in FIG.
and signals 1 to n obtained from the first to nth information tracks DT.
The phase is completely matched. However, if there is a misalignment between the head that records timing signals on the timing track TT and the head that records information on the information track DT, or the head that records the timing signal on the timing track TT and the head that records information on the information track DT do not match. If there is a discrepancy in the alignment relationship with the head that refutes the information signal of , as shown in FIG. Some phase shift occurs between signals 1-n. Further, a phase shift also occurs when a card is taken or recorded while being oblique to the head. Conventional information reproducing devices detect phase differences tl to tn for each information track DT and correct them so that the phase differences become zero, or reproduce information within a predetermined time after reading a timing signal "1". It reproduced information by detecting the presence or absence of a signal "1".

In the former case, a complicated circuit is required, and the cost increases as the number of information tracks increases. In the latter case, if the information signal "1" is output before the timing signal "1" or if the scanning speed of the timing track TT and the information track DT, such as the card conveyance speed, decreases, the information signal "1" There was a drawback that ``1'' was played as ``0''. This invention was made in view of Mu's father's points, and has a simple configuration and is also a timing track TT.
Another object of the present invention is to provide an information reproducing device which is not affected by the scanning speed of an information track DT and can correctly reproduce information even if there is a slight deviation in the arrangement of a recording head and a recording head.

According to this invention, the information pulse of the information signal "1" is
It was stored in the storage means, the time from when the timing pulse of the timing signal "1" was output until the next timing pulse was output was counted by the time counting means, and based on the counted value, the time before and after the timing pulse was generated was counted. Since the control means causes the signal stored in the first storage means to be stored in the second storage means within a predetermined percentage of the value, there is a discrepancy between the recording on the timing track and the recording on the information track. , or even if the timing of timing pulses and the timing of information pulses are shifted in time due to a misalignment between the timing track head and the information track head,
If the deviation is within a predetermined percentage time of the count value of the time counting means, the information signal "11" can be correctly reproduced.

Further, according to the present invention, even if the conveying speed of the card changes, the counted value of the time counting means changes and the predetermined percentage time changes, and the timing of inputting into the second storage means is determined by the timing pulse. The interval is determined by a predetermined ratio, and the information can be correctly reproduced without being substantially affected by fluctuations in the conveyance speed. Moreover, according to the present invention, information with high recording density can be reproduced without requiring a complicated circuit. Embodiments of the present invention will be described below with reference to the drawings.

FIG. 4 is a block diagram of the information reproducing device. 1 is a pulse oscillator.

2 is a 4-bit counter that receives the output pulse output from the pulse oscillator 1 and increments.

Reference numeral 3 denotes a 4-bit counter that receives a pulse issued every time the counter 2 counts one pulse from the pulse oscillator 1 and increments.

Therefore, counters 2 and 3 can count 25 pulses. Registers 4 and 5 read and store the counts of counters 2 and 3, respectively, when a trigger input signal is input to the trigger input terminal T. 6 is a matching circuit that compares the "2", "4", and "8" outputs of the register 4 and the "1", "2", and "4" outputs of the counter 2, respectively, and outputs a matching signal when the signs of the corresponding outputs are equal. It is.

7 is the "1", "2", "4", "8" output of register 5 and "81" output of counter 2, and "1", "2", "4" of counter 3
This matching circuit outputs a matching signal only when the corresponding outputs have the same sign and is receiving a matching signal from the matching circuit 6.

Reference numeral 10 denotes an input terminal for inputting an output signal of the timing track head.

1 1 to ln are input terminals into which output signals of the first to nth information track recording heads are input.

20 to 2n are differentiating circuits that take out rising signals of pulses generated at input terminals 10 to ln, respectively.

The output signal of the differentiating circuit 20 is input to the reset input terminals R of the counters 2 and 3, and to the trigger input terminals T of the registers 4 and 5. The output signals of the differentiating circuits 21 to 2n are input to set input terminals S of RS flip-flops 31 to 3n, respectively. The coincidence signal outputted by the coincidence circuit 7 is supplied to the reset input terminals R of the RS flip-flops 31 to 3n, and is supplied to the reset input terminals R of the RST flip-flops 41 to 4n.
It is input to the trigger input terminal T of.

The RST flip-flops 41 to 4n each have an RS
The set output signals of the flip-flops 31 to 3n are received at the set input terminal S, the reset output signals of the RS flip-flops 31 to 3n are received at the reset input terminal R, and when the trigger input signal is supplied to the trigger input terminal T, the RS flip-flop The stored values of the groups 31 to 3n are loaded and stored. The set output signals of RST flip-flops 41-Z4n appear at output terminals 51-5n, respectively, forming an information reproducing device. Now, it is assumed that a fixed number of pulses from the pulse oscillators 1 to 18 are generated between when a timing pulse is generated at the input terminal 10 and when the next timing pulse is generated at the input terminal 10'.

When the count values of counters 2 and 3 reach 180, counter 2 outputs “4” and counter 3 outputs “1”, “2”, and “8”.
” output is “1” and other outputs are “0”, input terminal 1
A pulse is generated at the register 4 through the differentiating circuit 20.
Since trigger input signals are supplied to registers 4 and 5, registers 4 and 5 store the counts of counters 2 and 3, respectively. As a result, the "4" output of register 4 and the "1", "2", and "8" outputs of register 5 become "1" and the other outputs become "0". On the other hand, counters 2 and 3 are reset by a signal from the differentiating circuit 20 and start counting from 1 again. Note that the reset signal for counters 2 and 3 and the trigger signal for registers 4 and 5 are output at the same time, but before the count values of counters 2 and 3 are reset to zero, the count values of counters 2 and 3 are output to register 4, respectively. and 5. When a 9M fixed pulse is supplied to the counter 2 after the counter counters 2 and 3 are reset, the "2" and "8" outputs of the counter 2 and the "1" and "4" outputs of the counter 3 are "1", and the other outputs are "1". The output becomes "0".

At this time, the match circuit 6 contains "8" and "4" of the register 4.
The code “0101” is supplied from the “2” output, and the counter 2
The code "010" is supplied from the "4", "2", and "11" outputs. Therefore, a coincidence signal is supplied from the coincidence signal 6 to the coincidence circuit 7. On the other hand, in the matching circuit 7,
In addition to the match signal from match circuit 6, “8” of register 5
The code TIoII is supplied from the outputs "4", "2" and "1", and the code "1011" is supplied from the outputs "4", "21" and "1" of the counter 3 and the output "8" of the counter 2. Therefore, a coincidence signal is output from the coincidence circuit 7, and RST
A trigger signal is supplied to the trigger input terminal T of the flip-flops 41-4n, and the stored values of the RS flip-flops 31-3n are transferred to the RST flip-flops 41-4n. The playback signals are taken out from the output terminals 51 to 5n.
The coincidence signal output from the coincidence circuit 7 is supplied to the trigger input terminals of the RST flip-flops 41 to 4n, and at the same time,
Reset input state R of RS flip-flops 31 to 3n
is supplied to

However, RS Fritzpf. Before the flip-flops 31-3n are reset, the values stored in the RS flip-flops 31-3n are stored in the RST flip-flops 41-4n. As is clear from the above, in this embodiment, the RS flip-flops 31 to 3n, which store information read from the card via the differentiating circuits 21 to 2n, are reset when a coincidence signal is output from the coincidence circuit 7. Only when.

Incidentally, the coincidence signal is output from the coincidence circuit 7 when half the time from when a timing pulse is taken from the card until when the next timing pulse is taken has elapsed. Therefore, as shown in FIG.
The signals ``1'' generated at 1 to ln are stored in the RS flip-flops 31 to 3n, and when the coincidence signal is output from the coincidence circuit 7, the RST flip-flops 41 to 4n are advised, so that the card conveyance speed is Even if the speed differs from case to case, the mutual arrangement of multiple heads and the relationship between cards and heads are not affected by the difference in speed, and the mutual arrangement of multiple heads and the relationship between cards and heads are not affected by the difference in speed. Even if there is some deviation, the information can be corrected again. Note that 0 is generated between the generation of the first timing pulse and the generation of the next timing pulse.
In this case, the values stored in the registers 4 and 5 are the values stored when the card was read last time, and the matching circuit 7 does not generate a matching signal at the correct time.

To eliminate this, either a spare code is provided at both ends of the card, or only a timing code is recorded. FIG. 5 is a block diagram showing another embodiment, in which the number of information tracks is one.

Regarding FIG. 5, parts that play the same roles as those shown in FIG. 4 are given the same reference numerals and detailed explanations are omitted. In FIG. 5, numeral 8 receives a pulse output from the pulse oscillator 1 and advances, and also receives a coincidence signal from the coincidence circuit 7 or a signal from the differentiation circuit 20 via an OR circuit 30 and is reset. It is a bit counter. 9 indicates that the counter 8 receives the pulse from the pulse oscillator 1 by 1.
It is a 2-bit counter that is incremented by receiving a pulse every time the needle is counted, and is reset by receiving a coincidence signal from the coincidence circuit 7 or a signal from the differentiation circuit 20 via the OR circuit 30.

The Yamachi circuit 6 compares the "4" and "8" outputs of the register 4 and the "1" and "2" outputs of the counter 8, respectively, and supplies a match signal to the match circuit 7 when the signs of the corresponding outputs are equal. I get used to doing it.

In addition, the matching circuit 7 inputs “1”, “2”, and “4” of the register 5.
The "8" output is compared with the "4" and "8" outputs of the counter 8 and the "1" and "2" outputs of the counter 9, respectively, and if the signs of the corresponding outputs are the same and the match signal from the match circuit 6 is It is designed to issue a match signal only when it is receiving data. Therefore, the count values of counters 9 and 8 are
Each time the count value of counters 3 and 2 becomes one quarter of the stored value of register 5 and 4,
, 2/4, 3/4, and 4/4, the coincidence circuit 7 outputs a coincidence signal. 340 is a 3-bit counter that increments every time it receives a coincidence signal output from the coincidence circuit 7 and is reset by the output of the differentiation circuit 20. 50 is "1" of the counter 40 "
2" is an exclusive OR circuit which receives the outputs at its input terminals, respectively.

Reference numeral 60 denotes a differentiating circuit which takes out the rising signal of the exclusive OR circuit 50 and supplies it to the trigger input terminal T of the RST flip-flop 41.

70, the "1" and "2" outputs of the counter 40 are both "1"
This is an AND circuit that outputs a signal when .

480 is a differentiating circuit that takes out the rising signal of the AND circuit 70 and resets the RS flip-flop 31.

Now, assume that 180 pulses are generated from the pulse oscillator 1 from the time a timing pulse is generated at the input terminal 10' until the next timing pulse is generated at the input terminal.

When the timing pulse occurs at the input terminal 10, the registers 5 and 4 read the evening "10110100". At the same time, counters 2, 3, 8, 9, and 40 are reset.
After that, the count values of counters 9 and 8 become "45", that is, "
00101101'', the coincidence circuit 7 outputs a coincidence signal.

The coincidence signal output from the coincidence circuit 7 resets the counters 8 and 9 via the OR circuit 30, and also resets the counters 8 and 9 through the OR circuit 30.
The river is supplied. As a result, the counter 40 becomes "1".
The output becomes "1". At this time, "2" on the counter 40
Since the output is "0", exclusive OR circuit 5
RST flip-flop 41 via 50 differentiating circuit 60
The trigger input is input to RST flip-flop 41.
The memory value of the S flip-flop 31 is stored. Next, when the count values of counters 9 and 8 reach "45", matching circuit 7
A match signal is output from the counter 40, and the count value of the counter 40 becomes "2".

At this time, the "1" output of the counter 40 is "0" and is "2".
The output is "1", but the value of the counter 40 is already "1".
'', the exclusive OR circuit 50 was outputting a signal, so no signal is output from the differentiating circuit 60. In order to ensure this operation, a return delay circuit may be provided between the exclusive OR circuit 50 and the differentiator circuit 60. When the count values of counters 9 and 8 reach "45" for the third time, the count value of counter 40 becomes "3", and AND circuit 7
A signal "1" is output from 0, and the RS flip-flop 31 is reset via the differentiating circuit 80.

Therefore, in this embodiment, the signal generated at the input terminal 11 during a quarter cycle before and after the timing pulse is output is stored in the RS flip-flop 31 and stored in the flip-flop 41. In both of the above two embodiments, registers 4 and 5 are stored every time a timing pulse is generated so that the information can be read correctly even if the card conveyance speed fluctuates while reading the information written on the card. is changed, but if there is no possibility of large fluctuations in the card transport speed while reading a single card,
The time between timing pulses may be measured only once initially for each card.

[Brief explanation of drawings]

FIG. 1 is a waveform diagram showing an ideal information reading output, and FIG. 2 is a waveform diagram showing an actual information reading output. FIG. 3 is a waveform diagram for explaining the principle of the first embodiment of the present invention, and FIG. 4 is a block diagram of the first embodiment. FIG. 5 is a block diagram of the second embodiment. FIG. 6 is a vague diagram of a magnetic card. 1: Pulse oscillator, 2, 3, 8,
9, 40: Counter, 4, 5: Register, 6, 7: Matching circuit, 31 to 3n; RS flip-flop, 41 to 4n
;RST flip-flop; C; card; TT; timing track; DT; information track. Figure 1 Figure 2 Crocodile j Figure Groove Figure Groove 4 Figure Turning over

Claims (1)

[Scope of Claims] 1. A card carrying device that has an information track and a timing track that is provided substantially parallel to the information track and has a signal recorded thereon for timing the reading and reproduction of information recorded on the information track. In the information reproducing apparatus that reads and reproduces the information while being conveyed by the timing track, the time counting means counts the time from the generation of a timing pulse until the generation of the next timing pulse by reading the timing track. a first storage means for storing information pulses generated by reading the information track; a second storage means for reproducing information by reading the values stored in the first storage means; an information reproducing device comprising: control means for causing a second storage means to read the signal stored in the first storage means within a predetermined proportion of the count value before and after the timing pulse is generated based on the count value of the counting means; . 2. An oscillator that generates clock pulses, a counter that counts the clock pulses generated from the oscillator and is reset by the timing pulses generated by reading the timing track, and a counter that is reset by the timing pulses generated by the timing pulses. 2. The information reproducing apparatus according to claim 1, wherein said time counting means is constituted by a third storage means for reading numerical values. 3. The control means outputs a signal when half of the time counted by the time counting means has passed since the timing pulse was generated, and reads the signal stored in the first storage means into the second storage means. Claim 1, characterized in that the first storage means is reset at the same time as the first storage means is reset.
The information reproducing device according to item 1 or 2.