JPS60207364A - Manufacture of integrated circuit device - Google Patents

Abstract

PURPOSE:To form transistors having different thresholds value proper to a Schmitt trigger circuit, etc. extremely simply by preventing an execution to a low threshold value transistor of a shallow implantation during a forming process for an NMOS transistor. CONSTITUTION:A gate oxide film 13 is formed in an element region in a field oxide film 12 on a semiconductor substrate 11, and ions having the same conduction type as the substrate 11 are deep-implanted. Ions are shallow-implanted in an NMOS transistor formation prearranged region A. That is, a formation prearranged region B for a low threshold value transistor is coated with a resist 14, and ions having the same conduction type as the substrate 11 are implanted in the low quantity of dose. The resist 14 is removed, and gate electrodes 15A, 15B are shaped to predetermined sections on the gate oxide film 13. Accordingly, threshold voltage is brought to approximately 0V because impurity concentration in the vicinity of the surface of a channel on the low threshold transistor side is brought to approximately 0.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method of manufacturing an integrated circuit device including an LSI circuit with an MO8 configuration, and particularly relates to a method of manufacturing an integrated circuit device such as a memory, a microprocessor, etc. be.

[Technical background of the invention]

2. Description of the Related Art Devices such as memories or microprocessors must operate stably against noise in input signals, and some Schmitt trigger circuits are used as their input circuits. The eleventh is to convert such a Schmitt trigger circuit into a C
An example of a circuit configured with MOS (complementary MO8),
Figure 2 shows its input/output characteristics. In FIG. 1, an enhancement type P-channel MO8'rr, an enhancement type N-channel MO8Tra and an enhancement type N-channel MOS transistor TrB are connected in order between one power supply VDD and the other power supply VSS.
These are connected in series, their respective gates are commonly connected, and the input Vin is supplied to this common connection point. Then, the output Vout is drawn out from the connection point between the transistor Trl and the transistor Tr2, the gate of the enhancement type transistor Trc is connected to this connection point as a transistor for output potential feedback, and the connection point between the transistor Tr2 and the transistor TrB. is connected to the drain of the transistor Tr4.

In such a circuit, for example, when the input V in is at a high level, the transistor Tr1 is in an off state, and the transistors Tr2 and Tr3 are in an off state.
is in the on state. Therefore, the output Vout! 10-level. On the other hand, the gate of the transistor Tr4 has an output V
Since out is input, the transistor Tr4 is in the off state, and the input/output characteristics in this case are the transistor Tr4.
+, β of transistor Tr4 and transistor Tr3
The ratio (transconductance ratio) I determines this. In other words, when the input vIn changes from high level to low level, the above three transistors Tr+ m T
The circuit darkness value is determined by r2y Trs, and as shown in Figure 2, when Vin becomes 'Via = Vl, the output Vout
transitions from low level to high level.

Conversely, when the input Vin changes from low level to high level, the transistor Trl'' is in the on state, and the transistor Tr! and the transistor Trl are in the off state, so the output Vout is at the high level.

Therefore, the transistor Tr4 is in an on state, and the voltage VM at the connection point between the transistor Tr2 and the transistor Tr3 becomes high level. Voltage VM at this connection point
That is, the transistor Tr! When the voltage at the source end of T is at a high level, the substrate effect is effective and the transistor T
The threshold voltage of ry increases. Therefore, the circuit threshold value v2 in this case is larger than the value V when the input Vin changes from high level to low level, and the input/output characteristics have hysteresis as shown in FIG.

A circuit with such hysteresis in its input/output characteristics does not respond to a signal with an amplitude less than the hysteresis width Vh, so it is effective in overcoming noise in the input signal, and an input circuit using a Schmitts trigger circuit is a large-scale LSI
It is about to be widely applied to

[Problems with background technology]

By the way, input circuits such as MOS memories or microprocessors do not only function as normal input circuits (
, a function to convert TTL level input signals to MOS level is also required. Normally, when operating with a voltage of 5V, on the TTL side, 0.8V or less is a low level, and 2.0V or less is a low level.
V or higher) is considered to be level. Follow °Cs TT
In order to efficiently convert L level signals to MOS level, the threshold of the input circuit should be set to 1.5, which is approximately the middle of these potentials.
It is preferable to set the value around v.

However, as mentioned earlier, in the Schmitt trigger circuit shown in FIG. Therefore, it is difficult to set the center value of the threshold of the Schmitt trigger circuit to around 1.5V.

Therefore, the present inventors made it possible to set the threshold of the Schmitt trigger circuit to a preferable value by making only the +iA value of the transistor Tr2 lower than that of the other transistors, for example, an intrinsic type MO8) transistor. I thought.

However, in the normal MO8 process, manufacturing transistors with different threshold values has a problem in that the process is complicated. Specifically, in a normal manufacturing process of, for example, an NMOS transistor, setting the threshold of an enhancement type transistor and an intrinsic type transistor requires accurate threshold control for each, and the channel of each transistor must be controlled accurately. Precise shallow implant in the area
n) That is, ion implantation was performed into a shallow surface region.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and provides a method for manufacturing a circuit device that can extremely easily form transistors with different threshold values suitable for input circuits such as Schmidts I-to-I+G circuits. This is what I am trying to do.

[Summary of the invention]

That is, the method for manufacturing an integrated circuit device according to the present invention focuses on the fact that there is no need to set a threshold value strictly for transistors in which a low threshold value is desirable in a Schmidt IJ circuit for an input circuit, etc.
Shallow implantation in the process of forming an O8I-transistor is selectively not performed on transistors and the like that are desired to have a low threshold value.

Therefore, the method of manufacturing an integrated circuit device of the present invention includes a high threshold voltage transistor and a transistor of the same type as this transistor, which preferably has a low threshold voltage, for example, in a Schmitt trigger circuit for an input circuit. In this step, the channel ion implantation step for controlling the threshold voltage into the region where the high threshold voltage transistor is to be formed is performed by implanting the channel ions into the region where the high threshold voltage transistor is to be formed while a resist film is deposited on the region where the low threshold transistor is to be formed. This is carried out selectively, and the channel ion implantation step for controlling the threshold voltage is not particularly performed in the region where the low threshold transistor is to be formed.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

As mentioned above, it is better for the transistor Trt of the Schmitt trigger circuit in No. 11 to have a threshold voltage lower than that of a normal transistor constituting the main circuit of a memory, a microprocessor, etc. Specifically, it is preferable that the threshold voltage be around OV. It is desirable that there be. Try this transistor
When the threshold of Tr2 is about 0■, even when the substrate effect is effective, the threshold of transistor Tr2 increases by about 1V, and the threshold of the Schmitt trigger circuit is set to 1.5.
It becomes possible to set it to about V.

A method of manufacturing an integrated circuit including such a low-threshold transistor will be described next, taking as an example the manufacturing process of the second transistor Tr2 and the third transistor Tr3 in FIG.

In FIG. 3, gate oxidation is performed on an element region surrounded by a field oxide film 12 on the surface of a P-type semiconductor substrate 11 to form a gate oxide film 13 of a predetermined thickness.

Next, ions of the same conductivity type as the base plate 11 (usually boron) are heated at an acceleration voltage of 100 KeV and a dose of 1.0x.
Deep implant (Deep I)
mp (fantation). This is achieved by implanting a high dose of impurities at a relatively high acceleration.
The purpose is to increase the substrate mW in the deep part of the channel to prevent leakage between the source and drain.

Next, a shallow implant is performed on the surface area of the substrate in the region A where an enhancement type NMO8) transistor is to be formed. That is, in FIG. 4, a region B where a low threshold transistor is to be formed is covered with a resist 14, and a substrate 11 such as boron is coated.
Ions of the same conductivity type are accelerated at a relatively low acceleration voltage of, for example, 40 KeV and at a relatively low acceleration voltage of, for example, 2. It is implanted at a low dose of about OX 10"/cd. This sets the threshold voltage of the NMOS transistor to about O.SVV.

Next, after removing the resist 14, a polysilicon layer, for example, is formed at a predetermined portion on the gate oxide film 13, as shown in No. 51, and patterned.
Gate electrode 15A.

Form J5B.

Thereafter, as shown in the sixth song, an N-type impurity such as arsenic is ion-implanted into the gate electrode 15 on the inclined surface of the semiconductor substrate 11 using 15B as a self-line mask 2, and a diffusion layer 16 that becomes a Coos drain is formed. Form .16.

In the same figure, an enhancement type transistor having a normal high threshold value and an intrinsic type transistor having a threshold value of almost Ov are connected in series with a common diffusion @1e in the center of the figure.

8) The impurity concentration profile (distribution) A in the channel region on the transistor side and the impurity concentration profile B in the channel region on the low-threshold transistor side are shown in 7. The graph of is shown below. As is clear from this graph, the impurity concentration near the channel surface on the low threshold transistor side where shallow implantation is not performed is almost 0, so channel inversion is easy and the threshold voltage is approximately Ov. Furthermore, since the concentration in the deep part of the channel is the same as that of a normal NMO8 transistor, the leakage characteristics are not worse than those of a normal transistor.

In addition, the manufacturing process of the above example includes the following steps, except for the step of depositing a resist film on the region where the low threshold transistor is to be formed.
This process can be performed simultaneously with the process of forming NMOS transistors that constitute the main circuit of a memory or microprocessor. The resist film deposition process only needs to cover the channel region of the low-threshold transistor, and does not require strict precision in the deposition area, making it an extremely easy process. .

Similarly, in the above embodiment, a deep implant is first performed in the element region, and then a shallow implant is performed, but conversely, a resist film is selectively deposited on the region where a low threshold second transistor is to be formed. In this case, shallow implantation is performed via a gate oxide film on the inclined wall where high threshold transistors are planned to be formed, the resist film is removed, and deep implantation is performed in the regions where high threshold transistors and low threshold transistors are planned to be formed. good.

〔Effect of the invention〕

As described above, according to the method for manufacturing an integrated circuit device according to the present invention, without adding complicated steps or changing steps,
For example, a low threshold transistor such as an intrinsic MO81-transistor can be replaced with a normal enhancement type MOS.
Can be formed simultaneously with transistors. This allows TTL
It is possible to form L-IJ circuits in the same process as conventional ones, which can efficiently convert signals from MOS level to MOS level, and contributes to improving the operating performance of large-scale integrated circuits such as memories or microprocessors. I can do it.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a Schmitt trigger circuit, FIG. 2 is a diagram showing input/output characteristics of the Schmitt trigger circuit, and FIGS. 3 to 6 are diagrams of an integrated circuit device according to an embodiment of the present invention. The 71st cross-sectional view for explaining the manufacturing method is a graph showing the impurity concentration distribution in the channel region of the transistor. 11... Semiconductor substrate, 12... Field oxide film,
13... Gate oxide film, 14... Resist film, 7.
5A... Gate electrode, 15B... Gate electrode, 16
...Diffusion layer. Applicant's agent, patent attorney Suzue Takehikotomo m-.ト云F禦人+、-＝傑

Claims (2)

[Claims] (1) In a method for manufacturing an integrated circuit device comprising a high threshold voltage transistor and a low threshold voltage transistor of the same type as the high threshold voltage transistor, a method for controlling the threshold voltage in the region where the high threshold voltage transistor is to be formed is provided. The channel ion implantation step is selectively performed in the region where the low threshold transistor is to be formed with a resist film being deposited on the region where the low threshold transistor is to be formed, and in order to control the threshold voltage in the region where the low threshold transistor is to be formed. 1. A method for manufacturing an integrated circuit device, characterized in that a channel ion implantation step is not performed. (2) The first inverter configuration in which the gates are connected in common and the source and drain are connected in series. for output potential feedback, the gate and drain of which are connected to the connection point between the second and third transistors, the first transistor and the second transistor, and the connection point between the second transistor and the third transistor, respectively; In the method for manufacturing a plurality of transistors including a second transistor of a Schmitt trigger circuit for an input circuit comprising a fourth transistor, a resist film is deposited on a region where the second transistor is to be formed; A method of manufacturing an integrated circuit device according to claim 1g1, characterized in that a channel ion implantation step for threshold control is performed in a region where a transistor is to be formed.