JPS60200301A - Control system for semiconductor production process - Google Patents

Abstract

PURPOSE:To attain the high control accuracy and to improve the production yield of semiconductors by controlling the processing conditions of each processing part through an adaptation control part, an FF control part and a set value control part based on the measurement value signal and the design value sent from a measurement part. CONSTITUTION:For adaptation control, a processing part 1 is controlled by a control part 3 based on the data obtained from a measurement part 2 set in a succeeding process. The target value M set from outside and the signal sent from the part 2 are supplied to the part 3. For FF control, a processing part 4 is controlled by a control part 6 based on the data obtained from a measurement part 5 set in the preceding process. The part 6 receives the target value M from outside and the signal from part 5 and delivers a signal to the part 4. For set value control, a processing part 7 is controlled by a control part 8. The part 8 calculates the target value Ms of processing corresponding to the design value or the corrected design value D and controls the part 7 with the target value signal Ms.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor manufacturing process control system that improves yield, improves control accuracy, and automates processing processes.

[Background technology]

Semiconductor devices such as ICs, LSIs, and VLSIs are systems in which various elements such as transistors, diodes, resistors, and capacitors are combined with wiring for forming circuits on a semiconductor substrate. Therefore, if there is a defect or non-standard part in any of the various elements or circuits, the entire semiconductor device becomes defective.

This probability of defect occurrence is expressed as the product of the probabilities of defect occurrence of various elements, wiring, and other components.

As the degree of integration of semiconductor devices increases, processing accuracy is approaching its limit. Since the minimum width of a pattern is becoming finer from 1.5 μm to submicron, the occurrence of defects is likely to increase. In order to suppress the occurrence of these defects and improve the manufacturing yield of semiconductor devices, it is therefore necessary to control each processing step in the semiconductor device manufacturing process with high precision. In order to achieve this goal, it is preferable to automate the control of the processing steps.

However, current semiconductor device manufacturing processes do not meet this requirement, which is an obstacle to improving yield. For example, most of the control of each processing step is open control. Furthermore, control is performed manually on a batch (loft) basis based on data obtained from inspections after each processing step. Artificial factors intervene in the control of each processing process, leading to problems of unstable processing and low efficiency. In addition, it is difficult to perform optimization control that takes into account the differences between each processing step, and this poses a problem in that it is difficult to achieve high precision control.

[Purpose of the invention]

The purpose of the present invention is to provide each processing step (
The aim is to improve manufacturing efficiency and uniformity of processing by automating control of manufacturing processes.

Another object of the present invention is to improve control accuracy and stabilize control by performing optimization control that takes into account the mutual influence between each treatment (step) process.

Another object of the present invention is to provide a semiconductor device manufacturing process control system that can improve the manufacturing yield of semiconductor devices by performing the optimization control described above.

The above and other objects and novel features of the present invention include:
The description herein and the accompanying drawings will become clear.

[Summary of the invention]

A brief summary of typical inventions disclosed in this application is as follows.

That is, each treatment step (process) and measurement step (process) of the semiconductor device manufacturing process are combined to form a series of manufacturing processes. Each treatment step (process) is controlled by adaptive control or feedforward (F, F 2 ) control using data obtained in the measurement step (process).

Further, each treatment step (process) is configured to be able to control the treatment conditions of the previous and subsequent treatment steps (processes) based on the data and design values of the measurement step (process) by controlling set values. This makes it possible to automate the control of the manufacturing process and to perform optimization control between each processing step (process).

Therefore, it is possible to achieve high precision control and thereby improve manufacturing yield.

〔Example〕

FIG. 1 (Al to IcI are the main controls of the system of the present invention [adaptive control J rF, F control (Feed For
wardControl)Jr set value control" is a basic configuration diagram.

First, these will be explained.

"Adaptive control" refers to a measurement or inspection step or process (hereinafter simply referred to as a measurement section) in which a - processing step or process (hereinafter referred to as a unit processing section) 1 is provided in a subsequent step, as shown in Figure 1. The controller 3 performs control based on the data obtained in step 2. A target value set from the outside and a signal from the measuring section 2 are input to the control section 3 . The control section 3 outputs a signal to the processing section 1.

According to this control, for example, the processing process of a workpiece such as a wafer is controlled as follows. After the i-th wafer or the i-th batch is processed in the processing section 1, it is measured in the measurement section 2. The data obtained as a result is input to the control unit 3 as the i-th signal Ti. In the control section 3, the signal Ti
and a target value (external setting value) M set from the outside, and find the difference between the two. Based on this difference, the control signal 5i
n1 is output to the processing unit 1 to process the il1th wafer or the i+>th batch - this enables optimal control (and control automation).

In the "F, F control", as shown in FIG. 1B), the - processing 4 is controlled by the control section 6 based on the data obtained by the measurement section 5 provided in the previous step. A signal from the measuring section 5 is input to the control section 6, and the control section 6 outputs a signal to the section 4''.

According to this control, the processing result of the i-th wafer or the wafer of the i-th batch in the previous step is inputted to the control section 6 as the i-th signal T1 from the measuring section 5. Based on the signal Ti and the externally set target value MK given to the control section 6, the i-th control signal Si is output to the processing section 4. The i-th wafer or wafer 1 of the i-th batch transferred from the measuring section 5 to the processing section 4 is processed based on the signal Si.

This allows optimal control to be performed.

"Set value control" is as shown in FIG. The computer simulates processing conditions or target processing conditions that should be changed in response to changes in the material, atmosphere, temperature, etc. for the wafer.

According to this control, simulation is performed within the control unit 8 based on the set value signal DK such as a design value or a corrected design value. That is, a target value M8 of processing in the processing process 7 corresponding to the design value or the corrected design value is calculated. The target value signal M8 is input from the control section 8 to the processing section 7, and the processing section 7 is controlled by the signal MS.

FIG. 2 is a diagram showing a control system of an embodiment in which the above three controls are applied to the manufacturing process of a semiconductor device consisting of an MO8 type field effect transistor (MOSFET).

A part of the MOSFET manufacturing process will be briefly shown below, corresponding to the control system diagram in FIG. 2 and FIGS.

A gate oxide film 102 is formed on the surface of a P-type silicon semiconductor substrate 101 of a wafer by heat treatment using a quartz tube as a reaction furnace 51.
A gate oxidation portion 11 is provided. Immediately after this, the thickness T of the gate oxide film 102 is measured. An oxide film thickness measuring section 12 for measuring X is provided (FIG. 3).

Next, an ion implantation unit 13 is provided, which is an ion implantation device that implants impurities such as boron (t3+) into the substrate 101 through the gate oxide film 102 to adjust the threshold voltage Vth (see FIG. 3). Bl).

Next, the substrate 1 is coated using a CVD device or other film forming device.
01 is provided with a polysilicon film forming part 14 for tepositioning a polysilicon film 103 (FIG. 3 tcI
).

A coating section 15 is provided on this polysilicon film 103 to coat and form a resist film 105 using a spinner 52 or the like. Immediately after that, there is a resist film thickness measuring section 16 that measures the film thickness TR of the resist film 105 (FIG. 3 0).
).

Next, the gate mask 106 is formed by an exposure unit 17 that reduces and transfers the pattern of the photomask using an exposure unit 53 such as a step-and-repeat camera, and a developing unit 18 that includes a developing unit 54 that drips a developer while rotating the substrate 101. Form. Immediately after that, a gate mask width measurement section 19 is provided that measures the pattern width LR of the gate mask 106 that defines the patterned channel length (see FIG. 3 (old 1. old)).

Next, an etching section 20 is provided for patterning the polysilicon film 104 using the gate mask 106 as a mask using an etching device 55 such as a plasma etching device. The gate length determines the channel length of the polysilicon film that is subsequently etched, that is, the gate electrode 107. A gate measuring section 21 is provided to measure the .

Although details are omitted below, the source/drain region 108
An ion implantation part for forming an interlayer insulating film 109, a processing part for forming an interlayer insulating film 109, a contact hole formation, and an aluminum wiring 11.
The MOSFET shown in FIG. 3H is completed through a processing section 22 including a processing section for forming 0 and the like.

After finishing the processing in the wafer state, a W/P measurement unit 2 measures and inspects the characteristics of each wafer or chip, for example, Vth, using a quafer or chip inspection device 56.
3 is provided.

Further, a final measurement section 24 is provided for testing final characteristics such as access time TACC after the semiconductor device is completed.

In this example, in order to obtain wafers and chips with desired characteristics, each of the processing sections described above controls the following processing conditions.

In the gate oxidation part 11, the film thickness T of the gate oxide film 102 is controlled by controlling the oxidation time T1 and, depending on the case, the oxidation temperatures TF and MP (excluding this example). Adjust X.

Further, the ion implantation section 13 controls the dose amount NTD. This becomes one element of threshold voltage ■th control. Furthermore, in the coating section 15, the rotation speed R is controlled to adjust the resist film thickness T.
Adjust R. On the other hand, the exposure section 17 controls the exposure time TF, xP, which is one of the exposure conditions, and the development section 18 controls the development time TD, thereby adjusting the mask width LR that defines the channel length. Furthermore, the etching time in the etching section 20, particularly the overetching time T in this example. E is controlled to adjust the gate length L8.

Of course, in order to perform these controls, the oxide film thickness T must be adjusted as shown in the lower column of FIG. x, threshold voltage vth, resist film thickness TR, gate mask width LR, gate length L, and access time TAccE. It is set.

In order to control each of the above-mentioned elements between the above-mentioned processing units and measurement units, the above-mentioned “adaptive control”, l”F
, F control" and "setting value control" are performed between the respective processing units.

This will be explained below with reference to FIG. In FIG. 2, the letters A in each control section indicate adaptive control, F and F indicate feedforward control, and P indicates set value control.

be done. As data for control, the measured value T by the oxide film thickness' measuring section 12 is used. X and the design value T. Target value T obtained by correcting X using adaptive control 45 and 46 described later. Use X (horizontal line "-" added). The measured value T is sent to the adaptive control unit 30. X and target value T. The difference ΔTo from X is input. Difference △
ToX may be set within the control unit 30. Difference △
Tox and Δ held as information in the adaptive control unit 30
△T4MF using the correlation between TiMa and △Tox
, put on. On the other hand, the oxidation time set value control section 31 receives the input target value T. X and Ti held internally as information
M.P., and T. The requested TIMo calculates TlMF, by shimmy tan, using the correlation with X.
is corrected by the above-mentioned ΔT and the oxidation time of the gate oxidation portion 11 is controlled.

In other words, the gate oxide film thickness T of the next wafer to be processed.

Optimally control X. Note that the gate oxidation section 11 and the ion implantation section 13 are controlled by a dose amount F, an F control section 32, and a dose amount setting value control section 33. The above-mentioned film thickness measurement value T is used as control data. X and the design value vth are used. The dose amount F, the F control unit 32 receives the input film thickness measurement value T. X, NTD and T held internally as information
. The dose NTD of ions implanted in the ion implantation section 13 is determined based on the correlation with X. The design value of the threshold ■th and the dose amount set value control unit 33 are set to NTD.
The target value of the dose amount is corrected by the adaptive control unit 45 using the correlation between Vth and Vth. The optimum dose amount NTD is adjusted from a comparison between the corrected target value NTD and the value determined by the control section 32. This control is performed on a wafer basis. Therefore, the film thickness Tox is determined for each wafer.

The coating section 15 is controlled by a resist film thickness adaptation control section 34 and a rotation speed setting value control section 35 . As data for control, the measured value TR obtained by the resist film thickness measuring section 16
Then, a target value TR obtained by correcting the film thickness design value TR by an adaptive control 44 described later is used. A difference ΔTR between the measured value TR and the target value TR is input to the resist film thickness adaptive control section 34. The difference ΔTR is held internally by the adaptive control unit 34 as information. The rotational speed correction value ΔR is calculated using the correlation between ΔTR and ΔR. On the other hand, the rotation speed R is determined by the rotation speed setting value control section 35 through a simulation using the input target value TR and the correlation between R and TR held internally as information. The coating rotation speed for the next wafer 1 is adjusted using this R and the correction value ΔR.

The exposure unit 17 is controlled by an exposure F, an F control unit 36, an exposure adaptive control unit 37, and an exposure setting value control unit 38. Measured value TR, target value LR, and difference ΔLR are used as data for control.

The target value [R is obtained by correcting the design value LR of the width of the resist mask for gate formation, which defines the gate length, by an adaptive control 43 to be described later. The difference △LR is the target value LR
This is the difference between R and the measured value R obtained by the gate forming resist mask width measuring section 1.9. The exposure setting value control unit 38 controls the target value LR and TF, x, which is held as information internally.
The exposure time TEXP is simulated using the correlation between P and LR. The exposure adaptive control unit 37 performs exposure using the difference ΔLR between the target value LR and the measured value LR, and the correlation XP between ΔT and ΔLR, which is held as information inside the exposure adaptive control unit 37. Add the time correction value △TExP. on the other hand,
The exposure F, F control section 36 calculates TF, xP from the correlation between the measured value TR of the resist film thickness measurement section 16, TI, xP, and TR held as internal information. This TEXP
and the simulated T], , XP, correction value △T
Determine the optimum exposure time T with ExP. This optimum exposure time T is determined for each wafer.

As described above, when exposing each chip using a step-and-repeat camera, the exposure time can be further corrected for each chip. Chip exposure time correction F, F
The control section 47 corrects the optimum exposure time TEXP for each wafer using the input film thickness measurement value TR0J for each chip from the film thickness measurement section 16, and controls the exposure time for each chip.

The developing section 8 is controlled by a developing adaptive control section 39.

The adaptive control unit 39 controls the above-mentioned difference in the width of the gate forming mask △
LR and Δ held internally by the control unit 39 as information.
Using the correlation between TDEv and ΔLR, the corrected development time ΔTDP,v with respect to the standard development time is determined, and the optimum development time TDEv is adjusted.

The etching section 20 is controlled by an etch FF control section 40, an etch time setting value control section 41, and an etch adaptation control section 42. The aforementioned measured value LR1, measured value LE, and target value R are used as data for control. Measured values LF and &ma are values obtained by the gate length measuring section 21. The target value LF is obtained by correcting the gate length design value LP by adaptive controls 45 and 46, which will be described later. The etch time setting value control unit 41 receives the target value LF, the difference ΔLE between the measured gate length LP, and the target value LR of the gate mask width.
is input. The control unit 41 receives these inputs and T held therein as information. . The overetching time T is calculated using the correlation between LR and LR. . is determined by simulation. The etch time adaptive control unit 42 selects the input difference △L and the △L]i that is internally held as information.
, and the correlation between ΔToIi and the overetching time correction ΔTOEi. Etch FF control section 40
automatically calculates the etching correction time ΔToF using the input measurement value LR of the gate mask width and the correlation between ΔToP and LR, which is held as information internally.

From these values, calculate the optimum etching time (overetching time).

The adaptive control unit 43 receives the aforementioned gate length difference ΔL0 as an input, and outputs a signal for correcting the design value LR to obtain the target value LR. The adaptive control unit 43 is effective in controlling the gate mask width LR with high precision. Similarly, the adaptive control unit 44 receives the difference edge as an input, and outputs a signal that corrects the design value 〒R to reach the target value 〒.

The adaptive control unit 45 receives the threshold design value ■th and the measured value ■
The difference Δ■th from th is input. The adaptive control unit 45 inputs the target values LE, T'ox and N as the difference Δ■thml inputs. Outputs a signal to turn D on.

Furthermore, the adaptive control unit 46 sets the access time design value 〒ACCE
The difference ΔTAccF between the measured value TACCE and the measured value TACCE is input. The adaptive control unit 46 inputs the difference ΔTAccF and corrects the design value LP, . . . ox to the target value. l Outputs a signal to reduce TOX.

Each control section configured as described above is eventually connected between adjacent processing sections or measurement sections, or is connected across one or more processing sections or measurement sections. In other words, the conditions for each processing unit are set in a state where a series of processing steps are related to each other. In this case, each control section differs only in the weight of the control amount, that is, the magnitude of the control amount. The control amount of the control unit shown in the upper part of FIG. 2 is made larger than that in the lower part. In other words, the control amount of the adaptive control unit and F, F control unit that performs control between adjacent processing units is increased, and the control amount of the set value control unit and adaptive control unit that performs control between distant processing units is increased. The amount is kept small.

Furthermore, in order to finally obtain a semiconductor device that satisfies the specifications, hierarchical control is performed and weighted. Device specifications, such as film thickness, width, length, depth, etc., are quantities that are directly controlled.

Control that focuses on these is the adaptation and F
Performed by F control and set value control of medium control amount ℃
There is. Control focusing on device characteristics, such as threshold voltages of individual MISFETs, resistance values of individual resistors, etc., is performed with a small amount of control and mainly through adaptation and set value control from non-adjacent processing units. Control focusing on IC characteristics, that is, characteristics of the completed chip as a whole, such as access time and delay time, is performed by adaptive control, which requires the least amount of control. Device characteristics and IC characteristics, which are determined by a combination of device specifications and cannot be directly controlled, are mainly controlled by correcting design values. According to this, even if the device specifications slightly deviate from the design values, a product that meets the specifications can be obtained in the end.

Therefore, according to the process of this embodiment, the gate oxidation portion 11 is immediately processed under improved conditions in the next punch as a result of the oxide film thickness of the negative punch. In the ion implantation section 13, the optimum dose amount for each trap for each wafer that is sent has already been determined. In the coating section 15, the coating rotation speed of the next wafer is improved based on the coating result of the negative wafer. In the exposure section 17, the exposure amount is determined by a comprehensive judgment based on conditions suitable for the film thickness of the wafer being sent and conditions based on the development results of the previously exposed wafer or chip. Of course, the developing time of the developing section 18 is also determined based on the results of the previous wafer development. The overetching time is also determined by the gate mask width of the wafer sent to the etching section 20 and the gate length of the wafer etched earlier.In the end, responsive control can be achieved by controlling adjacent processing sections. can be done.

Further, when determining the conditions of each part, adjustment is performed by setting value control based on design values. In this set value control, the conditions are determined by simulation, and the W/P measuring section 23
Since the design value is corrected and set as the target value based on the results of the final measurement section 24, the accuracy of condition determination can be increased. At the same time, by controlling (jumping over) a plurality of processes in this way, it is possible to suppress excessive fluctuations in conditions for each wafer 71 and each chip, and to stabilize and equalize quality. In this case, the responsiveness, stability, etc. of processing condition settings can be adjusted as desired by varying the specific gravity of each control section.

In this embodiment, the unit is chip-based depending on the processing.

Since conditions are set for each wafer and each batch (lot), the conditions are set optimally for batch processing such as the gate oxidation section 11, chip-based processing such as the exposure section 17, and other wafer-based processing. Allows setting of conditions.

In the above description, it is assumed that each control unit is connected to a host computer for centralized management, thereby making it possible to automate processes and perform centralized management.

〔effect〕

(1) Connect the adaptive control unit, F, F control unit, and set value control unit to each processing unit and measurement unit that make up the manufacturing process, and control each processing unit based on the measured value signal and design value from the measurement unit. Since it is configured with 5 ICs to control processing conditions, it is possible to automatically control each processing condition and achieve automation of the entire process control.

12) Since the processing conditions of each processing section are controlled based on the correspondence between the measurement value signal of the measurement section and the design value, the accuracy of each processing condition can be improved and highly accurate control can be performed.

(3) The processing conditions of the processing units before and after the measurement unit are controlled by the measurement value signal of the measurement unit in the adaptive control unit, F, F control unit adjustment setting value control unit, so the measurement unit corresponds to each processing unit. There is no need to provide the same, and the system can be simplified.

+41 The processing conditions of one processing section can be controlled based on each measurement value signal of each measurement section before and after it,
Control accuracy can be further improved.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the oxidation temperature may be controlled in the gate oxidation section, and the exposure illuminance may be controlled in the exposure section. In addition, the adaptive control unit, F,
The F control section is not limited to the illustrated position and may be changed as appropriate.

[Application field]

In the above explanation, the invention made by the present inventor was mainly applied to the manufacturing process of MOSFET, which is the field of application that formed the background of the invention, but it is not limited to this, and can be applied to the manufacturing process of other devices. can also be applied.

[Brief explanation of the drawing]

Figure 1: CBl, IcI are adaptive control, F, F
FIG. 2 is an overall diagram of a system according to an embodiment of the present invention, and FIG. 11. Gate oxidation part, 12... Oxide film thickness measurement part,
13... Implant part, 14... Polysilicon film forming part, 15... Coating part, 16... Photoresist film thickness measuring part,
17...Exposure section, 18...Development section, 19...Gate mask width measurement section, 20...Etching section, 21...
Gate measurement section, 22... Completion process section, 23... W/P
Inspection Department, 24...Final Inspection Department, 30, 34, 37, 39, 4
2゜43-46...adaptive control section, 31, 33, 35゜38.41...set value control section, 32, 36, 40...
・F, F control section, TOX l vTHI TRI LR
? LE t TACCE...Design value. Agent Patent Attorney Akira Takahashi Mistake 1 Diagram

Claims (1)

[Claims] (1) A series of manufacturing processes is constituted by a processing section in a semiconductor manufacturing process and a measurement section that measures specifications after processing,
An adaptive control section, F, F control section, and set value control section are connected to each processing section and measurement section, and the processing conditions of each processing section are controlled by the adaptive control section based on the measurement value signal and design value from the measurement section. , F, F control section, and set value control section. 2 The adaptive control unit is connected between the processing unit and the measurement unit provided at a post-process position of the processing unit, and controls the next processing based on the measurement value in the measurement unit of the semiconductor that has been processed in the processing unit. 2. A semiconductor manufacturing process control system according to claim 1, which is capable of controlling processing conditions in a semiconductor processing section. 3, F, F control section connects the processing section and a measuring section provided at a pre-process position of the processing section, and adjusts the temperature of the semiconductor based on the measured value of the semiconductor measured at the measuring section. Claim 1 which controls the processing conditions in the processing section
The semiconductor manufacturing process control system described in Section 1. 4. The semiconductor manufacturing process control system according to claim 1, wherein the set value control section performs simulation based on the design value and the measured value of the measurement section to control the processing conditions of the processing section.