JPS60196842A - Memory device for video printer - Google Patents

Abstract

PURPOSE:To prevent a device from deterioration at a recording time and to print recorded information while checking its contents by recording video information as an analog one and outputting the recorded video information at a format proper to a high speed or low speed external apparatus. CONSTITUTION:A video signal inputted to a terminal 1 is inputted to an I/O port (IOP)2 through a data bus DB and supplied to a CPU3. The CPU3 transmits a signal based upon the input video signal to VRAMs 6, 7 through a converter VDP4 for monitor receiver and supplies the signal to a VRAM8 through a converter VDP5 for a printer. Video information to be printed out by the printer is recorded in the VRAMs 7, 8 and information other than the video information to be printed out by the printer is recorded in the VRAM6. An output signal from the printer converter VDP5 is supplied to an output terminal 18 of the printer through a color converting circuit (CCNV)15, a selector (SEL)16 and a vertical/ horizontal converting circuit (VHCNV)17.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a memory device for a video printer, and particularly to a memory device for a video printer that outputs recorded video information as a video signal in a format compatible with an external tMTa. -ru.

(Prior art) In recent years, with the development of electronic technology, devices such as game devices, computer graphics devices, and personal computers that use video signals as output display signals have become widely used. These devices output video signals from a video display processor (hereinafter referred to as VDP) controlled by a control circuit whose main component is a medium-temperature processing circuit (hereinafter referred to as CPU). It is structured so that The explanation regarding the above-mentioned VDP can be found in the March 30, 1981 issue of Nikkei Elec 1 to Ronics J (pages 156 to 164), published by Kuchigaru McGraw-Hill.
Since it is described in , the explanation will be omitted here.

The video information output from these devices (such as No. 8) is stored in memory (recorded) and output to various external devices. It is becoming increasingly important to monitor, print, and print using low-speed external devices such as printers when confirming, storing, transmitting, and comparing video information.

(Problem to be solved) However, as mentioned above, conventionally, when recording video information such as video A (FII), the video signal is converted into a digital signal from analog to digital (hereinafter referred to as ΔD). This converted digital signal has been recorded in memory.

However, when recording video information using this method, image deterioration occurs due to problems such as conversion accuracy, and it is difficult to sequentially convert each dot of video information at precise timing and record it in memory. The problem is that the configuration of the device becomes very complicated and the cost becomes high.

Furthermore, as mentioned above, many of the conventional memory devices for video printers are configured to select and switch between monitor output and print (printer) output. It is necessary to check the content by looking at the screen, and then switch to the hV or other print output, which leads to the problem of poor operability.

Another problem is that it is difficult to record new video information during printing, or to search for and prepare the next video information to be printed from among multiple video information that has been recorded in advance, resulting in poor operability. The points were also on the right.

C1 The present invention records video information by △
Since the configuration is such that the recorded video information is recorded without D conversion and output as video information in a format that is compatible with high-speed external equipment and low-speed external equipment, the video information is This prevents deterioration of the recorded I5+! While checking the image information, it is possible to output a print output signal in a format compatible with low-speed external devices, and furthermore, the recorded video information can be outputted in a format compatible with low-speed external devices! It is an object of the present invention to provide a memory device for a video printer that is capable of recording new video information during a period of outputting a specific print output signal, and has significantly improved operability.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention records input video information, and transfers the recorded video information to a low-speed external device and a high-speed external device. outside! This is a memory device for a video printer that outputs data to an IllI! a control unit that outputs a data signal of image information as image information data No. 11 processed in accordance with the operation input; and a first clock pulse generator that outputs a clock pulse signal of a first frequency. , a second frequency signal outputting a lock pulse signal, a dark signal of video information is supplied from the nerator and the control section, records a data signal of the video information, and transmits a lock pulse signal between them. a first memory and a second memory capable of mutually transferring data signals of recorded video information; converting a first frequency into clock pulses supplied from the first clock pulse generator and controlling the controller; selects the data signal of the video information recorded in the first memory and the second memory based on the control data signal supplied from the controller, converts the data signal into a signal suitable for the high-speed external device, and outputs the signal; a first image generation unit that generates a first image, and a data signal of video information is supplied from the control unit;
a third memory for recording the same video information data signal as the video information data signal recorded in the second memory; The frequency ratio [, the third pulse signal and the control data signal supplied from the control section]
The data signal of the video information recorded in the memory of
The purpose of the present invention is to provide a memory device for a video printer, which includes a second image generation section that converts the image into Pii data and outputs it, in a form that is compatible with external equipment.

(Embodiment) An embodiment of the memory device for a video printer according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block system diagram of an embodiment of a memory device for a video printer according to the present invention, and FIG. 2 illustrates the operation of an embodiment of the memory device for a video printer according to the present invention.
This is a first diagram.

Note that D shown in FIG. 2 indicates one screen on which video information is displayed, and -Hsync and Vsync
, indicate the horizontal synchronization signal and vertical synchronization signal, respectively, ■ indicates the time since the arrival of the horizontal synchronization signal, TV indicates one vertical synchronization period, and CLK indicates the sampling clock pulse generator (hereinafter, 5CPG), which will be described later. A clock pulse signal outputted from 22 (denoted as ) is shown.

Reference numeral 1 denotes a terminal of a data bus DB, to which a data signal of video information (hereinafter sometimes simply referred to as a data signal) is supplied from a video information supply source.

The data signal input to the terminal 1 is input to the input/output ports 1 to 2 (hereinafter referred to as OP) via the data bus DB. The data signal input to l0P2 is supplied to a central processing unit (hereinafter referred to as CPU) 3. CPU3
The data from l0P2 (data signal based on ff1) is sent to the first memory, video random access memory (hereinafter referred to as VRAM) 6, and the second memory via VDP4.
In addition to being transmitted to VRAM7, which is the memory of
It is supplied to the third memory VRAM8 via P5. Further, VDP/1.5 operates according to the control data signal of CPU 3J.

Incidentally, VDP/1 and VRAM6.7 are elements constituting the first image generation section, and VDP5 and VRAM8 are elements C constituting the second image generation section.

Furthermore, the CPU 3 generates VRΔfvl 6 as necessary.

The data time numbers of the registers 7.8 and VDP/1.5 are output from terminal 1 via l0P2. The data signal output from the terminal 1 is transferred and output to an external memory (not shown in FIG. 1) connected to the terminal 1.

The VDP 4 described above converts the recorded video information into a format suitable for the monitor receiver (output VDP can control two systems of VRAM 6.7).
l 1,1 tail. On the other hand, V D P 51. i Adjust the recorded video information to fit your needs! The VRAM 8 is controlled by the VDP, which is output after converting it to the video information of your computer. The video information to be printed by the printer is recorded in the VRAMs 7 and 8 mentioned above, and video information other than the video information to be printed by the printer is recorded in the VRAM 6.

Further, the VRAM 6 described above has a recording capacity that can record video information equal to or greater than that of the VRAMs 7 and 8.

Reference numeral 9 denotes an operation unit (hereinafter referred to as OP), which is provided with a group of operation switches (not shown in FIG. 1) to be described later.
9 transmits an operation input to l0P2, and 10P2 transmits a signal corresponding to the operation input to OP9 to CPU3.

10 is random number 2 memory (hereinafter referred to as RAM)
＞, 11 is a read-only memory (hereinafter referred to as ROM)
) The T-1 RAM 10 and ROM 11 are memories used by the CPU 3 to perform various processing operations to be described later.

In addition, l0P2, CPLI3, OP9, RAMl0°R
OM11 is an element constituting the control section.

12 and 13 generate the voltage E1 pulse to drive VDP4 and 5, and the voltage pulse fG to drive the voltage VDP4 and 5.
These are first and second clock pulse generators (hereinafter referred to as CLK) that supply to DP4 and DP5. Specifically, CLK12 converts the data signal of the video information supplied by VDP4 into a type f11 that is compatible with the monitor receiver.
The first frequency (
For example, the CLK 13 outputs a clock pulse signal of about 10.7 M l-I Z ), and the VDP 5 converts the supplied video information data signal into a video signal conversion output suitable for the printer. A pulse signal with a frequency of 2 (for example, about 30 M) (lz) is output.

The output signal of VDP4 is supplied to monitor output terminal 14.

The output of VDP5 is a color conversion circuit (hereinafter referred to as CCNV).
) 15, selector (hereinafter referred to as SEL) 1G,
Vertical and horizontal change circuit (hereinafter referred to as V)-ICN V) 1
7 to the printer output terminal 18.

Note that the above-mentioned CCN V 15 converts the video signal output from the VDP 5 into M (magenta), C (cyan), Y (
It is a conversion circuit that converts iIA into each signal of ``]-),
5EL16 is M, C converted with CCN V i5.

This is a selector (1s selection circuit) that sequentially selects and switches any one of the Y signals to one screen IG to override the output.
) ICNV17 is composed of a Zumble hold circuit, etc., and the video information of one screen is transmitted sequentially from 8 to the right.
This is video information that is continuously transmitted from the top to the top of one screen and is transmitted continuously from the left to the right. I! This is a circuit that performs so-called vertical-horizontal conversion, which converts it into image information.

Therefore, M and C are output from the printer output terminal 18.

The M, C, and Y signals are sequentially selected and switched for each screen, and a vertically and horizontally converted video signal is output. This type of video/signal is suitable as a video signal supplied to an external device with a length of 1 m such as a printer that prints by inputting a short data signal string.

In addition, the SEL 16 outputs various control signals corresponding to the operator's input to the CP9. The control circuit 19 supplies SEL, 1G with a selection signal that sequentially selects and switches the M, C, and Y signals for each screen as described above. Further, this selection signal is output from the output terminal 20 as a color data signal.

Also, the output 4r5@ of VDP5 is V l-1 separation circuit 2
1, and the Vl-1 separation circuit 21 separates the horizontal synchronization signal and vertical synchronization (ffl bow).The horizontal synchronization signal and vertical synchronization signal are supplied to the control circuit 19 and the 5CPG.
22, and is also output from the output terminal.

CLK13 also supplies a clock pulse signal to 5CPG22. Furthermore, as mentioned above, the 5CPG 22 is connected to the t-l s y in FIG.
Horizontal synchronization indicated by nc (Vsyn in g and Figure 2)
Vertical synchronization in Ji3 shown in c is supplied, and these signals are supplied with 5CPG22. is CL K in Figure 2.
The clock pulse I3@ shown in is output. 5CPG2
The clock pulse signal output from 2 is the time 1+ (time position at the left edge of the screen indicated by D in FIG. 2, and horizontal synchronization indicated by l-1sync in FIG. 2) shown in FIG. For each vertical phase period (based on the temporal position at which the signal occurred), one vertical phase period (the second
During the period from the top edge of the screen to the bottom edge of the screen, indicated by D in the figure), a [ ] pulse signal as indicated by CLK in FIG. 2 is generated, and similarly at every time t2 shown in FIG. Next one! ! ! CL in Figure 2 over the direct synchronization period TV.
Output a lock pulse signal as shown by K, and perform the following steps.
Similarly, at time t3. At times t4+...tN, a clock pulse signal indicated by CLK in FIG. 2 is output. In addition, the controller 1゛・[Call circuit 19 is 5CPG22
is a control signal that controls the operating state of
・When no operation is performed): A control signal is supplied to put the 1SCPG 22 into a non-operating state.

In addition, the clock pulse signal output from the 5CPG22 is supplied to the VHCN V17. As mentioned above, the -VlICNV17 is composed of a sample and hold circuit, so the clock pulse signal outputted from the 5CPG22 is supplied to the CI-V1 in FIG. The beat lock pulse signal indicated by K is used as a rimbling bow. 5 more CPG2
The lock pulse signal as shown by CLK in Fig. 2 output from 2 is output by a delay circuit (hereinafter referred to as DLY).
24 is also supplied.

DLY24 outputs a signal delayed by 1/2 of the pulse width of the clock pulse signal supplied from 5CPG22 to output terminal 25J.

The terminal 26 is an interrupt signal input terminal for causing the CPU 3 to perform an interrupt processing operation. When an interrupt signal (pulse) is input to the terminal 26J, the CPU 3 performs a flow transition as shown in FIG. 4, which will be described later. Interrupt operation is started according to the following.

Below are 1. Referring to FIG. 3, the operation of the CPU 3 of the embodiment of the video printer memory device according to the present invention shown in FIG. 1 will be explained.

FIG. 3 is a diagram illustrating the operation of the CPU of an embodiment of the memory device for a video printer according to the present invention.
It is. Note that unless otherwise specified, the steps in the following explanation are shown in 7 [J-1R-C] in FIG. Then, the CPU 3 starts operating and moves to step 1.

In step 1, CP'U 3, VDP4, 5, VRAM
6.7.8, RAM10. l0P2 (7) After initialization, the process moves to step 2.

Switch 2 checks to see if any of the O12 operation switches (not shown in Figure 1) has been pressed (key switch t).
1), move on to step 3.

In step 3, in accordance with the operation input to O12, a branch is made to steps 4 to 7, which will be described later, so as to perform a predetermined processing operation.

To be more specific, when the new screen display switch (not shown in Figure 1) installed in O12 is pressed, the process branches to step 4, and the external output switch (not shown in Figure 1) installed in O12 is pressed. When the switch (not shown in FIG. 1) is pressed, the process branches to step 5, and when the recording start switch (not shown in FIG. 1) provided at O12 is pressed, the process branches to step 6. No operation input 1. : If so, move on to step 8.

Step 4. ．． In step 5.6.7, after the following predetermined processing is performed, the process moves to step-up 8.

In step 4, the video information recorded in the VRAM 6 is changed to
The signal is output from the monitor output terminal 14 via the DP4.

In step 5 (when the external output switch provided at O12 in step 1 above is pressed), the video information recorded in the VRAM 8 is outputted from terminal 1 via DP5 and TOP'2. Specifically, after the start mark date of the video information recorded in the VRAM 8 is transmitted via the above-mentioned transmission route, it is transmitted at 9600 baud using the same transmission route.
The data of the video information recorded in the VRAM 8 and the contents of the register of the VDP 5 are transmitted one after another at a transmission speed of .

In step 6, the video information 'a-' recorded in the VRAM6 is
It is transmitted to TVRAM7.8 via VDP4.5. However, the processing operation in step 6 () during printout is prohibited.

- No processing operation is performed in step 7.

In step 8, it is determined whether new video information is to be input. If an operation input for inputting new video information is input to O12 (YES), the process moves to step 9; if not (NO), the process moves to step 10.

Step 9 In step 9, start mark data of the video information input to terminal 1 is detected, and data transmitted after the star 1-mark data is stored in VRAM6 and RAM10 (v
Record the register value of DP4, and then proceed to step 10.

In step 10, it is detected whether or not the print start switch (not shown in FIG. 1) provided at O12 is pressed, and when it is pressed, that is, the print start switch provided at O12 is :II-79) When the state changes from ON (conducting state) to ON (conducting state) (YES), step 1
Move to 2 and when the print start switch is not pressed (N
o>, that is, when the state of the print start switch is the same as the previous state (for example, when it is turned on continuously or when it is turned off), the process moves to step 2.

In step 11, 'CPU 3 is the control circuit 1.
9 and the Nikon 1-roll circuit 19 is S E L
A signal for activating 5CPG 16 is supplied to 5ELi6, and a signal for activating 5CPG 22 is supplied to 5CPG22. After this, return to step 2.

The CP of one embodiment of the memory device for a video printer according to the present invention shown in FIG. 1 described above with reference to FIG. 4 will be explained below.
The operation of LJ3 will be explained.

FIG. 4 is a graph for explaining the interrupt processing operation of the CPU of one embodiment of the memory device for a video printer according to the present invention. It should be noted that the steps in the following description refer to the steps shown in FIG. 4, unless otherwise specified.

When an interrupt signal (pulse) is input from the terminal 26 while the CPU 3 is performing a processing operation according to the 70-digit shown in FIG. 3, the CPU 3 starts the interrupt processing operation (INT )L, move to step 1.

In step 1, from CPLI3 to control circuit 19
A signal is supplied to stop the generation of the fij signal for controlling the 5EL 16 and 5CPG 22 outputting to the 5EL 16 and 5CPG 22, and then the process moves to step 2.

In step 2, after clearing the print start switch provided in OF2, the interrupt handling operation is finished, and the process returns to the step that was being performed when the interrupt handling operation was started. Processing operations are started according to the flowcharts 1 to 1 shown.

By the way, when printing the video information recorded in the VRAM 6, there are cases where it is better to convert any color of the video information recorded in the VRAM 6 to another color and print it, resulting in sharper edges for printing. be. This J: Unagi, that is, OF2
When the color conversion switch (not shown in FIG. 1) provided in the CPU 3 is pressed, the CPU 3 executes the flow 11.
Performs processing operations according to the instructions.

The operation of the CPU 3 of the embodiment of the memory device for a video printer according to the present invention shown in FIG. 1 will be explained below with reference to FIG.

FIG. 5 is a diagram 7 for explaining other processing operations of C and PtJ of an embodiment of the memory device for a video printer according to the present invention.
0-boot-1--boot. Note that the steps in the following description refer to the steps shown at 70-17- in FIG. 5 unless otherwise specified. Also, in the following explanation, the third
Only the processing operations (steps) that are different from the 70-diato shown in FIG. Specifically, 70-chi 17-1~ shown in FIG.
Step 12.13.
Flowage 1F-1 to which 14 was added.

When the data exchange switch (not shown in FIG. 1) provided in OF2 is pressed, a processing operation is performed in which the process branches from step 3 to step 12.

In step 12, as described above: (when the data exchange switch provided in OP 9 is pressed), the video information recorded in VRAM 7 is transmitted to VRAM 6 via VDP=lI.

Note that the data exchange switch described above must be operated when performing color conversion of the video information recorded in VRAM 7, but it is not necessary to operate it when performing color conversion of video information recorded in VRAM 6. There's no need.

After a predetermined processing operation is performed in step 8 or step 9, the process moves to step 13.

In step 13, the color conversion switch (
(not shown in FIG. 1) is pressed, and when the color conversion switch is pressed (YES), the process moves to step 14, and when the color conversion switch is not pressed (NO>, step 10 is detected). /\Move.

In step 14, any color of the video information transmitted to the VRAM 6 in step 12 is converted, and after confirming the desired color conversion processing, the video information recorded in the VRAM 6 (video information on which color conversion has been performed) is converted to the VDP4. The data is then transmitted to the VRAM 7 via the . However, the immediate color conversion process in step 14 described above is V[ and l! is recorded in ΔM6. ! A! Regarding image information, only ℃ can be executed, and the image information to be printed when the color conversion switch provided in 0P9t is pressed carelessly (an erroneous operation occurs) (the image recorded in VRAM 7 and 8) information)
is prevented from being color-converted.

1: In the description of the above embodiment, a first and a second clock pulse generator are provided, and each clock pulse generator is configured to output clock pulse signals of the first and second frequencies. However, it is also possible to provide a single oscillation circuit, divide the output signal of this oscillation circuit, and generate clock pulse signals of the first and second frequencies. It goes without saying that the first and second clock pulse generators in the explanation of the example may be clock pulse generators having the above configuration.

(Effects of the Invention) Since the present invention has the above-described configuration, it is possible to prevent video information from deteriorating when recording video information, and to adapt it to low-speed external equipment while checking the recorded video information. During the period in which the Jj signal is being output as the J signal, a new 1l11! It has the advantage that image information can be recorded and operability is significantly improved.

[Brief explanation of the drawing]

FIG. 1 is a block system diagram of an embodiment of a memory device for a video printer according to the present invention, FIG. 2 is a diagram for explaining the operation of an embodiment of the memory device for a video printer according to the present invention, and FIG. The figure is a flow chart for explaining the operation of the CPU of an embodiment of the memory device for a video printer according to the present invention, and the tt54 diagram is the interrupt processing operation of the CPU of an embodiment of the memory device for a video printer according to the present invention. FIG. 5 is a flowchart for explaining other processing operations of the CPU of an embodiment of the memory device for a video printer according to the present invention. 1...terminal, 2...input/output capo-1~(l0P), 3
...Central processing! A position (CPLI), 4.5...
Video A-dis V rape ottsu () (V DP)
, 6, a, 8...Video Random Acres Me Hair (VR
AM), 9... Operation unit (OP), 10... Random access memory (RAM), 11.
・Read-only memory (ROM), 12, 13...
・Clock pulse generator (CLK) 14... Monitor output terminal, 15... Color variable four-way (CCNv) 16... Hirefta (SEL) 17-1 Lateral variation TFL (V HCN V), 18.・
・Printer output terminal, 19...control circuit, 2
0, 23.25...Output terminal, child, 21...VH separation circuit, 22...Zumbling pulse generator (
SCPG), 24...delay circuit (DLY), '2G...terminal. Patent Applicant: Japan Victor Co., Ltd.

Claims (1)

[Claims] A memory device for a video printer that records input video information and outputs the recorded video information to a low-speed external device and a high-speed external device, the operation unit being located at the right corner,
a control unit that outputs an IC control data signal in response to an operation input input to the operation unit, and outputs an input video information data signal as a video information data signal processed in accordance with the operation input; a first clock pulse generator that outputs a clock pulse signal of a first frequency; a second clock pulse generator that outputs a clock pulse signal of a second frequency; and a second clock pulse generator that outputs a clock pulse signal of a second frequency; a first memory and a second memory to which a signal is supplied, record a data signal of the video information, and are capable of mutually transferring data signals of the recorded video information and information; Selecting the art signal q of the video information recorded in the first memory and the second memory by a clock pulse signal of a first frequency supplied from the clock pulse generator and a control data signal supplied from the control section. and a first image generation unit that converts the image into an image suitable for the high-speed external equipment and outputs it, and a data signal of video information is supplied from the control unit; a third method for recording a computer signal of video information that is the same as a data signal of video information recorded in the memory;
and a clock pulse signal of a second frequency supplied from the second clock pulse generator and a control data signal supplied from the control section.
a second image generation section which outputs a data signal of video information recorded in the memory in a form (converted to P'i number 1) suitable for the low-speed external device.