JPS60192474A - Pocket television set - Google Patents

Abstract

PURPOSE:To provide a key input function while keeping good external appearance with miniaturization by providing a touch switch for manual input on a display panel of a pocket television set and also providing a pattern recognition means recognizing an input pattern from the touch switch. CONSTITUTION:A key sense circuit 23 discriminates the content by a signal from a touch switch 22 and feeds an output to a CPU24. When the calculator mode CAL is selected by a mode switch 8, the CPU24 detects a scanning side display control circuit 17 and touch operation and the detection signal is outputted to the CPU24. The CPU24 writes a signal from the key sense circuit 23 as an input pattern to a memory in the scanning side display control circuit 17 and compares the content with the standard pattern for recognition. In such a case, the CPU24, in case of the television reception mode, stores the result of recognition to the memory as a memo data and when the calculator mode is selected, the CPU24 executes arithmetic processing according to the result of recognition and displays the input data and processing result at that time on a display panel 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a pocket television with data entry functionality.

[Prior art and its problems]

In recent years, compact pocket televisions have been put into practical use that use liquid crystal display panels in their display sections. Also, recently, A? Consideration is being given to adding a computer or electronic memo function. However, if you want to add functions such as a personal computer or an electronic memo to your pocket TV, a key personnel department will be required. Even if the keys are arranged in a small area in order to provide this manual key section, there are problems in that the appearance is poor and the operability is also poor.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a pocket television that maintains a small size without deteriorating its appearance and is equipped with key manual functions.

[Key points of the invention]

The present invention provides a touch switch for handwritten input on the display panel of a pocket TV, and also provides pattern recognition means for recognizing four turns of input from this touch switch, thereby making data input by handwriting possible. .

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure and FIG. 2 show the external appearance of a pocket television according to the present invention. 1 and 2, reference numeral 1 denotes a case, which consists of a front case 1& and a back case 1b, with a display window 2 on the front of the front case 1a, a display panel 3 located in the display window 2, A channel display section 4 and a speaker sound emitting section 5 are provided. Also, in the same figure, 6 is a gerium adjustment dial that also serves as a power switch, 7 is a tuning dial, and 8 is a VHF.

A mode switch 9 selects the UHF reception mode V and the computer (CAL) mode, and 9 is a rod antenna.

The display panel 3 is constructed using, for example, a liquid crystal display element, and a touch switch constructed of transparent electrodes is provided on the front surface of the panel as shown in FIG. This touch switch is a touch electrode T! ~TSOs are arranged in a 5×6 matrix, for example, and buttons are provided so that desired data can be entered by handwriting. The touch electrode T't-'rs.

The details of the handwritten input recognition process will be described later.

Next, the overall configuration of the electronic circuit will be explained with reference to FIG. In the figure, reference numeral 11 is a tuner, which selects a desired radio wave from among the radio waves received by the rod antenna 9,
It is converted into an intermediate frequency and output to the television circuit 12. This television circuit 12 amplifies and detects the signal from the tuner 11 and outputs it as a television video signal and an audio signal.

This audio signal is sent to the audio circuit 13, amplified, and output (to the speaker 14). Further, the video signal output from the television circuit 12 is input to a sync separation circuit 15 and a sync conversion circuit 16. The synchronization separation circuit 15 separates a horizontal synchronization signal and a vertical synchronization signal contained in the input video signal, and supplies the separated signals to a scanning-side display control circuit 17 formed of a semiconductor chip. Further, the A/D conversion circuit 16 operates according to instructions from the scanning side display control circuit 17, converts the video signal sent from the television circuit 12 into a digital signal, and converts the video signal sent from the television circuit 12 into a digital signal. The signal is output to the signal-side display control circuit 18 which is configured by a chip. Then, the display panel 3 is moved by the scanning side display control circuit 17 and the signal side display control circuit 18.

Further, in FIG. 3, reference numeral 20 denotes a calculation function section, which includes a timing signal generation circuit 21, a touch switch 22, a key sense circuit 23, and a CPU (central processing unit) 24. The touch switch 22 is provided in a layered manner on the display panel 3 as described above, and when touched, outputs a sampling signal from the timing signal generation circuit 21 to the key sense circuit 23 according to the operation position. -5= Rust. The content is determined by the key sense circuit 23td and the p-edge switch 22, and is output to the CPU 24. When the computer mode CAL is selected by the mode switch 8, the CPU 24 detects the scanning side display control circuit 12 and the touch operation, and sends the detection signal to the CPU.
Output to 24.

The CPU 24 writes the signal from the key sense circuit 23 into the memory in the scanning side display control circuit I7 as an input four turns, and compares the contents with the standard pattern to recognize it. In this case, the CPU 24 stores the recognition result in the memory as memo data in the TV reception mode, executes arithmetic processing according to the recognition result in the computer mode, and displays the input data, processing results, etc. at that time on the i4 channel. Display on 3.

Next, a touch switch 22 provided on the top surface of the display panel 3 and a key sense circuit 2 for detecting its operation key.
3 will be explained in detail with reference to FIGS. 4 to 7. On the upper surface of the protective glass (or transparent plastic plate) provided on the front surface of the display/arm panel 3, there is a
The transparent touch electrodes 'r, -w'r3o are arranged in a 5×6 matrix. The above touch electrode T1~'r
so is connected to the key sense circuit 23. This key sense circuit 23 calculates the contact capacitance component of each touch electrode 'rt-T' when a human body contacts the touch electrode 'rl-'rso.
io and is configured as shown in FIG. 5.

FIG. 5 shows a basic configuration diagram of the key sense circuit 230. 30 in the figure is a CMOS innovator, and this CM
N-channel MOS that constitutes the OS inverter 30)
A rectangular wave X with a predetermined period (for example, 16 Hz) is applied to the 'r'-) electrodes of 31 Lanzostars (hereinafter referred to as N-MOS) and P-channel MO8) sxB of Lanzostars (hereinafter referred to as P-MOS). has been input, and N
-MOS, VIA, and one end of P-MOS 31B are connected to each other via a tensile resistor 32 of 0MO8IC. Furthermore, a low potential Vllll is supplied to the other end of the N-MOS 31A, and the P-MOS 37
A high potential VDD is supplied to the other end of B via the case 1. And P-MOS 31 B and tensile resistance 32
The connection point with is connected to the touch electrode TI and is also connected to the input side of the CMOS inverter 33. The output B of this inverter 33 is input to another inverter 34 connected in series and is inverted. This inverter 34
The output of is ANDp −) where the square wave X is input
35. The output Y of this ANDf-) J5 is a determined signal used to determine whether or not a human body has touched the touch electrode T1. In addition, C in the figure
x is a stray capacitance component, which is caused by natural phenomena such as wiring capacitance caused by the wiring of the touch electrode T, and f-) capacitance caused by the high input impedance of 0MO8ICP-). Further, Cy in the figure is a contact capacitance component caused by the human body that occurs between the case 1 and the touch electrode T when the human body touches the touch electrode T1 in a state where the human body is in contact with the case 1.

Therefore, when the human body is not touching the touch electrode Tl, the CMOS inverter 30 receives the rectangular wave X shown in FIG.
is input, N-MOS JIA is ON, P
-MOS 31 B is turned off. Therefore, on the input side of the inverter 33, the low potential VSS is connected to the N-MOS 3
1 is input via A. At this time, the inverter 33
Depending on the time constant of the stray capacitance component CI and the tensile resistance 32, the output B of ), the start-up will be delayed. Therefore, the output Y of the AND dart 35 becomes a rectangular wave whose pulse width is equal to the delay amount Dx, as shown by Y (switch OFF) in FIG.

Next, when the touch electrode T1 is touched with the human body, the touch electrode T1
Between Case 1 and Case 1, there is a contact capacitance component Cy due to the human body.
is formed. This contact capacitance component Cy is the stray capacitance component C
Since the output B of the inverter 33 is connected in parallel to Its rise is delayed by a length (Dx+Dy) corresponding to the composite capacitance component. For this reason, andf −)
The output Y of 35 becomes a rectangular wave whose pulse width is equal to the delay amount DI+DyK, as shown by Y (switch ON) in FIG.

FIG. 7 shows the overall configuration of the key sense circuit 33, which includes 30 touch electrodes TI-JI'.

is specified in a time-division manner, and the rectangular waves Y corresponding to the touch electrodes T1 to T3° are sequentially output. That is,
A 5-bit signal a''-'e is inputted to this key sense circuit 23 from the control circuit.

When these 5-bit signals a to e are input to the decoder 36, the decoder 36 outputs signals "'1" to "'30" corresponding to the input 5-bit data, and the corresponding transmission y is outputted from the decoder 36. -) supplied to Gl~aSO. This transmission l--) Gl-G
so is turned ON when the corresponding signals "1" to "30" are at the high VDD level, and a corresponding touch electrode TI-Jrs is connected to one end of so.

10-, and the other end is connected to the connection point of inverters 30 and 33. Therefore, each transmission r) G l-G so is alternatively turned on sequentially.
Then, the touch electrode Tl is connected to the connection point between the inverters 30 and 33 in a time-division manner. Therefore, the rectangular waves Y corresponding to the touch electrodes T1 to T'so are sequentially output from the antenna 35 and supplied to the CPU 24. This CP
The U 24 includes a handwritten input recognition unit, the details of which will be described later, and recognizes and processes the input data from the key sense circuit 23 by this recognition unit.

Therefore, the scanning side display control circuit 17 in FIG.
is constructed as shown in FIG. In the figure, reference numeral 41 denotes a control circuit, which uses the vertical synchronization signal φV and horizontal synchronization signal φH from the synchronization separation circuit 15 in FIG. A conversion circuit 1 that generates a signal φF and fits a chisel enabler signal a
The pulse signals φL1φs1φ2 and φF are sent to the signal side display control circuit 18.

Further, the control circuit 41 writes a "1" signal to the shift register 42, and sequentially shifts the shift register 42 using the clock φL. Then, in accordance with the data shift of the shift register 42, the constant scanning side P writer 43 operates to sequentially scan the display electrodes of the display panel 3. Furthermore, the control circuit 4
1 is the clock pulse φ! on the I10 port 44. ,φ2
is given as a read pulse. A RAM 45 and a ROM 46 for information processing provided in the scanning side display control circuit 17 are connected to this I10 port 44. Above R
The AM 45 is used as an input cut-turn memory for storing processing data of the CPU 24 and for storing input i4 turns during handwriting input. Further, first and second standard 1,000 turns for determining handwritten input are written in the ROM 46 in advance. And the above I10 port 44
is connected to the CPU 24, A/D conversion circuit 16, and signal side display control circuit 18, and performs data input/output processing.

Further, the signal side display control circuit 18 in FIG.
It is constructed as shown in FIG.

In the figure, 51 is an I10 port, and Ilo 71! from the scanning side display control circuit 17! - Data D8 sent from port 44 is input. This port 51 contains ROM (character generator) 52 and RAM.
53 is connected. Above ROM52 and RAM
53 is addressed by the data sent via Ilo f-) 51, and is addressed by the ROM 52.
The data read from Il is written to RAM 53 and
o 4! - sent to port 51. Further, information processing data sent from the scanning side display control circuit 17 is written to this I10 port 5I via the I10 port 51.

This 17-port 5 reads out the television video signal sent from the scanning side display control circuit 17 or the data stored in the RAM 53 and outputs it to the shift register 54. The shift register 54 reads data from the I10 port 51 in synchronization with the shift clock φS from the control circuit 41 and sequentially shifts the data by 13-. The data stored in the shift register 54 is transferred to the buffer 55 by the latch clock φL from the control circuit 41 and sent to the signal side driver/driver 56. The signal side driver 56 generates a gradation signal based on the data from the buffer 55 in accordance with the clock pulse φ2 and the data from the sofa 55, and drives the display A channel 3 for display. In this case, the signal side driver 56 inverts the polarity of the display drive signal in synchronization with the frame switching signal φyK from the control circuit 41 in order to AC drive the display panel 3.

Therefore, the control circuit 41 in the scanning side display control circuit 17 has a vertical counter 6 as shown in detail in FIG.
1. Horizontal counter 62, decoder 63, sampling circuit 64, for example, 6 MHz two-phase clock pulse φ1
, φ snow, and generates various timing signals shown in FIG. Specifically, the vertical counter 61 counts the vertical synchronizing signal φV, and inverts the output signal every time it is counted.

14- The output signal of the vertical counter 61 is sent to the scanning side dryer 743 and the signal side display control circuit 18 as a frame switching signal φF. Further, the horizontal counter 62 counts the horizontal synchronizing signal φH and is reset by the vertical synchronizing signal φV, and the count contents are sent to the decoder 63.

This decoder 63 decodes the count contents of the horizontal counter 62 and outputs a chip enable signal CE, a latch clock φ, m1# data DT, and a sampling f-) time signal GT.

The chip enable signal CE is inverted and output every time the horizontal counter 62 counts up, and the latch clock φL is output every time the horizontal counter 62 counts up, for example, by four. Further, the sampling r-) time signal GT remains at a high level while the clock signal φl is output for a certain period of time, for example, 160 times, at the timing when the chip enable signal CE becomes a low level.

Furthermore, '1'' data DT is output every time the horizontal car counter 2 is reset.The chip enable signal CE output from the decoder 63 and the clock φL are output from the shift register 42 and the signal side. Display control circuit 18, @1″ data DT is shift register 42, sampling? -) The time signal GT is sent to the sampling circuit 64. This sampling circuit 64 generates an oscillator 65 .while the sampling r-) time signal GT is applied. The clock pulse f1 from 160
The signal is output from the shift register 4 as the shift clock φB.
Give to 2. Further, the pulse signal φ output from the oscillator 65 is sent to the signal-side display control circuit 18 as a basic pulse for creating gradations. Furthermore, the clock pulses d' 1 and φ3 outputted from the oscillator 65 are
The signal is sent to the second port 44 as a read signal.

1 in the scanning side display control circuit 17 of FIG.
The two ports 44 are configured as shown in FIG.

In the figure, 7 is an instruction decoder (hereinafter abbreviated as INS decoder), and the INS decoder 7 is supplied with an operation instruction OP and a chip enable signal CEl from the CPU 24. The above INS decoder/71 receives an operation instruction O from the CPU 24.
When both P and chip enable signal CEl are "1#", the fourth ration set mode is entered, and the 4-bit data from the CPU 24 is processed as an operation code (command), and the operation command OP is "O", and the chip enable is set. When the signal CEl is "1", it is not in the execution mode and processes the 4-bit data from the CPU 24 as data.In other words, the INS decoder 71
In the operation set mode, 4-bit data from the CPU 24 is read and decoded via the buffer 76 and the latch circuit 77, and the latch circuits 72h, 72b,
Latch command to 72a, r-to circuit 131L, 73b, 7
3c+73d.

Transfer f-) 74 is given an r-) control signal. Further, 75 is a latch circuit, which transfers data from the conversion circuit 16 to a clock signal φ1. Latch in synchronization with φ. The data latched by the latch circuit 75 is taken out via the dart circuit 73a and the transfer r-) 74 and sent to the signal side display control circuit 18. In addition, the above transfer r −) 7
4 and the data from the CPU 24 are sent to the buffer 7.
8 to the latch circuits 72m+ 72b and 72c. These latch circuits 12t, 72b, 72c
reads input data according to control commands from the INS decoder 71 and provides it to the RAM 45 and ROM 46. That is, the data latched by the latch circuit 72a is stored in the ROM 46 as address data, and then transferred to the latch circuit 7J.
The data latched in b is written to RAM 45, and the data latched in latch circuit 72 is written to RAM 45.
45 as address data. The data read from the ROM 46 is then read out from the f-) circuit 73.
The data read from the RAM 45 is input to the latch circuit 79 via the dart circuit rJd. This latch circuit 79 reads the input data in synchronization with the clock pulses 18-s φ1 and φ2, and transfers the data to the clock pulses 18-
) 74 to the CPU 24 and the signal side display control circuit 18.

Also, I10 in the signal side display control circuit 18 in FIG.
The port 51 is configured as shown in FIG. In the figure, 81 is an instruction decoder (hereinafter referred to as I
An operation command OP and a chip enable signal CE are supplied from the CPU 24 to the NS decoder 81 (abbreviated as NS decoder 81). The INS decoder 81 includes the CPU 24
The operation set mode is entered when both the fourth ration instruction OP and the chip enable signal CE are 11#, and the 4-bit data from the I10 port 44 is processed as an operation code (instruction), and the operation instruction OP is 0. ”, chip insol signal C
E! When is 1”, it is in execution mode, and the above
The 4-bit data from 4 is processed as data. That is, in the operation set mode, the INS7' coder 81 reads and decodes the 4-bit data from the I10J-bit 44 through the buffer 86 and the latch circuit 88, and decodes the data from the latch 82a p 82b.
A latch command is given to +82c, and an f-to control signal is given to r-) circuits 83a, 83b and transfer dart 84. Also, 85 is a latch circuit, and the RAM
53 to r-) The data read out via the circuit 83a is input to the clock pulses φtrue and φ2 and read. The data latched by latch circuit 85 is read out via transfer gate 84 and input to buffers 116 and 87. Further, data sent from the I10 port 44 of the scanning side display control circuit 17 is input to the buffers 86 and 87. The output of the buffer 86 is then sent to a latch circuit 88 and a latch 82a.

82b and 82cVC are input. The latch circuit 88 reads input data and inputs it to the INS decoder 81 in synchronization with clock pulses φl and φ2. Further, latch circuits 821L, 82b, and 82c latch input data according to commands from the INS decoder 81, and
They are given to the ROM 52 as write data and address data, respectively.

Further, the output of the buffer 87 is sent to a latch circuit 89. This latch circuit 89 reads input data in synchronization with the clock pulses φl and φ, and the r-t circuit 83
It is output to the shift register 54 via b.

Next, details of the handwritten input recognition section in the CPU 24 will be explained with reference to FIG. Keys depending on handwriting operation
The data output from the sense circuit 23 is processed as coordinate data corresponding to each operation key, sent to the scanning side display control circuit 17, and written into the input arm turn memory 45a in the RAM 45. This RAM 45 is used for memo data storage and as an input memory 451. The pattern data stored in the input pattern memory 45a is then sent to the first feature extraction section 241, where features for each stroke of the input character are extracted.

The first feature extracted by the first feature extracting section 241 is sent to the first matching section 21-7 section 242 and compared with the standard pattern sequentially read out from the first standard pattern memory 46h. This first
The standard) arm turn memory 461L is configured in the ROM 46 of the scanning side display control circuit 17, and is a standard iJ? Stroke characteristics for turns are stored. The first matching unit 242 performs character recognition by comparing the input f-turn with the stroke characteristics of the standard pattern.
If the recognition result is not determined to be one character, the matching result is sent to the second feature extraction unit 243 and the second matching unit 24.
Output to 4. The second feature extracting unit 243 extracts a second feature from the input character turn stored in the input character turn memory 45h when the first feature extraction unit 241 cannot recognize the specific character. That is, the second feature extraction unit 243 determines the relative position of the stroke from the relationship between the start point and end point of each stroke of the input character, and determines the relative position of the stroke from the relationship between the start point and end point of each stroke of the input character, the distance between the start point and end point for characters with a -stroke, and the distance between the start point and end point for characters with two or more sides. , and extracts features from the distances between the end points and outputs them to the second matching section 244.

=22− This second matching section 244 is a second feature extracting section 243
and the data from the first matching section 242 and the second [quasi]
Standard No' that stores f-turn memory 46bK? The characters to be recognized are determined by sequentially comparing them with the turns. This second standard pattern memory 46b is connected to the RO of the scanning side display control circuit 17.
Constructed within M46. However, the 14th above? Character data D1 of characters recognized by the feature extraction unit 241 and character data D recognized by the second matching unit 244
2 is sent to selector 245. This selector 245
input data D1 . by the select signal SK output from the first matching section 242. Select D2. That is, the first matching section 242 selects the character data D1 from the first matching section 242 when the recognition result is determined to be one character, and the character data D2 from the second matching section 244 when the recognition result is not determined to be a - character. 245, the select signal S is output.

Then, the character data D selected by the selector 245
1 or D2 is sent to RAM4J and stored.

In this case, the CPU 24 detects the input of a specific character or the unattended state of data for a certain period of time or more, and ends the data input process for one screen.

Next, the overall operation of the above embodiment will be explained. When receiving television radio waves, select vHF or UHF using the mode switch 8 in FIG. When the power switch is turned on in this state, the radio waves received by the antenna 9 are tuned by the tuner 11, converted to an intermediate frequency, and sent to the television circuit 12. This television circuit 12 amplifies and detects the signal from the tuner 11 and outputs it as a television video signal and an audio signal.

This audio signal is sent to the audio circuit 13, amplified, and output from the speaker 14. Further, the video signal output from the television circuit 12 is input to the sync separation circuit 15 and the ω conversion circuit 16. The synchronization separation circuit I5 separates the horizontal synchronization signal φ■ and the vertical synchronization signal φV contained in the input video signal and supplies them to the scanning side display control circuit 12.

In addition, the line conversion circuit 16 is kept in an operating state by the scanning side display control circuit 27 in the television reception mode.
The video signal sent from the television circuit 12 is converted into a digital signal and output to the scanning side display control circuit 17. The data sent from the Φ conversion circuit 16 to the scanning-side display control circuit 17 is input to the port 44 as shown in FIG. As shown in FIG.
and various timing signals φL, based on the horizontal synchronization signal φ■.
φS.

φ? and “1# generates data DT. I10 port 4
4 is the clock/intermediate pulse φl as shown in FIG.
, φ3 is read from the conversion circuit 16 into the latch circuit 75, and the data is outputted to the signal side display control circuit 18 via the Y-to circuit 13m and the transfer Y-door 4. In addition, in FIG. 8, the 11" data DT output from the control circuit 41 is
- The signals are sent to the ZOSTER 42 and sequentially shifted within the shift register 42 in synchronization with the clock φL. The scanning side driver 43 operates in accordance with the data shift of the shift register 42, and sequentially scans the common side electrodes of the display panel 3.

On the other hand, when the signal side display control circuit 18 shown in FIG. 54, read it into the shift register 54 in synchronization with the shift clock φ8, and shift it sequentially. The data written in the shift register 54 is transferred to the buffer 55 by the latch clock φL and input to the signal side driver 56. The signal side driver 56 generates a gradation signal in synchronization with the input data from the buffer 55 in synchronization with the clock signal φ, and drives the segment side electrodes of the display channel 3 for display. below,
A similar operation is performed, and the display panel 3 is driven in accordance with the video signal from the television circuit 12, and a television image is displayed.

Therefore, while receiving TV as described above, if you want to take notes on the answers to prize quizzes, the name of the broadcasting station, the address to send the answers, etc. to a quiz show, etc., you can use the display panel 3 while receiving TV as described above. Trace the top with your finger and write down what you want to write down. The touch switch 22 is turned on in response to the finger movement at this time, and a key sense signal is sent from the key sense circuit 23 to the CPU 24. When the signal is input from the key sense circuit 23, the CPU 24 recognizes the content of the handwritten input using the recognition unit shown in FIG. 14 as described above, and writes the recognition result to the RAM 45, as shown in FIG. The following shows an example of memorized memos related to prize quizzes.

The input method is, for example, by first drawing a / (slash) on the screen, the initial state is set, the RAM 45 is cleared, and the next character drawn is recognized and input. If we assume that the capacity to store characters is the same as that of a TV screen, then the TV screen has 12
0x160 dots, 1 character is 5x7 dots (4x4 dots)
- 8x8 dots including space), 15x20 characters can be stored.

Writing starts from the (1, 1) character address, and the character address is updated every time one character is input. The space is u1 and the line feed is ν. When the data input is finished, the user inputs a specific character, symbol, etc. indicating the end of the input, or ends the data input as is. The CPU 24 detects the input of a specific character or the unattended state of data for a certain period of time, and
The writing of one screen data to AM 45 is completed.

The contents stored in this RAM 45 are displayed on the display iR channel 3 by specifying the computer mode and inputting a display command symbol.

Further, when selecting a function of the computer, first, the mode of the computer (CAL) is specified using the mode switch 8. When the mode of this CAL is specified, the CPU 24
are the scanning side display control circuit 17 and the signal side display control circuit 18
For the operation code OP and the chizo enable signal CE,

Output Cat, I10 port 44, I10 port 51
Enter. When the I10 port 44 in the scanning side display control circuit 17 is supplied with the chip enable signal CEl, the INS decoder 71 decodes the command from the CPU 24 as shown in FIG. 12, and controls the operation of each part. The INS decoder 71 firstly converts the r-) circuit 7
3a is closed to prohibit the input of the television video signal from the line conversion circuit 16, and then data or address data from the CPU 24 is written to the latch circuits 72IL, 72b, and r2e via the buffer 78, and the RAM 45
, ROM 46, etc. And this RAM
45 or ROM J 6 is latched by the latch circuit 79 via the r~t circuit 73C273d, and sent to the signal side display control circuit 18 via the transfer f-) 74. Further, the I10 port 44 directly outputs data sent from the CPU 24 to the signal side display control circuit 18. As shown in FIG. 13, this signal side display control circuit 18 sends a command from the CPU 24 to an INS decoder 81 and decodes it to control each circuit. In other words, the Tao port 51 reads the ROM 52 in response to a command from the CPU 24.
, RAM, 53 and transfers data from the CPU 24 or data read from the ROM 52 to the RAM.
Write to 53. Then, the data stored in the RAM 53 is read out to the shift register 54 and displayed on the display panel 3 as described above.

In the computer mode, when input operation is performed on the equal key after inputting calculation data by handwriting, the CPU 24 recognizes the input data, performs calculation processing, and displays the calculation result on the display panel 3. indicate. In other words, when in TV mode, the input data is simply stored as memo data, but when in calculator mode, it is stored as 10, -1X% like a normal calculator.
Depending on the input of function data such as ÷, the operand,
It is stored in the RAM 45 as an arithmetic number. RAM 45
is divided into areas such as operand register, calculation register, and result register, and the data written to these registers is compiled as appropriate and display data is created in RAM 5J, which is displayed on the monitor screen. is accomplished.

In the above embodiment, the touch electrode was provided on the surface of the display i4 panel 3, but it may be provided on the inside of the panel.

〔Effect of the invention〕

As described in detail above, according to the present invention, a touch switch for handwriting input is provided on the display panel of a pocket television, and a pattern recognition means for recognizing input and turns from this touch switch is provided. It is possible to perform handwritten input and arithmetic processing based on human power without deteriorating the appearance of the screen while maintaining its shape.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention, in which Fig. 1 is a perspective view showing the external appearance, Fig. 2 is a front view, Fig. 3 is a block diagram showing the overall configuration of the electronic circuit, and Fig. 4 is a display. FIG. 5 is a diagram showing the touch electrode provided on the nof channel, FIG. 5 is a diagram showing the touch electrode and part of the key sense circuit, and FIG. 6 is a signal waveform for explaining the operation of the key sense circuit in FIG. 5. 7 is a diagram showing the overall configuration of the Giessens circuit, FIG. 8 is a block diagram showing the configuration of the scanning side display control circuit, FIG. 9 is a block diagram showing the configuration of the signal side display control circuit, and FIG. 10 is a block diagram showing the configuration of the signal side display control circuit. The figure is a block diagram showing the configuration of the control circuit in the scanning-side display control circuit of Fig. 8, Fig. 11 is a timing chart for explaining the operation of the control circuit, and Fig. 12 is the scanning-side display control circuit of Fig. 8. FIG. 13 is a block diagram showing details of the I10 port in the circuit. FIG. 13 is a block diagram showing details of the hub port in the signal side display control circuit of FIG. FIG. 14 is a block diagram showing details of the handwritten input recognition section in the CPH, and FIG. 15 is a diagram showing an example of handwritten input data storage. DESCRIPTION OF SYMBOLS 1...Case, 11...Front side case, 1b...Back side case, 3...Display quantity panel, 8...Mode switch, 12...TV circuit, 15...Sync separation circuit , Noro... Line conversion circuit, 17... Scanning side display control circuit, 18... Signal side display control circuit, 20... Calculation function section, 22... Touch switch, 23... Key sense Circuit, 24...CPU, 30...CMOS inverter, 31 people...MOS) Lanzostar, 31B...
- MOS transistor, 41... control circuit, 44.
51...I10 port), 45153...RAM, 4
6.52... ROM, 71.81... Instruction decoder, 72&~72C175, 77, 79,
821L+82b, 85. lI8+89...Latch circuit, 74,114...Transfer? -), 76.1
B, 86.87... Nonots 7a, 45g... Input cover turn memory, 46a... 1st standard z and turn memory, 46b... 2nd standard 4 no? Turn Memo I), 241・
...first feature extraction section, 242...first matching section,
243...Second feature extraction unit, 244...Second matching unit, 245...Selector. Applicant's agent Patent attorney Takehiko Suzue 33-

Claims (1)

[Claims] A display i4 channel that displays images received by the television receiver circuit, a plurality of touch keys provided on the surface of this display panel, and all operations of the touch keys. A key sense circuit for detection, an input key turn memory for storing the pattern of key manual data detected by the key sense circuit, a standard four turn memory for storing the standard number F turn, and the above input cover turn memory. An incoming cover turn data recognition means performs i4 turn matching stored in the stored pattern and the standard i+turn, and calculation processing is performed based on the incoming cover turn data recognized by this person's mother turn data recognition means. and processing means for displaying the processing results on the display panel.