JPS60189270A - Manufacture of compound semiconductor device - Google Patents
Manufacture of compound semiconductor deviceInfo
- Publication number
- JPS60189270A JPS60189270A JP4441584A JP4441584A JPS60189270A JP S60189270 A JPS60189270 A JP S60189270A JP 4441584 A JP4441584 A JP 4441584A JP 4441584 A JP4441584 A JP 4441584A JP S60189270 A JPS60189270 A JP S60189270A
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- low
- layer
- type
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 150000001875 compounds Chemical class 0.000 title claims abstract description 7
- 239000004065 semiconductor Substances 0.000 title claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000012535 impurity Substances 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims abstract description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 7
- 238000000137 annealing Methods 0.000 claims abstract description 7
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 238000001947 vapour-phase growth Methods 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract description 3
- 239000012808 vapor phase Substances 0.000 abstract description 2
- 230000003213 activating effect Effects 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 6
- 238000009826 distribution Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/93—Variable capacitance diodes, e.g. varactors
Abstract
Description
【発明の詳細な説明】
（技術分野）
本発明は化合物半導体装置の製造方法に関し、特にヒ化
ガリウム（ＧａＡｓ）の超階段接合バラクタの製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing a compound semiconductor device, and more particularly to a method for manufacturing a superstep junction varactor of gallium arsenide (GaAs).
（従来技術）
近年１発振器の周波数変換器、変調器としてバラクタダ
イオードが広く使用されている。これは逆方向バイアス
を印加することによって接合容量が変化することを利用
したもので、特に小さな印加電圧で大きな容址変化比が
得られる超階段接合のものが有利である。(Prior Art) In recent years, varactor diodes have been widely used as frequency converters and modulators for single oscillators. This utilizes the fact that the junction capacitance changes by applying a reverse bias, and a hyperstep junction is particularly advantageous because it can provide a large capacity change ratio with a small applied voltage.
このような超階段接合のＳｉバラクタはＴＶチューナ等
に広く利用されている。最近直列抵抗が小さく出来、そ
の結果Ｑの高い容量となるＧａＡｓの超階段接合バラク
タの開発がさかんとなっている。Such super-step junction Si varactors are widely used in TV tuners and the like. Recently, there has been an active development of GaAs superstep junction varactors, which have a small series resistance and, as a result, a high Q capacitance.
第１図は従来の代表的な超階段接合の不純物濃度分布を
示す図である。第１図に示すように。FIG. 1 is a diagram showing the impurity concentration distribution of a typical conventional hyperstep junction. As shown in Figure 1.
低抵抗Ｎ型ＧａＡｓ基板１に不純物ｍ度が５８１０１５
ｃｍ−３程度のｎ型高抵抗層２と１０１６〜１０１７８
ｍ 程度の不純物濃度を有するｎ型低抵抗層３にＰ型の
低抵抗層４が形成されたものである。The impurity level is 581015 in the low resistance N-type GaAs substrate 1.
n-type high resistance layer 2 of about cm-3 and 1016 to 10178
A P-type low-resistance layer 4 is formed on an n-type low-resistance layer 3 having an impurity concentration of approximately m2.
このような不純物濃度分布を有するＱａＡｓウェーハに
所定の電極を形成して超階段接合バラクタを製造するも
のである。A superstep junction varactor is manufactured by forming predetermined electrodes on a QaAs wafer having such an impurity concentration distribution.
従来、上記不純物濃度分布のウェーハを製造する方法と
しては、低抵抗基板１に気相成長によって高抵抗層２が
形成されたエピタキシャルウェーハにＳｉヲ不純物とし
たイオン注入によってｎ型低抵抗層３を形成したのちＺ
ｎ、拡散等によりＰ型低抵抗層４を形成していた。しか
し所要の容量−電圧特性を得るためには上記低抵抗層３
の厚さの制御が最も厳しく要求され、イオン注入でこの
厚さを厳しく押えても、その後のＰ型低抵抗層形成の拡
散のバラツキ等で変化し、目標とする容量−電圧特性を
安定して得ることが難しい。一般的に上記ｎ型の高濃度
Ｉｉｌ！３の厚さは種々の要求、容量−電圧特性から０
．５〜１．０μｍの範囲に設定されるが、この厚さを±
１０％程朋に制御しなければならず、このような条件に
適合した製品の製造は困難で、すなわち量産性に欠ける
という欠点があった。Conventionally, as a method for manufacturing a wafer with the above impurity concentration distribution, an n-type low resistance layer 3 is formed by ion implantation with Si as an impurity into an epitaxial wafer in which a high resistance layer 2 is formed on a low resistance substrate 1 by vapor phase growth. After forming Z
A P-type low resistance layer 4 was formed by diffusion or the like. However, in order to obtain the required capacitance-voltage characteristics, the low resistance layer 3
The most stringent requirement is to control the thickness of the capacitance, and even if this thickness is strictly controlled by ion implantation, it will change due to variations in diffusion during the subsequent formation of the P-type low resistance layer, making it difficult to stabilize the target capacitance-voltage characteristics. difficult to obtain. Generally, the above n-type high concentration Iil! The thickness of 3 is 0 due to various requirements and capacitance-voltage characteristics.
．． The thickness is set in the range of 5 to 1.0 μm, but the thickness can be changed to ±
It is necessary to control the temperature by about 10%, and it is difficult to manufacture products that meet such conditions, which has the drawback of lacking mass productivity.
また、一方最近Ｐ 層を使用しない方法として前記Ｎ型
低抵抗層３に直接金属を接続したショットキバリア型の
超階段バラクタが発表されたが、これは順方向電流の立
上り電圧がＰ」Ｎ接合を有したものに比べ低いために大
きな信号の発振器には適さないという欠点がある。On the other hand, a Schottky barrier type hyper-step varactor in which a metal is directly connected to the N-type low resistance layer 3 has been recently announced as a method that does not use a P layer, but this is because the rising voltage of the forward current is It has the disadvantage that it is not suitable for large signal oscillators because it is lower than those with oscillators.
（発明の目的ン
本発明の目的は１以上の欠点を除去し、低抵抗層の厚さ
が厳密に制御でき、容量−電圧特性を特徴とする特性が
安定して得ることが出来る化合物半導体装置の製造方法
を提供することにある。(Objective of the Invention) The object of the present invention is to eliminate one or more drawbacks of a compound semiconductor device in which the thickness of the low resistance layer can be strictly controlled and characteristics characterized by capacitance-voltage characteristics can be stably obtained. The purpose of this invention is to provide a method for manufacturing the same.
（発明の構成）
本発明の化合物半導体装置の製造方法は、低抵抗ヒ化ガ
リウム基板上に該基板と同一導電型の所定の不純物濃度
、厚さを有する高抵抗層が形成されたヒ化ガリウムウェ
ーハにおいて、該ウェーハにイオン注入、アニールによ
って前記高抵抗層と同一導電型で不純物濃度の高く所定
の厚さを有する低抵抗層を形成する工程と、前記低抵抗
層の上に、該低抵抗層と反対の導電型を有する低抵抗層
をエピタキシャル成長により形成する工程とを含んで構
成される。(Structure of the Invention) A method for manufacturing a compound semiconductor device according to the present invention includes forming a high resistance layer on a low resistance gallium arsenide substrate and having a predetermined impurity concentration and thickness of the same conductivity type as the substrate. In the wafer, a step of forming a low resistance layer having the same conductivity type as the high resistance layer, high impurity concentration, and a predetermined thickness by ion implantation and annealing into the wafer, and forming the low resistance layer on the low resistance layer. The method includes a step of forming a low resistance layer having a conductivity type opposite to that of the layer by epitaxial growth.
（実施例）
以下１本発明の実施例について１図面を参照して説明す
る。第１図は従来の代表的な超階段接合の不純物濃度分
布を示す図であるが１本発低抵抗基板１に気相成長によ
って ｓ ｘ １０１１０１５ａ 程度のｎ型高抵抗エ
ピタキシャルＮ２を形成した後、Ｓｉ等全不純物とした
イオン注入続いてアニールすることによ、 １ｏ１６〜
１０１７ｃ ｍ−３程度のｎ型低抵抗層３を規定厚さに
形成する。このイオン注入層の厚さはドーズ量並びに加
速電圧の制御により精密に制御できる。また打込みイオ
ンの活性化のアニールは比較的低温で活性化できるため
注入層の深さはあまり変化することはなく設計値通りの
Ｎ型低抵抗層の厚さを得ることは容易である。(Example) An example of the present invention will be described below with reference to one drawing. FIG. 1 is a diagram showing the impurity concentration distribution of a typical conventional super-step junction. After forming an n-type high-resistance epitaxial layer N2 of about s x 1011015a by vapor phase growth on a single low-resistance substrate 1, By ion implantation with all impurities such as Si, followed by annealing, 1o16 ~
An n-type low resistance layer 3 of about 1017cm-3 is formed to a specified thickness. The thickness of this ion-implanted layer can be precisely controlled by controlling the dose and accelerating voltage. Further, since the implanted ions can be activated at a relatively low temperature during annealing, the depth of the implanted layer does not change much, and it is easy to obtain the thickness of the N-type low resistance layer as designed.
次に％気相エピタキシャル成長によりＰ型低抵抗層４を
形成する。この形成は９００°Ｃ程度で数十分のエピタ
キシャルにより形成できる。Next, a P-type low resistance layer 4 is formed by vapor phase epitaxial growth. This formation can be done by epitaxially performing several tens of minutes at about 900°C.
従来の拡散法によるときは、拡散条件でＰ型不純物が急
速に拡散し時によりＮ型低抵抗層をつきぬけることがあ
り、またこの拡散の深さの制御性非常に困難であったが
１本実施例では比較的低温のエピタキシャル成長法によ
りＰ型低抵抗層全形成するので若干の不純物の移動はあ
るがその量は少く十分制御出来る。以上により本発明の
一実施例による制御されたバラクタの超階段接合を形成
することができ、これに所定の電極を形成すれば超階段
接合を有するバラクタは完成する。When using the conventional diffusion method, the P-type impurity diffuses rapidly under the diffusion conditions, sometimes penetrating the N-type low resistance layer, and it is extremely difficult to control the depth of this diffusion. In this embodiment, the entire P-type low resistance layer is formed by epitaxial growth at a relatively low temperature, so although some impurity movement occurs, the amount is small and can be sufficiently controlled. As described above, a controlled hyper-step junction of a varactor according to an embodiment of the present invention can be formed, and by forming a predetermined electrode thereon, a varactor having a hyper-step junction is completed.
なお、実施例ではエピタキシャル成長によるＰ型低抵抗
層の形成は気相成長法によったが液、相エピタキシャル
法によっても出来ることは説明するまでもない。In the embodiment, the P-type low resistance layer was formed by epitaxial growth using a vapor phase growth method, but it goes without saying that it can also be formed by a liquid phase epitaxial method.
（発明の効果）
以上説明したとおり１本発明によれば、Ｎ型低抵抗層の
厚さ等はイオン注入、アニールの条件のみによって決定
し、最も問題とされた後のＰ＋型低抵抗層形成時の拡散
等の影響を受けないため所定の容量−電圧特性を安定し
て得ることが出来る。(Effects of the Invention) As explained above, according to the present invention, the thickness etc. of the N-type low resistance layer are determined only by the ion implantation and annealing conditions, and the formation of the P+ type low resistance layer after the most problematic Since it is not affected by time diffusion, etc., a predetermined capacitance-voltage characteristic can be stably obtained.
第１図は代表的な超階段接合の不純物濃度分布を示す図
である。
ｌ・・・・・・Ｎ型低抵抗ＧａＡｓ基板、２・・・・・
・Ｎ型高抵抗エピタキシャル層、３・・・・・・イオン
注入形成によるＮ型低抵抗層、４・・・・・・Ｐ型低抵
抗層。
表１ｄ力゛÷のＩｆ−’夕十シャＪＬ層力Ｋｙ亭１１￥
ＩFIG. 1 is a diagram showing the impurity concentration distribution of a typical hyperstep junction. l... N-type low resistance GaAs substrate, 2...
- N type high resistance epitaxial layer, 3... N type low resistance layer formed by ion implantation, 4... P type low resistance layer. Table 1d force ÷ If-' Yujusha JL layer force Kyitei 11 yen
I
Claims (1)
の不純物濃度、厚さを有する高抵抗層が形成されたヒ化
ガリウムウェーハにおいて。 該ウェーハにイオン注入、アニールによって前記高抵抗
層と同一導電型で不純物濃度の高く所定の厚さを有する
低抵抗層を形成する工程と。 前記低抵抗層の上に該低抵抗層と反対の導電型を刹する
低抵抗層をエピタキシャル成長により形成する工程とを
含むこと全特徴とする化合物半導体装置の製造方法。[Scope of Claim] A gallium arsenide wafer in which a high resistance layer having a predetermined impurity concentration and thickness of the same conductivity type as the substrate is formed on a low resistance gallium arsenide substrate. forming a low resistance layer having the same conductivity type as the high resistance layer, high impurity concentration, and a predetermined thickness by ion implantation and annealing into the wafer; A method for manufacturing a compound semiconductor device, comprising the step of forming, by epitaxial growth, a low resistance layer having a conductivity type opposite to that of the low resistance layer on the low resistance layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4441584A JPS60189270A (en) | 1984-03-08 | 1984-03-08 | Manufacture of compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4441584A JPS60189270A (en) | 1984-03-08 | 1984-03-08 | Manufacture of compound semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60189270A true JPS60189270A (en) | 1985-09-26 |
Family
ID=12690865
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4441584A Pending JPS60189270A (en) | 1984-03-08 | 1984-03-08 | Manufacture of compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60189270A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62285476A (en) * | 1986-06-03 | 1987-12-11 | Nec Corp | Manufacture of varactor diode |
| JPS63300570A (en) * | 1987-05-29 | 1988-12-07 | Nec Corp | Manufacture of gallium arsenide hyper abrupt varactor diode |
| JPH05206486A (en) * | 1992-01-13 | 1993-08-13 | Nec Corp | Manufacture of gaas varactor diode |
-
1984
- 1984-03-08 JP JP4441584A patent/JPS60189270A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62285476A (en) * | 1986-06-03 | 1987-12-11 | Nec Corp | Manufacture of varactor diode |
| JPS63300570A (en) * | 1987-05-29 | 1988-12-07 | Nec Corp | Manufacture of gallium arsenide hyper abrupt varactor diode |
| JPH05206486A (en) * | 1992-01-13 | 1993-08-13 | Nec Corp | Manufacture of gaas varactor diode |
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