JPS60187938U - microcomputer device - Google Patents

microcomputer device

Info

Publication number
JPS60187938U
JPS60187938U JP7278084U JP7278084U JPS60187938U JP S60187938 U JPS60187938 U JP S60187938U JP 7278084 U JP7278084 U JP 7278084U JP 7278084 U JP7278084 U JP 7278084U JP S60187938 U JPS60187938 U JP S60187938U
Authority
JP
Japan
Prior art keywords
clock
division ratio
frequency division
microcomputer device
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7278084U
Other languages
Japanese (ja)
Inventor
岩橋 清太郎
松田 良行
増田 治樹
Original Assignee
オムロン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by オムロン株式会社 filed Critical オムロン株式会社
Priority to JP7278084U priority Critical patent/JPS60187938U/en
Publication of JPS60187938U publication Critical patent/JPS60187938U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の構成を示す概略ブロック図、第2図は
本考案に係るマイクロコンピュータの一実施例の構成を
示す回路図、第3図は分周比設定器16の設定状態とマ
イクロセッサ18に供給されるクロック周波数との関係
を示す図、第4図は第2図における各部の動作波形を示
すタイミングチャートである。 10・・・マイクロコンピュータ装置、12・・・クロ
ック発振回路、14・・・可変分周回路、16・・・分
周比設定器、18・・・マイク西プロセッサ。
FIG. 1 is a schematic block diagram showing the configuration of the present invention, FIG. 2 is a circuit diagram showing the configuration of an embodiment of the microcomputer according to the present invention, and FIG. FIG. 4 is a timing chart showing the operation waveforms of each part in FIG. 2. FIG. DESCRIPTION OF SYMBOLS 10... Microcomputer device, 12... Clock oscillation circuit, 14... Variable frequency division circuit, 16... Frequency division ratio setter, 18... Microphone west processor.

Claims (1)

【実用新案登録請求の範囲】 基準クロックの発振源となるクロック発振回路と; 外部から与えられた分周比設定情報に応じた分周比で、
前記基準クロックを分周してドライブ用クロックを形成
する可変分周回路と; 前記可変分周回路に対して、分周比設定情報を供給する
ための分周比設定器と; 前記ドライブ用クロックをシステムクロックと、   
して動作するマイクロプロセッサとからなることを特徴
とするマイクロコンピュータ装置。
[Claims for Utility Model Registration] A clock oscillation circuit that serves as an oscillation source for a reference clock; and a frequency division ratio according to frequency division ratio setting information given from the outside;
a variable frequency divider circuit that divides the frequency of the reference clock to form a drive clock; a frequency division ratio setter that supplies frequency division ratio setting information to the variable frequency divider circuit; and the drive clock. the system clock,
A microcomputer device comprising: a microprocessor that operates as a microprocessor;
JP7278084U 1984-05-18 1984-05-18 microcomputer device Pending JPS60187938U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7278084U JPS60187938U (en) 1984-05-18 1984-05-18 microcomputer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7278084U JPS60187938U (en) 1984-05-18 1984-05-18 microcomputer device

Publications (1)

Publication Number Publication Date
JPS60187938U true JPS60187938U (en) 1985-12-12

Family

ID=30611509

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7278084U Pending JPS60187938U (en) 1984-05-18 1984-05-18 microcomputer device

Country Status (1)

Country Link
JP (1) JPS60187938U (en)

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