JPS60187813A - Detecting system on abnormality of absolute signal of absolute encoder - Google Patents

Abstract

PURPOSE:To detect the abnormality of an absolute signal, by adding incremental signals in one direction while subtracting incremental signals in the reverse direction, and by determining the result of these operations. CONSTITUTION:When an incremental signal P is inputted from an OR circuit G3 after an absolute signal A is inputted to an input end D of FFF1, a counter C count the signal P to be added. When the input of the signal A is discontinued, the count value of the counter C is stored in a latch circuit R. The count value of the signal P generated during a period when the signal A is outputted shows a definite figure if the signal A is normal. Therefore, any abnormality of the signal A can be detected from the count value of the counter C.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention and Objects of the Invention The present invention relates to an absolute signal abnormality detection method for an absolute pulse encoder that uses both absolute and incremental signals.

A pattern for absolute signals and a pattern for incremental signals are arranged geometrically on a rotating disk, and the rotating disk is attached to the shaft of a motor. Obtain the absolute signal and incremental signal from the incremental signal pattern and determine the rotational position 2 of the motor.
Direction of rotation.

Pulse encoders for obtaining rotational speed and the like are well known. In such a pulse encoder.

If the motor is rotated in a fixed direction, the same number of incremental signals will be generated within each unit of absolute signal. For example, a fixed number of incremental signals ranging from tens to hundreds are generated in the lowest unit of the absolute signal.

On the other hand, the AbFlu 1 signal may exhibit an abnormality due to dust adhering to the rotating disk, a defect in a device such as a driver or receiver, or a defect during transmission. Therefore,
The present invention is directed to the above-mentioned absolute unit.
The purpose of this invention is to detect abnormalities in the absolute signal by utilizing the fact that the number of incremental signals is constant.

Structure of the Invention The present invention provides a pulse encoder that outputs an absolute signal and an incremental signal, and outputs 20 incremental signals during one absolute signal output during rotation in one direction, in which the incremental signal in one direction is not caulked. , the incremental signal in the opposite direction is subtracted n
An absolute system in which a reversible counter consisting of bits is provided, the counter counts the incremental signals outputting one absolute signal, and an abnormality in the absolute signal is detected by detecting that the counting result of the reversible counter is not zero. This is an absolute signal abnormality detection method for encoders.

Embodiment FIG. 1 shows an embodiment in which the absolute signal abnormality detection method of the present invention is implemented, in which Fl and F2 are D-type flip-flops, G1 is an exclusive OR, C is an up/down counter, R is a latch circuit, G2 and G3 are OR circuits.

Further, A indicates the output of the absolute signal value in the lowest unit of the absolute signal, and -P indicates a positive incremental signal and a negative incremental signal, respectively. The absolute signal A is input to the input terminal of the flip-flop F1, and the output Q of the flip-flop F1 is input to the input terminal of the flip-flop F2. F2
The clock end of GK is positive.

The output of an OR gate G3 that receives negative incremental signals P and -P is input. The output Q of each Noritsu flop F1°F2 is inputted to the exclusive OR G1, and the output is inputted to the reset terminal of the counter C and the latch circuit R, and is inputted to the reset terminal of the counter C and the latch circuit R. Furthermore, a positive incremental signal P is input to the addition terminal U of the counter C, and a negative incremental signal -P is input to the subtraction terminal, and the count value of the counter C is latched by the signal from the exclusive OR G1. The output of the latch circuit R is stored in the circuit R, and the output of the latch circuit R is output via the OR circuit G2.Then, the absolute signal of the lowest unit @ the incremental signal output during the A period is Assuming that the number of signals is N and the jJ counter C is composed of n bits, the number N of incremental signals in the absolute signal A, which is the lowest unit, and the bits of the counter C are calculated so that N=2n. The number 11 of is adjusted.As a result, when the counter C counts the number N of incremental signals in the absolute signal A of the lowest unit, its outputs 0-1 to 0-0 all become "0"2, - Next, the operation of the above embodiment will be explained with reference to the timing chart of FIG.

In FIG. 2, (a) is the absolute signal A, (b) is the incremental signal P, -P output from the OR circuit G3, (c) is the output of the flip-flop F1, (
d) shows the output of the Noritsu flop F2, (e) shows the output of the exclusive OR G1, and (f) shows the count value of the counter C.

Absolute signal A of a certain value is sent to flip-flop F1
After the positive or negative incremental signal P, -P is input from the OR circuit G3, it is assumed that the positive incremental signal P is input. The 70-tube F1 is set and outputs an output Q (see FIG. 2 (c)). After this output Q is input to the input terminal of the flip-flop F2, the flip-flop F2 is set by the incremental signal P and outputs the output Q (see FIG. 2(d)). As a result, the output j of the exclusive OR G1, which receives the outputs of the two slip flops Fl and F2, is outputted as shown in FIG. 2 (Bo), and the counter C is reset. On the other hand, since the incremental signal P is input to the addition terminal of the counter C, the incremental signal P input after the counter C is reset will be counted and added (see Figure 2). reference).

In this way, the incremental signal P is added,
When the absolute signal A disappears, the flip-flop F1 loses the absolute signal A, is inverted by the next incremental signal P, and output Q disappears.

In addition, flip-flop F2 is also a flip-flop]:1
The output Q disappears and is inverted by the next incremental signal P, and the output disappears. As a result, the exclusive OR G1 outputs a pulse as shown in FIG.

By the way, as shown in FIG. 2, the counter C counts the number of incremental signal elements P output during the period in which the absolute signal A is output (the number of incremental signal elements P output during the period in which the absolute signal A is output) is The two incremental signal children P immediately after are not counted, but the two incremental signal children P immediately after the absolute signal is lost are counted, so Abflu 1~signal j%A is the number N of incremental signal children P that is being output. (The count value N of the counter C becomes equal), and the number of incremental signal elements P generated during the period in which the absolute signal A is outputted is a constant number N if it is normal.

Therefore, when the counter C counts the certain number N, the output of the counter C at that time is 0-
1 to Q-n are all rOJ.

As a result, if normal, all rOJ will be stored in the latch R, and nothing will be output from the A circuit G2. However, there is an abnormality in absolute signal A,
Counter C counts more or less than a certain number N,
The latch circuit R is set by the output from exclusive OR G1.
When the counter C is activated and the value of the counter C at that time is stored in the latch circuit R, the output of the counter C is C)-1 to Q-.
Since at least one of n is not rol, an output signal is output from the OR circuit G2 and an abnormal signal is output.

By using this output, a lamp or the like can be turned on to notify of an abnormality in the pulse coder.

In the above example, a case has been described in which the motor rotates in the normal direction, but the only difference is that when the motor rotates in the reverse direction and the incremental signal -P is output, the counter C is decremented, and the other operations are the same. In this case as well, if normal, the latch circuit R
The values of the outputs 0-1 to Q-n of the counter C stored in are rOJ, so no output is output from the OR circuit G2, but if the absolute signal A is abnormal, the latch circuit At least one value is stored in R.
Since it is no longer OJ, an abnormal signal is sent from OR circuit G2.

Also, even when the motor is reversed, +mL+
J-J+IJ+〒-He/r-1S+hIIJ'71i
11. ” 1 = ≠ Since the reversal incremental signal -P is subtracted by adding a to C, only “O” is stored in the latch circuit R, and in this case, only when an abnormality occurs, the OR circuit G2 outputs an abnormality signal. A signal will be output.

Note that in the above embodiment, abnormality detection is performed based on the number of incremental signals in the lowest unit of the absolute signal, but abnormality detection is performed based on the number of incremental signals included in the upper unit of the absolute signal. Of course, this is a good thing.

Effects of the Invention The present invention uses the absolute signal and incremental signal generated by the pulse encoder itself in a pulse encoder that generates absolute signals and incremental signals to detect an abnormality in the absolute signal of the pulse encoder itself. This allows the abnormality to be detected accurately.

[Brief explanation of drawings]

FIG. 1 is an embodiment of the present invention, and FIG. 2 is an operation timing chart of the embodiment. Fl, F2...Flip-flop, G1...Exclusive OR, G2. G3...OR circuit, C...up/down counter, R...latch circuit. Patent applicant FANUC CORPORATION Figure 1 Figure 2 123 N-25N J-1

Claims (2)

[Claims] (1) In a pulse encoder that outputs absolute signals and incremental signals, and outputs 2n incremental signals during one absolute signal output while rotating in one direction, the incremental signals in one direction are added, and the incremental signals in the opposite direction are The signal is provided with a reversible counter consisting of n bits for subtraction, and this counter counts the incremental signal during one absolute signal output.By detecting that the counting result of the reversible counter is not zero, the absolute signal is An absolute signal abnormality detection method for absolute encoders that detects abnormalities. (2) The absolute signal abnormality detection method for an absolute encoder according to claim 1, wherein the period during which the reversible counter counts the incremental signals is a 1R low unit output period of the absolute signal.