JPS60187812A - Detecting system of loss of incremental signal of encoder - Google Patents

Abstract

PURPOSE:To facilitate the detection of a loss of an incremental signal, by checking an incremental signal immediately after switching, and by detecting incremental signals from the second onward. CONSTITUTION:A plus signal P from an incremental signal detecting circuit 1 resets FFF2 and sets FFF1. Therefore signals P of the second and subsequent thereto are obtained from a gate G9. As for a minus incremental signal -P, also signals -P of the second and subsequent thereto are obtained from a gate G10. When at least either one of the phases A and B of an output of a pulse encoder is lost, an incremental signal loss detecting circuit 4 delivers no signal.

Description

[Detailed Description of the Invention] Industrial Field of Application and Prior Art The present invention relates to a pulse 7T saw 7/l''' illusion I eight for detecting the rotational position of a motor, etc.
This invention relates to an incremental signal loss detection method for an encoder that detects the loss of pulses.

An incremental pulse encoder for detecting the rotational position of a motor outputs an incremental signal corresponding to the rotational direction and speed of the motor from A-phase and B-phase signals that are shifted by half a wavelength from each other.

That is, slits are provided equally on the circumference of a slit disk attached to the motor shaft, and as the motor rotates, the slits obtain signals of phase A and phase B that are shifted by half a wavelength. The signal is input to an incremental signal detection circuit 1 as shown in FIG. 1, and this circuit obtains an output pulse that matches the rotational direction of the motor.

The incremental signal detection circuit 1 shown in FIG. 1 is obtained by a slit disk, a photoelectric converter, etc., and has an IS A phase.

The B-phase signal is input, and the pulse A as shown in FIGS. 2 and 3 is generated via Schmitt circuits 2 and 3.

Get pulse B. And these pulse inverters I
The pulse is inverted to create 100 in the inverted pulse 'shown in FIGS. 2 and 3, and the distribution pulses A, B, human, and white are further differentiated using a differentiator circuit to create a differentiated pulse. As shown in FIG. Positive incremental signal P by OR gate G11
, a negative incremental signal -P is obtained by AND gates G5 to G8 and OR gate G12. That is, the motor rotates in the forward direction, and as shown in FIG.
When the B phase is shifted by half a wavelength and pulses A and B are generated, a positive incremental signal P is output as shown in FIG. 2 via AND gates G1 to G4 and OR gate G11. Also, the motor rotates in reverse, and as shown in Figure 3,
When pulses A and B of phase and B phase occur, AND gate G5
A negative incremental signal -P is output via ~G8 and OR gate G12. Note that the symbols A and B written below the AND gate in Fig. 1 and below the pulse output of the incremental signal terminals P and -P in Figs. 2 and 3
, A', B', 入, 100, 8', 0' have the following meanings.

A: Signal of pulse A B: Signal of pulse B A': Differential signal of pulse A B': Differential signal of pulse B input: Reverse signal of pulse A B: Reverse signal of pulse B 8': Differential signal of pulse input B': Differential signal of pulse B. For example, A'.white indicates the AND of signal A' and signal B.

As described above, when the motor rotates in the forward direction, the incremental signal detection circuit 1 of the pulse encoder outputs the positive incremental signal P, and when the motor rotates in the reverse direction, the negative incremental signal -P is output. However, if there is some kind of failure in the pulse encoder and either phase A or phase B is missing and no output occurs, or if the output is not output all the time? i1 match etc. occur. for example,
As shown in FIG. 4, when the B phase is missing and pulse B is not output, the incremental signal detection circuit 1 alternately outputs a positive incremental signal P and a negative incremental signal -P. Become. In other words, when the B phase is missing and the output is zero, B=O, B
' = O, B = 1.8 ' = 0, so only AND gate G1 and AND gate G7 in Fig. 1 output,
As shown in FIG. 4, positive and negative incremental signals P and -P are alternately output. Also, B
Even when a signal is output from the phase to the wealth and B=1, the AND gate G3. The only signal of G5 is output, and the positive and negative incremental signals P and -P are alternately output. Similarly, when the A phase is missing and the output becomes zero, positive and negative incremental signals are alternately output even when a signal is always output from the A phase.

Incidentally, if both the 6th phase and the B phase are missing and become zero, and both phases output signals, no incremental signal will be output.

However, conventionally, it has been difficult and difficult to detect defects in the A phase or B phase of a pulse encoder as described above. The purpose of this invention is to provide an incremental signal loss detection method that can detect.

Structure of the Invention The present invention provides that, at the time when the positive and negative incremental signals output from the incremental signal detection circuit of a pulse encoder switch, the first incremental signal output after switching is blocked, and other incremental signals are This is an incremental signal loss detection method for an encoder in which a signal is extracted and output, and loss of the incremental signal is detected from the extracted incremental signal and the terminal voltage of the motor to which the pulse encoder is attached.

Embodiment FIG. 5 shows an embodiment in which the present invention is implemented, in which 1 is a known incremental signal detection circuit, for example, a whistle 1Mζ壬SET 21t? Incremental signal detection circuits other than the circuit shown in Figure 1 may be used.For example, when the B phase is output and is "1", the rising and falling of the A phase may be used. Forward and reverse rotation pulses +P for <A' and B of AND gate G5 and input' and B signals of AND gate G3>.

-P may be used). 4 is an incremental signal loss detection circuit implementing the method of the present invention;
F2 is a flip-flop, G9. G10 is an AND gate, and G13 is an OR gate.

5 is an amplifier that amplifies the voltage Vo from the terminal voltage detection circuit of the motor to which the encoder is attached, 6 is an absolute value circuit, 7 is a comparator, R1 and R2 are resistors, and C is a capacitor.

Next, the operation of this embodiment will be explained with reference to the timing chart of FIG.

In addition, in FIG. 6, (a) is the output of the positive incremental signal 10P, and (b) is the output of the flip-flop F1.
set output, (C) is the output of AND gate G9, (d
) is the output of the negative incremental signal -P, (e
) is the output of the flip-flop F2, <f) is the output of the AND gate G10, and (g) is the OR gate G13.
, that is, the output of the incremental signal loss detection circuit.

If, at the time point (■) in FIG. 6, the positive incremental signal 10P is continuously outputted from the incremental signal detection circuit 1 as shown in FIG. 4, the positive incremental signal 10P resets the flip-flop F2 and The flip-flop F1 is set, and the signal is further input to the AND gate G9. Flip-flop F1. F2
, it is inverted at the falling edge of the input signal and there is a delay, so
As shown in FIG. 6(b), the set output is output later than the positive incremental signal 10P at the negative end.

Therefore, as shown in FIG. 6(C), the AND gate G
9 outputs positive incremental signals for the second and subsequent shots.

On the other hand, the positive incremental signal 10P increments to the negative incremental signal -P.

At the time point ◎ in FIG. 6 when the output of the mental signal detection circuit 1 changes, the first negative incremental signal -P resets the 7-lip flop F1 and sets the flip-flop F2. flip flop F
As mentioned above, the setting of 2 is delayed a little, so the AND gate GIO which inputs the output of the flip-flop F2 and the negative incremental signal -P outputs the second and subsequent negative incremental signals -P. becomes. As a result, as shown in FIG. 6(g), the incremental signal from OR gate G13 is positive;
Regardless of whether it is negative or negative, it will continue to be output. However, as shown in Figure 6 and after, when either the A phase or the B phase is defective and the incremental signals are output from positive and negative alternately, the positive incremental signal 10P causes the flip-flop F1 to fail.
is set, but because there is a delay, it is not output from AND gate G9, and therefore is not output from OR gate G13. Then, the output flip-flop F1 is reset and the flip-flop F2 is set. In this case as well, since there is a delay, no output signal is output from AND gate G10 and no output signal is output from OR gate G13. Similarly, the positive + of the incremental signal
If P and minus-P signals are output alternately, no output will be made from the OR gate. In addition, A phase, B phase
If both phases are defective, the positive and negative incremental signals 10P and -P are not output from the incremental signal detection circuit 1, and therefore no output is output from the OR gate G13 in this case as well.

As described above, when at least one phase of the pulse encoder is lost, no signal continues to be output from the incremental signal loss detection circuit 4.

On the other hand, if the motor to which the encoder is attached is rotating, the detected voltage Vo of the terminal voltage of the motor is amplified by the amplifier 5 and charges the capacitor C +I: f X 41<
:ITiM I-'i;' I ”/ 11 zo
Since the output of the output circuit 4 turns on the transistor of the inverter I and grounds it, the electric charge charged in the capacitor C is discharged.
No output is output from the absolute value circuit 6, and an H level output is output from the comparator 7. However, if the signal is not continuously output from the incremental signal loss detection circuit 4,
Codenser C remains charged, and comparator 7 outputs an L-level encoder failure signal via absolute value circuit 6. In addition, if the pulse encoder is normal and the motor to which the pulse encoder is attached rotates forward and reverse, and the positive incremental signal P is output for one pulse and the negative incremental signal -P is output for one pulse,
Even in such a case, the incremental signal loss detection circuit 4 does not send out a signal as described above.

However, since the detection voltage of the motor terminal voltage input to the amplifier 5 is input alternately as positive and negative, the capacitor C is not charged, and as a result, the comparator 7 does not send out an L-level encoder failure signal. .

In the above embodiment, the flip-flops F1 and F2 are used, but instead of the flip-flops, a delay element that continues to output an output signal with a delay when there is an input signal may be used.

Effects of the Invention As described above, according to the present invention, defects in one of the A and B phases and defects in both phases of a pulse encoder, which have been difficult to detect in the past, can be detected using a simple circuit.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of an incremental signal detection circuit of a conventional pulse encoder, and FIG. 2 is a timing diagram in which the incremental signal detection circuit outputs a positive incremental signal when the motor rotates in the positive direction. Figure 3 is a timing diagram of the output of a negative incremental signal when the same motor rotates in the opposite direction. Figure 4 is a timing diagram of the incremental signal output from the incremental signal detection circuit when the B phase is lost. Timing diagram: FIG. 5 is an embodiment of the present invention; FIG. 6 is a timing diagram of the same embodiment. 1... Incremental signal detection circuit, 2.3...
Schmitt circuit, 4... Incremental signal loss detection circuit, 5... Amplifier, 6... Absolute value circuit, 7...
・Comparator, ■... Inverter, D... Differential circuit, F
l, F2...Flip-flop, 01-G10...AND gate, 011-G13...OR gate. Patent applicant FANUC Co., Ltd.

Claims (1)

[Claims] (1) At the point when the positive and negative incremental signals output from the pulse encoder's incremental signal detection circuit switch between each other, the first incremental signal output after switching is blocked, and the other incremental signals are extracted and output. An incremental signal loss detection method for an encoder is configured to detect the loss of the incremental signal from the extracted incremental signal and the terminal voltage of the motor to which the pulse encoder is attached.