JPS60187029A - Heat treatment furnace - Google Patents

Abstract

PURPOSE:To avoid the plastic deformation of a semiconductor wafer by previously forming a large number of gas jets near a wafer take-in-and-out section for a core pipe when a boat on which a large number of the semiconductor wafers are erected at intervals is housed in the furnace core tube and the wafers are oxidized or diffused in a desired manner. CONSTITUTION:A furnace core tube 5 is surrounded by a soaking pipe 1, a heater 2 is wound on the outer circumference of the soaking pipe 1, and a boat 7 with an extruded bar 8 is housed in the furnace core tube 5. A large number of semiconductor wafers 61-63, etc. are erected on the boat 7, and a large number of gas jets 11 are bored previously near a taking-in-and-out section for the wafers 61-63 while being positioned at the pipe wall of the furnace core tube 5. A gas 3 is blown against the wafers 61-63 in the vertical direction from the jets 11, the ambient temperatures of the wafers are lowered up to 78-97% of a heat treatment temperature for the wafers, and temperature difference among the central sections and peripheral sections of the wafers is reduced. Accordingly, the plastic deformation of the wafers is prevented, yield is improved while the tolerance of the speed of carrying of the wafers is spread, and the lowering of a through-put is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a heat treatment furnace used particularly for oxidizing and diffusing semiconductor substrates.

[Technical background of the invention and its problems]

Conventionally, during the semiconductor manufacturing process, semiconductor substrates (p-eva)
The one shown in FIG. 1 is known as a heat treatment furnace used for oxidation and diffusion of.

1 in the figure is a heat equalizing tube with a spiral heater 2 completely wrapped around its outer periphery. Inside the soaking tube 1, a furnace core tube 5 having an inlet 4 for the surrounding air gas 3 at one end is provided. A port 7 into which a plurality of wafers 6 are to be implanted is provided at the bottom of the furnace core 5, and a push rod 8 for inserting and removing the port 7 is locked at the end of the port 7. There is.

The temperature distribution of the heat treatment furnace having the structure described above becomes a curve shown in FIG. In the same figure, the temperature distribution curves are in areas A, B, and C.
Of these, area B is a soaking area where the wafer 6 is oxidized and diffused. In other words, during oxidation and diffusion, the UniNo 6 is heated from the room temperature area through area A to area B. However, according to the heat treatment described above, when the Eva 6 is transported from a room temperature region to region A via region B, or vice versa, Since there is a steep temperature gradient in region A, a temperature difference occurs within the wafer 6, and a large stress is generated. When this stress reaches a certain value or more, the wafer 6 is plastically deformed and the yield decreases. For this reason, the transport speed of the wafers 6 is normally selected within a certain allowable range determined by the interval at which the wafers 6 are lined up on the boat 7 and the diameter of the wafers. Here, an example of the relationship between the transport speed of the wafers 6 and the interval between the wafers 6 is as shown in FIG. However, as the wafer 6, a silicon substrate with a diameter of 100 μm and a thickness of 525 μm was used.
The temperature of region B is 1000°C.

In the figure, the curve (a) is the boundary line between the presence and absence of plastic deformation, and plastic deformation occurs in Ueno 6 at the upper part of the curve (a), and no plastic deformation occurs at the lower part.

However, recently the diameter of wafers has become larger,
Correspondingly, the curve (a) shown in Figure 3 goes downwards, and to give an example of this, the permissible transport speed becomes very small, leading to a decrease in throughput.
In the case of 25 dragons, the allowable conveyance speed is 1 diameter
It is reduced to about 1/2 compared to that of 00 Dragon. Also,
When the diameter of the wafer is changed from 100111 to 125, the area ratio is (125/100)''=:=1.56, and the advantage of increasing the diameter is lost in the oxidation and diffusion transport process.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned problems, and it prevents plastic deformation of wafers to prevent a decrease in yield, and widens the allowable range of wafer transport speed when wafer diameters increase, thereby increasing throughput. [Summary of the Invention] The present invention aims to provide a heat treatment furnace that can prevent the temperature from decreasing at around 78% of the heat treatment temperature.
When the temperature difference is ~98%, a method of reducing the temperature difference between the center and peripheral parts of the substrate, specifically by blowing gas parallel to the main surface of the semiconductor substrate, reduces yield and throughput due to plastic deformation. It is an attempt to prevent this.

A detailed description will be given below with reference to FIGS. 4 and 5.

In Figure 4, the vertical axis shows the temperature difference (ΔT) between the periphery (for example, 5 degrees) and the center of the substrate, which occurs when the semiconductor substrate is put into the core tube of the heat treatment furnace, and the horizontal axis shows the temperature difference (ΔT) at that time. This is a plot of the temperature around the substrate.However, the heat treatment temperature 1
000° C., substrate diameter 100 gg, substrate transport speed IFcIIL/min, and substrate spacing 6 degrees. It is clear from the figure that the temperature difference ΔT becomes maximum when the temperature around the substrate is around 750°C. Note that this was not limited to the case where the substrate diameter was 100mm, but was the same in cases of other diameters. Here, if the presence or absence of plastic deformation mentioned above was determined simply by the magnitude of stress, the figure shows that plastic deformation is most likely to occur at around 750°C, but in reality, this is not the case because the ease of plastic deformation differs depending on the temperature. By the way, when a silicon substrate is taken as an example of a semiconductor substrate, the upper yield stress is a measure of the ease of plastic deformation, and the higher the temperature, the smaller the upper yield stress, the more likely the substrate will be plastically deformed. Therefore, the temperature difference ΔT in Figure 3 divided by the upper yield stress at each temperature is a parameter that represents the ease of plastic deformation. In Figure 5, the vertical axis shows the temperature difference ΔT divided by the upper yield stress. The temperature around the substrate is plotted on the horizontal axis. Here, the heat treatment temperature is 1000°C. According to Figure 5, △T/upper yield stress has a peak between 780 and 970°C around the substrate, and plastic deformation is most likely to occur in this temperature range. In addition, the present inventors have found that the heat treatment temperature is 1
As a result of examining not only the case of 000°C but also the persimmon case, it was confirmed that the peak shown in FIG. 5 occurs when the temperature around the substrate is 78 to 97% of the set heat treatment temperature. For this reason, the inventors of the present invention have provided a means for reducing the temperature difference between the center and the periphery of the substrate when the temperature around the substrate is 78% to 97% of the heat treatment temperature, thereby reducing yield and throughput. tried to prevent it. In addition, when it is less than 78% and when it exceeds 97%, the stress applied to the substrate can be almost ignored, so there is no need to provide such a means. This will be explained with reference to FIG.

The same members as in FIG. 1 are given the same reference numerals and their explanations are omitted.
C@Output gas 3..., which is a plurality of gas ejection ports, is provided near the wafer central part and the peripheral part (e.g., from the outer periphery) as a means of reducing the temperature difference between the wafer center and the peripheral part (for example, from the outer periphery). ,
When the temperature around the wafer is 78 to 97% of the heat treatment temperature from these gas jet ports, O is blown parallel to the main surface of the wafer 6. 6...
The temperature around the wafer was around 78°C, which was the heat treatment temperature.
~98% - Since the gaseous outlet 11 for blowing the heavy gas 3 is provided, the surface of the wafer 6 can be heat-treated more uniformly than in the past. Therefore, the stress when moving the wafers 6 in and out of the furnace core I#5 during oxidation and diffusion can be reduced, thereby widening the allowable range of the transport speed of the wafers 6 and improving throughput.

In fact, the diameter is IQQl! IK, the presence or absence of plastic deformation of wafer 6 with a thickness of 525 ttm was investigated, 8F! 7
The results shown in the figure were obtained. In the figure, the vertical axis shows the conveyance speed of the wafers 6, the horizontal axis shows the interval between the wafers 6, and the curves (a) and (b) show the wafers 6 according to the present invention and the conventional apparatus, respectively. ...is the boundary line between the presence and absence of plastic deformation. Plastic deformation occurs in the wafer 6 above this boundary line, and plastic deformation does not occur in the lower part /Ii. From the same figure, it is clear that in the case of curve (a), the allowable upper limit value of the conveyance speed is 1°2 to 1.5 times larger than that in the case of curve (b). ) / When the relationship between the upper yield stress and the wafer peripheral temperature was investigated, the results shown in FIG. 8 were obtained.
(→ are the curves showing the conventional case, where the wafer spacing is 4 gm and the conveyance speed is 35 f/min.) According to the same figure, △T/upper yield stress can be made significantly smaller than in the case of Fig. 5. , it can be confirmed that large peaks can be eliminated.Therefore, it is clear that plastic deformation is less likely to occur compared to the case shown in Fig. 5.From the above, it is clear that the heat treatment furnace according to the present invention has a higher surface area than the conventional one. [Effects of the Invention] As detailed above, the present invention prevents plastic deformation of wafers, prevents a decrease in yield, and widens the allowable range of wafer transport speed. C that can provide a highly reliable heat treatment furnace that can prevent a decrease in throughput.

[Brief explanation of the drawings] Figure 1 is a cross-sectional view of a conventional heat treatment furnace, Figure 2 is a temperature distribution diagram of the heat treatment furnace shown in Figure 1, and figure 3? -i Figure 1 is a characteristic diagram showing the relationship between the wafer transfer speed in the heat treatment furnace and the wafer spacing, Figure 4 is a characteristic diagram showing the relationship between the temperature difference and the wafer surrounding temperature, and Figure 5 is the same as in Figure 1. Characteristic diagram showing the relationship between ΔT/upper yield stress due to heat treatment furnace and wafer ambient temperature, No. 6
The figure is a sectional view of a heat treatment furnace according to an embodiment of the present invention, FIG. 7 is a characteristic diagram showing the relationship between the wafer speed and the wafer spacing of wafer 1 in the heat treatment furnace of FIG. 6, and FIG. 8 is a characteristic diagram of the heat treatment furnace of the same heat treatment furnace. C is a characteristic diagram showing the relationship between △T/upper yield stress and wafer surrounding temperature. 1. Soaking tube, 2. Heater, 3. Atmosphere gas, 4. ...Furnace core tube, 6...Semiconductor substrate (wafer), 7...Boat, 8...Push rod, 11
...Gas outlet. Applicant's attorney Takehiko E Takehiko No. 1) l No. 2f"" I Stand No. 3L'3 Wafer spacing No. 41゛1 Wafer No. 50 from Urijima Fig. 6 00000 o' Oo 1 3N NONO Figure 7 158

Claims (2)

[Claims] (1) A heat soaking tube with a heater wrapped around its outer periphery, and a furnace core provided within the heat soaking tube and into which a semiconductor substrate embedded in a board is taken in and taken out so that the main surface of the substrate is perpendicular to the longitudinal direction of the heat soaking tube. The temperature of the tube and the surrounding area of the substrate is 78 to 9 of the heat treatment temperature.
A heat treatment furnace C characterized in that it is equipped with means for reducing the temperature difference between the center part and the peripheral part of the substrate when the temperature is 7%. (2) The heat treatment furnace according to claim 1, wherein the means for reducing the temperature difference between the central portion and the peripheral portion of the substrate is to blow gas parallel to the main surface of the semiconductor substrate.