JPS60183822A - Maximum likelihood correction circuit - Google Patents

Abstract

PURPOSE:To attain the error correction caused by the maximum likelihood estimation having a large error correcting effect by means of a decoder by providing plural storage areas corresponding to the number of bursts. CONSTITUTION:Error correcting coders 71a, 71b,...71i... encode transmission data 40 within a assigned time respectively and output data 43, 43' are transmitted via modulators 72a, 72b,...72i as a burst signal without post-amble in order to improve the line efficiency. An error correction decoder 74 in a demodulator 73 provided to the reception side processes altogether the transmission data included in a multiplex burst, and the result of decoding is outputted as 76a, 76b,... 76i.... The error correction decoder 74 is provided with a maximum likelihood estimation operating circuit 741 and plural storage areas 742a, 742b,...742i... for the maximum likelihood estimation to each burst signal. Through the constitution above, since the content of the preceding assigned burst signal period is stored for each burst signal in the storage areas 742a, 742b,...742i..., the storage content for the maximum likelihood estimation is not destroyed by other burst signal and continuous decoding is attained properly.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a time-division multiplex 4Xη-nod communication system used, for example, in the 5-to-5 communications network, and to solve problems based on maximum likelihood estimation. This is related to a maximum likelihood 1, 1 correction circuit that is capable of performing good luck.

[Technical background of the invention and its problems]

In satellite communications where wireless power is limited, error correcting codes are used to eliminate ;'lX! Although the aim is to reduce the ilQ power ↑(11,
, <・1 (. As shown in FIG. On the other hand, on the receiving side, the received signal is decoded by the decoder 6 and the error correction 111 encoder 7 to obtain received data d.

In such an i;1 star communication system, the ground and i.1'
Time-division multiple access is often used to effectively use the power transmitted on the planet. Each earth transmitting station 2a in FIG.

From 2b,...-t2it..., Fig. 3 fAl,
(Ill,..., (I),... Burst signals 3a, 3a', 3b, 3bζ..., 31...
.

FIG. 4 shows a 4W configuration of an example of a convolutional error correction encoder for performing maximum likelihood decoding.

In the figure, 40 is transmission data, 41 is a shift register,
Reference numeral 42 indicates an exclusive OR operation circuit, and 43 and 43' indicate output data. Left W in the figure: Transmission data 40 is supplied to the shift register 41 from the input terminal M
The signal is sent to the cross modulator I1, and its output is further transmitted.

On the other hand, in the earth receiving station 2r, if one decoder attempts to perform the error correction decoding, different earth transmitting stations 2a, 2b, . . . , 21 . It is necessary for the decoder to operate in common with respect to burst signals from ..., and for this reason, redundant bits have been conventionally added so that the operation does not depend on the data sent out by each earth transmitting station.

FIG. 5 shows an example of the structure of a burst signal.
indicates a preamble for burst synchronization, 52 indicates data, and 53 indicates a postamble for the above-mentioned error correction.

However, the JE decoder that uses maximum likelihood estimation, which has a large error correction effect, takes in a large amount of received data (1 office + 17) and decodes the most probable data from among them. It is characterized by a very large internal delay. Therefore, in order to send out data from a different previous transmitting station, it is necessary to make the data interval between the lXi 49 bursts sufficiently long and to add a long postamble, thus reducing the number of times and reducing the transmission efficiency. I couldn't do it.

As a countermeasure to reduce data between adjacent bursts, it has been common practice to switch between the father and father for burst 1 and operate. i 61X+, 60a, 60b.

...601... is transmission data from each transmitting station, 61
a, 61b.

611... are error correction encoders, 62a, 62b,
..., 621... is a modulator, 63 is a demodulator, 65a
, 65b, 65c, 65d, --... is out G5c, 6
5d, . . . indicate outputs.

However, the error correction m encoder based on the 71'):I standard has an extremely large hardware scale compared to other 1; This invention was made in order to eliminate the above drawback by 1, and it uses maximum likelihood estimation which has a large error correction effect. It has a large error correction function and has a small hardware scale. 'A
The present invention attempts to provide a maximum likelihood error correction circuit that can reduce the la 4i power.

[From 1jlJ O,) Ii,! j Essential] This output 131 accepts a signal in which a multiple-connected reverse burst signal is time-division multiplexed, and also uses an antinominal number for maximum likelihood estimation corresponding to each of these types of time-division multiplexed bursts. The present invention is characterized in that these storage areas are switched and used for each burst, and the operation is performed so that the area is continuously traced for each burst of interest.

[Result of invention]

According to this idea, by changing memory areas 1 and 4 on the side of the number of sheets corresponding to λq of the burst, ii:,! RJ correction using 1″17-likelihood estimation, which has a large correction effect, is
This is possible with just one marker. Therefore, it would be a good idea to suppress the expansion of the hardware scale and reduce noise reduction.

[Embodiment of the Invention] An embodiment of the invention will be described below with reference to Figures +/i.

Figure 7 shows the general structure of the error correction communication system including this actual 1'cli wl.

1, in zz, 70 a y 70 b e'...70
``'' 61 Ja 4cs data, 71a.

nb, -71i-... is i-guri correction code)) Jyo, 72a
, 721), =-72i... are modulators, and these error correction encoders 71a.

71b, -71+ +++: 13 and modulator 72
a, 72b, -72i= are respectively built in the earth transmitting stations 2a, 2b, . . . , 21, . Error correction encoders 71a, 71b,...71i
. . . specifically have the structure shown in FIG.
and modulate the output data 43.43' r::÷
72a, 72b, . . . 721', 5 burst signals without postamble are transmitted in order to improve line efficiency.

At this time 1. :':x correction encoder 71a, 71b,
...7Ii... are each ゛I'1. It operates only during the allocated burst time. Outside the allocated time, Ti) + operation is stopped and the sending data is sent by 1 until the next allocated burst time.
1-ν is kept within the e/d region.

In this way, the hourly broadcast data number 1 from the earth transmitting stations 2a, 2b, . . . , 21 .

In Figure 7, 73 is a receiver 1 installed in 11j, A, and 74 is a maximum likelihood error correction encoder of this invention that embodies the E circuit. , this decoder 74 collectively processes the transmission data included in the multi-1j1 burst, i8p, and the decoding results are 76a, 76
b, . . . 76j . . . are output.

Error correction 1) No. 1, (;÷74 is maximum likelihood estimation calculation circuit 7
41 and multiple storage areas 742a, 742b, . . . 7421 for maximum likelihood estimation for each burst signal.
It is equipped with These storage areas 742a, 742
b,...7421... are synchronization side signals obtained from the output of the demodulator 73 via the burst identification circuit 75.
1 signal is selected based on the maximum likelihood 11'['determined performance 4'
It is connected to the front circuit 741 as appropriate.

By configuring in this way, the area 742
a, 742b, ----742i- has Harstoy No. 3 f
(before ii); Since the content of the burst signal period is hidden, the maximum likelihood of 1.1 due to other burst signals is 1. (＼Contents will be destroyed, bye
) Be able to perform D-like No. 19 accurately.

FIG. 8 shows an embodiment of 114 cases in which the maximum likelihood error correction +E circuit of the present invention is made into a Viterbi signal based on the Viterbi algorithm as ;/(,゛・!).

Regarding the Viterbi decoding method, the basic information is summarized in the book by Viterbi and Homera [Principles of Digital Communication and Coding (Comaf Gro-Hill Publishing Co., Ltd., 1979); Jifl
omitted.

This Viterbi decoder has a branch metric circuit L'a81
, the path metric circuit 82 and the surviving path circuit 83, and the path metric circuit 83 also includes the surviving path storage circuit 831 and the i+
I'l°·1 is generated by the % likelihood decoding circuit 832. Note that a circuit having the same storage area as the path metric notation unique circuit 823 and the like is used. In the figure, 808 is the input QYI+, 80b is the input of the synchronization control signal, and the control fi! It has 1 go, 111 roe, and 8OC has 4 sardine roe.

In the circuit shown in Figure 8, jD is input from input 1 Mizuko 80a.
When the f+"I multi-11X data is input, a branch metric is generated in the branch metric circuit h'381, and this is input to the pasta) IJ Cook path 82.

In the path metric circuit 82, the path metric update circuit 821 via the IJ hook and the normalization circuit 822 (the pasta stored in the path metric storage circuit 823)
(Pre-1112 branch) Synthesis of IJ hook.

A comparison 1 selection is made and a new path metric is stored in the path metric i storage circuit 823. Pasta) I
The output of the J-sock new circuit 821 is the maximum likelihood ([(+constant)I''
3824, and thereby the normalization group j・f'
A1'+ is output to the normalization circuit 822.

Furthermore, the path metric updating circuit 821 uses the control signal used to update the path metric and the j11 error estimation circuit 824 calculates jI from the path metric of only the state W Frk.
>The control signal used when estimating the light value is input to the survival path circuit 83, and the survival bus storage circuit 831 and the maximum likelihood decoding circuit 832 are respectively connected, and the decoding result is output ψ;1. ' It is output from the fourth child 80c.

In this series of operations, the path metric notation 1)-circuit 823 and the surviving bus storage circuit 831 perform t'lt
As described above, each has a storage area corresponding to the number of bursts, so different storage areas are selected for different bursts based on the synchronization control signal input from the control terminal 80b. +:::fI, is stored. Therefore, for the burst of interest from the same transmitting station, use other bursts! Decoding can be carried out continuously without disturbing the embryo.

As described above, the maximum likelihood error correction circuit of the present invention stores a plurality of storage areas corresponding to the parse glue Sl (rHl 1,:
'f These 5 cI depending on the burst! '+' (
! By selecting ``l'', one decoder can perform the error correction using the maximum likelihood: 1lli specification with a large error correction IE effect. Therefore, the expansion of the If it can be suppressed, power consumption can be reduced1
There is a length of 1 kilo.

It should be noted that this invention is not limited to the above i;C embodiments, and can be implemented with multiple modifications within the scope without changing the gist.

[Brief explanation of the drawing]

``M'j Figure 1 is an explanatory diagram showing the multiple access communication type 1 river by Wi-77j, Figure 2 is the transmission Gi used for this communication form.
A schematic diagram of the 4iI side and receiver side, J31-1 is a waveform diagram of a burst signal to explain time division multiple access, and Figure 4 is a convolution diagram for performing maximum likelihood 11. Error correction code TE) A configuration diagram of an example of hemorrhoids, FIG. 5 is an explanatory diagram of an example of the waveform of a burst signal used in the above communication form, and FIG.
The figure uses multiple pieces of error correction 1 summer edition,! ii of the conventional communication method that consists of f9! FIG. 7 is a schematic diagram of an error correction communication system including one embodiment of the present invention. O! J% drunks! :gl is this episode 1. II
J i Bikubi i4) based on the Viterbi algorithm:
It is a circuit diagram of a royalty fee made as ¥1'. 1: Satellite 2a, 2b...21...Earth transmitting station 2:
Ground 1jz receiving station 3a, 3b...31...: Burst 1; J+j3゜4:1 Rinba I' JLX encoder 7:1 instead of iJ correct signal signal 40: Transmission data 41: Shift register 42
:Exclusion・111L discussion II 7ii Ren μ times I 43.
43. ': Output data 51: Brian 52: Data 53: Post ampule 60a, 60b-60i ・: Output data 61a, 6
1b...6ti...: Error correction encoder 62a, 6
2b-621: Modulator 63: Demodulator 64α, 64β: Error correction decoder 65a, 65)), 65c, 65d --: Output cuff 0ae70b, -704-: Transmission 4 to 7' 171a,
71b,...711...: error correction encoder 7za,
7zb, -724-: Modulator 73: Demodulator 74: Error correction decoder 741: I error estimation calculation circuit uza, u2b, -r42r ・: Note 1. C area 75
: burst identification circuit 76a, 76b, p6i-, : output 80a: input terminal sob: control terminal 80C: output) 11M child 81 nib branch metric circuit 82: path metric circuit 821: bus metric update circuit 822: normalization circuit 823 :Path metric storage circuit 824:Maximum likelihood estimation circuit 83:Raw @ remaining path circuit 831:Survival path record・i,・elephant circuit 832:Differential decoding circuit

Claims (2)

[Claims] (1) A plurality of multiple-connected burst signals accepts signals converted into time-division multiple rF bursts, has a decoding function for 11" 1-correction based on glory estimation, and supports each time-division multiple rF burst. i'! Several storage areas for likelihood estimation are provided, and these storage areas are removed for each burst of interest based on a control signal.゛1in error 1.% error correction circuit. (2) It is configured as a Viterbi decoder, and each of the IJ Cook storage circuit and the surviving path storage circuit has several storage areas (ri#) for maximum likelihood estimation, and each of these storage areas is selected.・1; iΣ enclosure, 5(1
The maximum likelihood error correction circuit described in Section 1.