JPS60182751A - Formation of wiring pattern of circuit board - Google Patents
Formation of wiring pattern of circuit boardInfo
- Publication number
- JPS60182751A JPS60182751A JP59037930A JP3793084A JPS60182751A JP S60182751 A JPS60182751 A JP S60182751A JP 59037930 A JP59037930 A JP 59037930A JP 3793084 A JP3793084 A JP 3793084A JP S60182751 A JPS60182751 A JP S60182751A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- circuit board
- patterns
- pattern
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title abstract 2
- 238000000034 method Methods 0.000 claims abstract description 20
- 230000007261 regionalization Effects 0.000 claims description 2
- 238000005520 cutting process Methods 0.000 abstract description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 2
- 238000010276 construction Methods 0.000 abstract 1
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 4
- 238000005304 joining Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000007787 solid Substances 0.000 description 4
- 238000005476 soldering Methods 0.000 description 3
- 235000007173 Abies balsamea Nutrition 0.000 description 2
- 241000218685 Tsuga Species 0.000 description 2
- 229910002092 carbon dioxide Inorganic materials 0.000 description 2
- 239000001569 carbon dioxide Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
Landscapes
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は回路基板の配線パターン形成方法に係り、特に
回路基板上に予め平板状(ヘク状)の電極バクーンを形
成した後に端子を持つ実装部品の該端子と該平板状電極
バクーンを接続後必要な配線パターン間を切り離すよう
にしてなる回路基板の配線パターン形成方法に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for forming a wiring pattern on a circuit board, and particularly to a method for forming a wiring pattern on a circuit board. The present invention relates to a method of forming a wiring pattern on a circuit board, which comprises connecting the terminal and the flat electrode backing and then separating the required wiring pattern.
従来9回路基板2例えばプリント基板上に抵抗。 Conventional 9 Circuit board 2 For example, a resistor on a printed circuit board.
コンデンザ或いは集積回路等のチップを実装する場合に
は予めプリント基板上に所定の配線パターンを形成し、
上記実装部品端子をパターンη111子孔にインサート
して半田例を行うか、或いは築積旧路用のチップをポン
チング或いは圧着接続するようにした電極パターンの接
続方法が知られている。When mounting chips such as capacitors or integrated circuits, a predetermined wiring pattern is formed on the printed circuit board in advance,
A method of connecting electrode patterns is known, in which the above-mentioned mounting component terminals are inserted into the holes of the pattern η111 and soldering is performed, or chips for built-up circuits are connected by punching or crimping.
このような接続方法によるときは実装部品の端子数が非
常に多く、その端子間のピンチが極めて小さい場合に回
路基板上に形成した電極パターンと」−記実装部品の電
極パターンの一対一の対応にわずかなずれを生じ接合部
での発熱や接合不良を生ずるら1と害があった。When using this type of connection method, the number of terminals on the mounted component is very large, and the pinch between the terminals is extremely small, so there is a one-to-one correspondence between the electrode pattern formed on the circuit board and the electrode pattern of the mounted component. A slight misalignment may occur, causing heat generation and poor bonding at the joint, which is harmful.
このような弊害を除去するために本発明者は先に実装部
品の複数端子と電極パターンを接合する方法として下記
の接続方法を提案した。In order to eliminate such disadvantages, the present inventor previously proposed the following connection method as a method for joining multiple terminals of a mounted component and an electrode pattern.
第1図は従来技術の電極パターンと実装部品の端子との
接合方法を示す平面図であり、第1図に於いて、■は回
路基板で該基板上には集積回路用のチップ2が配設され
、該回路基板には該チ・ノブ2用の出力電極3がパター
ニングされ、該出力電極3は例えば表示板4の電極5と
接合するように一対一で対応している。この状態で該出
力電極3と表示板4の電極5間に点線図示の如く薄い金
属板6を互いにまたがるように密着させ半田付すし。FIG. 1 is a plan view showing a method of joining an electrode pattern and a terminal of a mounted component according to the prior art. In FIG. Output electrodes 3 for the chi-knob 2 are patterned on the circuit board, and the output electrodes 3 are connected to the electrodes 5 of the display panel 4 in one-to-one correspondence, for example. In this state, a thin metal plate 6 is brought into close contact between the output electrode 3 and the electrode 5 of the display panel 4, as shown by dotted lines, so as to straddle each other and soldered.
炭酸ガスレーザまたはYへGレーザ等で」二記金屈板の
長手方向と直交する方向に切断フして互いに並設した電
極間を不導通状態とするようにした接続方法を提案しノ
こ。We proposed a connection method in which a carbon dioxide gas laser or a Y to G laser or the like is used to cut the metal plate in a direction perpendicular to the longitudinal direction to bring the electrodes disposed in parallel to each other into a non-conducting state.
この接続方法によれば従来技術で述べたような接合時に
複数の実装部品の端子と被接続パターンである電極パタ
ーン間でずれを発生しない接合方法が提案出来るが金属
板6を実装部品の端子3と被接続端子5間に密着接合す
る工程が増加するという問題があった。According to this connection method, it is possible to propose a joining method that does not cause misalignment between the terminals of a plurality of mounted components and the electrode patterns that are connected patterns during bonding as described in the prior art. There is a problem in that the number of steps for closely bonding the terminal 5 and the terminal 5 to be connected increases.
〔発明の目的〕
本発明は上記欠点に鑑み、実装部品の端子と被接続端子
間の密着接合が容易で高密度、高信頼度で接合出来、且
つ微小なピンチの配線パターンをユーザの要求に応じ任
意の形に、迅速に形成出来る回路基板の配線パターン形
成方法を提供することを目r内とする。[Object of the Invention] In view of the above-mentioned drawbacks, the present invention has been developed to facilitate close bonding between the terminals of mounted components and connected terminals, to achieve high-density, high-reliability bonding, and to meet the user's requirements for minutely pinched wiring patterns. It is an object of the present invention to provide a method for forming wiring patterns on circuit boards that can be quickly formed into any desired shape.
本発明の上記目的は回路基板上に複数の配線パターンを
形成し、該配線パターンを電極パターンとして用いる際
に該電極パターンを予め平板状電極パターンに形成し、
該平板状電極に1本或いは複数本の端子を有する実装部
品を接続した後に上記平板状電極パターンを切断して必
要な配線間を不導通状態とすることを特徴とする回路基
板の配線パターン形成方法を提供することで達成される
。The above-mentioned object of the present invention is to form a plurality of wiring patterns on a circuit board, and when using the wiring patterns as electrode patterns, to form the electrode patterns into flat electrode patterns in advance,
Wiring pattern formation for a circuit board, characterized in that after connecting a mounting component having one or more terminals to the flat electrode, the flat electrode pattern is cut to create a non-conducting state between necessary wirings. This is achieved by providing a method.
以下本発明の一実施例を図面について詳記する。 An embodiment of the present invention will be described in detail below with reference to the drawings.
第2図(al、 (b)、 (clは本発明の回路基板
の配線パターン形成工程の原理を示す回路基板の平面図
である。第2図(a)は回路基板1としてプリント基板
に実装部品2を配設すると共にパターン3を形成し。Figure 2 (al, (b), (cl) is a plan view of a circuit board showing the principle of the wiring pattern forming process of the circuit board of the present invention. Figure 2 (a) is a circuit board 1 mounted on a printed circuit board. Part 2 is arranged and pattern 3 is formed.
フレキシブル多芯ケーブル9の複数電極10(通常0.
2〜0.6i+nピツチ)と上記回路基板のパターン3
とを接続するために該回路基板の接合部にヘタ状に端末
電極8を形成する。該端末電極はパターン3と同様の銅
箔状の導電性部材等で形成されている。次の工程は第2
図(blに示す様にフレキシブル多芯ケーブル9の電極
10の電極先端10aを回路基板1の端末電極8上に載
置して例えば半田付を行なう。Multiple electrodes 10 of flexible multicore cable 9 (usually 0.
2~0.6i+n pitch) and pattern 3 of the above circuit board
A terminal electrode 8 is formed in the shape of a hemlock at the joint portion of the circuit board in order to connect the circuit board. The terminal electrode is formed of a copper foil-like conductive member similar to pattern 3. The next step is the second
As shown in FIG. 1, the electrode tip 10a of the electrode 10 of the flexible multicore cable 9 is placed on the terminal electrode 8 of the circuit board 1, and soldering is performed, for example.
次の工程は第2図(blに示す様にフレキシブル多芯ケ
ーブル9の電位10の電極先端10aを回路基板1の0
111未電極8」二に接地して例えば半田(=Jを行う
。The next step is to connect the electrode tip 10a of the flexible multi-core cable 9 with a potential of 10 to 0 of the circuit board 1 as shown in FIG.
111 non-electrode 8''2 is grounded and soldering (=J) is performed, for example.
次工程は第2図(C1に示す様に回路基板のパターン3
の先’)tit 3 aとフレキシブル多芯ケーブル9
の先端10aとを結ぶ端末電極部分12を除いてYへG
レーザを照射してM’i:l末電極8を切り離し11を
行なうことで回路基板1のパターン3とフし・キシプル
多芯ケーブル9の電極は接合12され、他のパターンと
は切り離されて非導通状態とすることが出来る。上記実
施例に用いる端末電極切り離し用レーザどしてはYA、
Gレーザの外に炭酸ガスレーザや電子ビーム等を用いる
ことが出来る。The next step is pattern 3 of the circuit board as shown in Figure 2 (C1).
') tit 3 a and flexible multi-core cable 9
G to Y except for the terminal electrode part 12 connecting with the tip 10a of
By irradiating the laser and cutting off the M'i:l end electrode 8 and performing step 11, the pattern 3 of the circuit board 1 and the electrode of the cross-pull multicore cable 9 are joined 12 and separated from other patterns. It can be in a non-conductive state. The laser for separating the terminal electrode used in the above example is YA,
In addition to the G laser, a carbon dioxide laser, an electron beam, etc. can be used.
第3図はその一実施例を示すものであり、同図に於いて
13はXYステージ、14.Y、14Xば該XYステー
ジをY軸及びX軸方向に移動させるためのモータで回路
基板lとフレキシブル多芯う一−プルはXYステージ上
に固定され、上記したレーザ或いは電子ビーム等のエネ
ルギ線照射源15からのエネルギ線で端末電極8を焼き
切る。XYステージ13を移動させるピッチや移動距離
はユーザの設計条(/1に応じ予めコンビ、i、−夕1
6に記1、Qさせて置くことで極めて高速に切断処理を
行うことが可能である。FIG. 3 shows an example of this, in which 13 is an XY stage, 14. Y, 14X is a motor for moving the XY stage in the Y-axis and The terminal electrode 8 is burned out by the energy beam from the irradiation source 15. The pitch and moving distance for moving the XY stage 13 are set in advance according to the user's design criteria (/1).
By setting 1 and Q described in 6, it is possible to perform the cutting process at extremely high speed.
第4図(Ill (bl (Clは本発明の更に他の実
施例を示すものであり、ヒームリーF型チップやフィル
ムキャリヤ等に実装された集積回路用チップをセラミッ
ク等の回路基板に装着する場合の製作工程を示す平面図
である。FIG. 4 (Ill (bl (Cl) indicates still another embodiment of the present invention, in which an integrated circuit chip mounted on a Heemley F-type chip or a film carrier is mounted on a circuit board made of ceramic or the like. FIG. 3 is a plan view showing the manufacturing process.
第4図(Fl)で17はセラミック回路基板で該基板上
に実装する集積回路チ/プを適当に接続する回路パター
ン18を形成すると共に1ノー積回路チンプのリー1−
゛とコンタクトする口字状のベタ状平板電極部19a、
19bを形成しヘタ状の平板電極部19a、19b内に
集積回路チップ20a、201)を第4図(b)のよう
に配設し4A積回路チソゾ20a、2Qbの複数本の端
末電極21a、21bを上記へ夕状の平板電極19a、
19bに一括半l」イζJ或いは熱圧着させる。次に第
4図fc)に示すように所望の配線パターンに応じて上
記したレーザ光線で切りRli L 2 sを行なう。In FIG. 4 (Fl), reference numeral 17 denotes a ceramic circuit board, which forms a circuit pattern 18 for appropriately connecting the integrated circuit chip mounted on the board, and also forms a circuit pattern 18 for appropriately connecting the integrated circuit chips mounted on the board.
a square-shaped solid flat plate electrode portion 19a in contact with ゛;
A plurality of terminal electrodes 21a of 4A integrated circuit chips 20a, 2Qb are formed, and integrated circuit chips 20a, 201) are arranged in the flat plate electrode portions 19a, 19b in the shape of a hemlock as shown in FIG. 4(b). 21b to the above plate electrode 19a,
19b and heat-bond it all at once. Next, as shown in FIG. 4 fc), cutting Rli L 2 s is performed using the above-mentioned laser beam according to a desired wiring pattern.
かくすることで回路基板内で集積回路20a。This allows the integrated circuit 20a to be integrated within the circuit board.
20bは互いにパクーニングされ所望の端末型(仏21
a、21b同志が接続されることになる。上記実施例で
は実装部品として集積回路チップとして例えばビームリ
ード型チップ等を用いた例を説明したが通當のDIPデ
ツプキャリヤ、フリップチップ等各種に適用可能である
。更に成る特定の配線パターンを形成する場合にも適用
可能である。20b are mutually parcooned to form the desired terminal type (French 21
A and 21b will be connected. In the above embodiment, an example was explained in which a beam lead type chip or the like was used as an integrated circuit chip as a mounting component, but it is also applicable to various types such as a conventional DIP dip carrier, a flip chip, etc. It is also applicable to forming further specific wiring patterns.
すなわち成る配線部分が特にユーザの要求によって変わ
る可能性のある場合に、その部分のみをベタ状の導電部
パターンとなし、この部分をユーザの要求に合ったパタ
ーンとするようにレーザで切断して行く様にしてもよい
。In other words, if there is a possibility that the wiring part may change depending on the user's requirements, only that part is made into a solid conductive pattern, and this part is cut with a laser to create a pattern that meets the user's requirements. You can do as you like.
また、上記実施例では電極間の切り離し手段としてレー
リ′並に電子ヒームについ一ζ述べたが、ダイヤモンド
カッタによるカノテング或いはパターンマスク上からサ
ンISブラストを噴出さ−Uてパターンを形成する等の
機械的方法、或いはフォトレジストを塗布した後にフォ
トリソグラフィによって化学的にエツチングすることで
非導電部を形成するように切り離すようにしてもよい。In addition, in the above embodiments, as a means for separating the electrodes, Rayleigh' or an electronic beam was used as a means for separating the electrodes, but it is also possible to use a machine such as cutting with a diamond cutter or a machine that forms a pattern by ejecting Sun IS blast from above the pattern mask. The non-conductive portion may be separated by a conventional method, or by applying a photoresist and then chemically etching it by photolithography.
以上説明したように本発明によればパターン電極と被接
続電極がこまかいピンチで配列されている間の接合に於
いて、目金せずれ或いは接続不良がなくなり、金属平板
を切断し圧着または圧接させる必要がないので工程が簡
略化出来て煩雑さが解消され一対一で対応する電極の接
続をより確実にし得る特徴を有する。As explained above, according to the present invention, there is no misalignment or poor connection in joining between patterned electrodes and electrodes to be connected arranged in a small pinch, and a metal flat plate can be cut and crimped or pressure-bonded. Since this is not necessary, the process can be simplified, complexity can be eliminated, and the connection of corresponding electrodes on a one-to-one basis can be made more reliable.
第1図は従来の回路基板の配線パターン形成方法を示す
回路基板の平面図、第2図ta+ 、 fb) 、 (
elは本発明の回路基板の配線パターン形成方法を示す
回路基板と被接続物のフレキシブル多芯ケーブルを示す
平面図、第3図は本発明に用いるレーザ或いは電子ビー
J、等のエネルギ線によって電橋を分離するために用い
る装置の一例を示ず路線図、第4図(al (b) (
clは本発明の回路基板の配線パターン形成方法の他の
実施例を示す回路基板と被接続物(ICチップ)とを示
す平面図である。
■・・・回路基板、 2・・・チ・7プ。
3.5・・・電極、 4・・・表示板。
6・・・金属板、 7・・・切断部分。
8・・・ベタ状の端末電極、 9・・・フレキシブル多
芯ケーブル、 10・・・フレキシブル多芯ケーブル電
極2 11・・・切り離し部分、 12・・・接合部分
。
13・・・XYステージ、 14.X、14Y・・・モ
ータ、 15・・・エネルギ線照射源、 16・・・コ
ンピュータ。
17・・・回路基板、 18・・・回路パターン、 1
9a、19b・・・ベタ状平板電極部、 20a、20
b・・・丈積回路チップ
(a)
第1図
(C)
第2図
第4図
8Fig. 1 is a plan view of a circuit board showing a conventional circuit board wiring pattern forming method, and Fig. 2 is a plan view of a circuit board showing a conventional method for forming wiring patterns on a circuit board.
el is a plan view showing a circuit board and a flexible multicore cable to be connected, showing the method of forming a wiring pattern of a circuit board of the present invention, and FIG. An example of the equipment used to separate the bridges is shown in the route map, Figure 4 (al (b) (
cl is a plan view showing a circuit board and a connected object (IC chip) showing another embodiment of the method for forming a wiring pattern on a circuit board according to the present invention. ■...Circuit board, 2...chip/7p. 3.5... Electrode, 4... Display board. 6...Metal plate, 7...Cutting part. 8... Solid terminal electrode, 9... Flexible multicore cable, 10... Flexible multicore cable electrode 2, 11... Separated portion, 12... Joined portion. 13...XY stage, 14. X, 14Y...Motor, 15...Energy ray irradiation source, 16...Computer. 17... Circuit board, 18... Circuit pattern, 1
9a, 19b... solid flat plate electrode portion, 20a, 20
b... Length product circuit chip (a) Figure 1 (C) Figure 2 Figure 4 Figure 8
Claims (1)
ーンを電極パターンとして用いる際に該電極パターンを
予め平板状電極パターンに形成し。 該平板状電極に1本或いは複数本の端子を有する実装部
品を接続した後に上記平板状電極パターンを切断して必
要な配線間を不導通状態とすることを特徴とする回路基
板の配線パターン形成方法。[Scope of Claims] A plurality of wiring patterns are formed on a circuit board, and when the wiring patterns are used as electrode patterns, the electrode patterns are previously formed into flat electrode patterns. Wiring pattern formation for a circuit board, characterized in that after connecting a mounting component having one or more terminals to the flat electrode, the flat electrode pattern is cut to create a non-conducting state between necessary wirings. Method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59037930A JPS60182751A (en) | 1984-02-29 | 1984-02-29 | Formation of wiring pattern of circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59037930A JPS60182751A (en) | 1984-02-29 | 1984-02-29 | Formation of wiring pattern of circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60182751A true JPS60182751A (en) | 1985-09-18 |
Family
ID=12511268
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59037930A Pending JPS60182751A (en) | 1984-02-29 | 1984-02-29 | Formation of wiring pattern of circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60182751A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06163741A (en) * | 1992-11-26 | 1994-06-10 | Kyocera Corp | Production of package for housing semiconductor element |
JP2012051254A (en) * | 2010-09-01 | 2012-03-15 | Toshiba Tec Corp | Inkjet head and method of manufacturing the inkjet head |
-
1984
- 1984-02-29 JP JP59037930A patent/JPS60182751A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06163741A (en) * | 1992-11-26 | 1994-06-10 | Kyocera Corp | Production of package for housing semiconductor element |
JP2012051254A (en) * | 2010-09-01 | 2012-03-15 | Toshiba Tec Corp | Inkjet head and method of manufacturing the inkjet head |
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