JPS60181853A - Disc cache controller - Google Patents

Abstract

PURPOSE:To shorten an apparent access time of a magnetic disc device by providing a disc cache controller with actual cache object areas and virtual cache object areas and switching automatically areas on a basis of frequencies in hit of accesses to both areas as required. CONSTITUTION:When the magnetic disc device is accessed by a higher device, extent tables 5-1 and 5-2 are retrieved; and when it is confirmed that data exists in an actual cache object area or a virtual cache object area, contents of a counter 6-1 (real) of 6-2 (artificial) which counts information indicating access of the area are incremented by +1. If data in the accessed area is stored in a cache memory (in case of a hit), contents of a counter 6-3 (real) or 6-4 (artificial) which counts the number of hits are incremented by +1. The number of accesses (the number of cache objects) and the number of hits are obtained, and, for example, the number of hits is divided by the number of cache objects to calculate a ratio of the number of hits, and an area having the highest ratio of the number of hits is switched to an actual cache object area, thereby shortening an apparent access time.

Description

Detailed Description of the Invention (Technical Field of the Invention) The present invention provides a disk cache control device, particularly a disk cache device provided in a magnetic disk device.
A real cache target area (area that actually performs caching operations) and a virtual cache target M area (area that records only information such as the number of cache targets) are provided, and the hint rate at which data in these areas is accessed is determined. This invention relates to a disk cache control device that determines the hit rate, etc., and switches a virtual cache target area with a high hit rate, etc., to a real cache target area as necessary.

(Technical Background and Problems) A magnetic disk drive is provided with a disk/cash control device in order to apparently improve the access time.

In order to shorten access time as much as possible, the disk cache control device is provided with an area for determining whether or not data is stored in the cache memory when accessed, and an area for not performing any determination. There is. When the area for which the determination is to be made is accessed, a predetermined table is referred to and the data is written in the cache memory. If it is determined that the content has not been accessed, the content is read out and written into the cache memory in preparation for the next access, and is sent to the host device. On the other hand, when an area in which no 1 determination is performed is accessed, the information is read from the disk device and sent to the host device without referring to the predetermined table.

However, if there is access as mentioned above.

This is because the area (actual cache target area) stored in the cache memory and used to determine whether or not the cache exists remains constant unless the area is changed from the host device.

If the job executed by the central processing unit, etc., which is a higher-level device, changes and the area to be accessed changes and becomes different from the actual cache target area that has already been registered, the disk device must be directly accessed. However, there was a problem in that the access time was apparently long.

(Object and Structure of the Invention) An object of the present invention is to solve the above-mentioned problems, and to provide a disk cache control device with a real cache target area and a virtual cache target area.

The degree of Hiso+-IJ accessing the both head regions is determined respectively.

By automatically switching the areas as necessary based on the hint frequency, etc., the purpose of the magnetic disk device is to shorten the above access time depending on the job to be processed. Therefore, the disk cache control device of the present invention is provided between a magnetic disk device and a host device, and is capable of handling data stored in the magnetic disk device.
In the disk cache control device, the real extent table section stores an address area to be stored in the cache memory, and at least one virtual address area that is not stored in the cache memory is registered. a virtual extent table section, an access counter that counts the number of times data in an address area registered in the real extent table section or virtual extent table section is accessed, and a virtual extent table section; a hit counter that counts the number of times data in the held address area is accessed; and a real/real/extent table that switches between the real extent table section and the virtual extent table section based on the contents of the access counter and the hit counter. It is characterized by comprising a virtual extent table switching section.

(Example of the invention) The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a system configuration diagram in which the present invention is used.

FIG. 2 shows one embodiment of the invention, and FIG. 3 shows another embodiment of the invention.

In the figure, 1 is a disk cache control device, 1-1 is a cache memory (CHM), 2-0. ' 2-1 is a magnetic disk control unit (DKC), 3-0° 3-1 is a magnetic disk unit (DKU), 4-0° 4-1 is a central processing unit (CPU), 5-1.5-2 .5-n is an extent table, 6-1 to 6-4 are counters, 7 is an interface, 8 is a tag decoder, 9-1 is a unit register, 9-2 is a cylinder register, 9-3 is a hend register, 10 is a extent decoder, 11 is a microprocessor, 12 is a control storage (C3,)
, 13 is a target/non-target determination circuit, 14 is a hash circuit,
' 15 represents a hash table, and 16 represents an extent table index.

In FIG. 1, numeral 1 in the figure is a disk cache control unit (DCC), which is a magnetic disk control bag! (D
KC) 2-0.2-1 and magnetic disk unit (DKU) 3
-0.3-1. The disk cache control device 1 is provided with a cache memory (CHM) 1''-1, in which data 1.q of the real cache target area registered in advance and frequently accessed data is stored. Therefore, when there is a request to access data in a predetermined area from a central processing unit (CPU) 4-0. When it is stored in -1.

Since the stored data is sent to the host device, access time can be extremely shortened. On the other hand, when the data is not stored in the cache memory f-1 in the disk cache control device 1, the magnetic disk device 3-0.3-1 etc. is accessed and the read data is stored in the disk cache control device 1. For example, LRU (Least Receiver) is stored in the cache memory 1-1 of
ntly Used method) in preparation for the next access, and also sends it to the first-ranked device.

However, - all of the data requested to be accessed from the higher-level device is not stored in the cache memory 1-1 of the disk cache control device mentioned above, but is an area registered in advance from the higher-level device (actual cache target area). Only those persons are subject to this.

For this reason, even if the area recorded in the cache memory l-1 is optimally set, for example, the central processing unit 4-
If the area to be accessed becomes other than the actual cache target area due to a change in the job processed by 0.4-1, the magnetic disk device 3-0.3~
1 has to be accessed, and the access time becomes significantly longer, which is almost the same as if there were no cache, so there was a problem with Gs1 that a sufficient cache effect could not be obtained.

Therefore, the present invention provides that the cache memory 1-1 has a real cache target area, which should be a real cache target area, and a virtual cache target area other than the real cache target area for collecting only information such as accessed users. By providing an area for real cache and a virtual cache area to be stored in the cache memory 1-1 as necessary based on information such as hitting the double-headed area, the apparent &t J - The access time of - is to be shortened. This will be explained in detail below.

In FIG. 2, reference numerals 5-1 and 5-2 are respectively extension 1-tables in which the above-described real cache target area and virtual cache target area according to the present invention are stored, respectively. The area information stored in the extent table 5-1.5-2 is written from a device, etc., or written by the disk cache control device itself to minimize the apparent access time when starting up the magnetic disk device. Preparing initial settings.

When a magnetic disk device is accessed from a host device, if the extent table 5-15-2 is searched and it is found that the area is within the actual cache target area or virtual cache target area, the area is accessed. A counter 6-1 or 6-
Increment the contents of 2 by “+1”. Then, the data in the accessed area is stored in the cache memory (
If it is stored in Figure 1 (1-1) (hint)
In order to count the number of hints, the contents of the counter 6-3 or 6-4 are incremented by +1.

In this way, the number of times the real cache target area and the virtual cache target area are accessed (cache target count) and the number of hints for each of these two areas are calculated.

Then, for example, a hint frequency ratio is calculated by dividing the hit frequency by the cache target frequency, and the area with the largest hit frequency ratio is switched to the actual cache target area.

This apparently shortens the access time above. The following will explain the signal flow.

8 in the figure is a tag decoder, which is a magnetic disk controller (DKC) 2-0.2-. 1 via the interface, decodes the access destination address, and reads the unit number (U), cylinder number (C), and head number (H) of the magnetic disk device 3-0 or 3-1. It is for decoding. The decoded unit number, cylinder number and head number are stored in each illustrated unit register 9-1. Cylinder register 9-2
and is stored in the head register 9-3. Based on the address information stored in each register, a search is performed to determine whether the data is stored in a real cache target area, a virtual cache target area, and a cache memory 1-1 (not shown), which will be described below.

In the figure, IO is an extent decoder.

Decoding a signal for registering or reading a predetermined real cache target area and virtual cache target area in the extent table 5-15-2, or switching between the real cache target area and the virtual cache target area, etc. It is something to do. The extent/
The signal decoded by the decoder is processed by a microprocessor (MPU) 11. The control program for performing this processing is stored in control storage (C
3) Stored in 12.

In the figure, reference numeral 13 denotes a target/non-target determining circuit, which is used to determine whether the address information requested for access is in the real cache target area or the virtual cache target area. The target/non-target determining circuit 13 selects the UNISO 1-register 9-1. Cylinder register 9-2
Then, it is searched whether or not the value corresponding to the address information read from the head register 9-3 exists in the extent table (real) 5-1 and the extent table (virtual) 5-2, and if it exists, the value corresponds to the address information read from the head register 9-3. The counter (actual) 6-1 or the counter (virtual) 6-2 is incremented by "'+1" to count the number of times the operation has been performed. As a result, the number of times the real cache target area or the virtual cache target area is accessed is counted.

In the figure, reference numeral 14 denotes a hash circuit, which is used to determine whether or not the data to which an access request is made is held in the cache memory 1-1. The hash circuit 14 searches whether or not a value corresponding to the address information read from the unit register 9-1, cylinder register 9-2, and head register 9-3 is written in the hash table 15. In the hash table 15, addresses of data held in the cache memory 1-1 and hit addresses within the virtual cache target area are written in the form of LRU. Therefore, as a result of the search, if the data to which the access request is made is within the actual cache target area that involves actual operations, this is notified to the magnetic disk controller 2-0.2-1 and the counter is (Actual) Increment 6-3 by “+1”. On the other hand, as a result of the search, if the data to which the access request is requested is within the virtual cache target area that does not involve actual operation, this is notified to the magnetic disk controller 2-0.2-1 and the counter is (virtual) 6
-4 is incremented by "+1". In this way, the number of times data stored in the cache memory 1-1 or virtual cache memory in the real cache target area or virtual cache target area is accessed.

That is, the so-called hit rate is calculated by counting the number of hits and dividing the number of hints by the number of accesses to each area counted by the counter (actual) 6-1 and counter (virtual) 6-2. I can do it. Then, considering the number of accesses, the number of hints, the hit rate, etc., calculate the area that should be used to reduce the apparent access time, and if the area is the area targeted for virtual cache, , the virtual cache target area is switched to the real cache target area, and the real cache target area is switched to the virtual cache target area. For example, the switching may be performed using the extent table 5-1.5-
This is done by the microprocessor 11 replacing the contents of the pointer pointing to the area where 2 is stored.

FIG. 3 shows an embodiment in which a plurality of virtual cache target areas are prepared. In the figure, numerals 5-1.6 to 15 are the same as those shown in FIG. 2 or are stationary.

Reference numeral 16 in the figure is an extent table index, which sequentially performs page turning by providing a plurality of extent tables 5-n (n=2°3.4...) indicating the virtual cache target areas mentioned above. It is for execution. By providing a plurality of virtual cache target areas using the extent table 5-n and the extent table index 16, one
without being constrained by having one virtual cache target area for one magnetic disk device 3-0.3-1.
It is now possible to divide the same magnetic disk device into multiple areas and collect information such as the number of accesses, number of hints, and hit-node rate mentioned above for each divided area, allowing for more fine-grained control. It becomes possible. At this time, the number of accesses and the number of accesses for each virtual cache target area are counted by the illustrated counter (virtual) 6-2 and counter (virtual) 6-4, respectively, and are stored.

In addition, the counters 6-1 to 6- shown in FIGS. 2 and 3
The number of accesses and the number of hits counted by 4 are read out by the microbrosé nosa 11 as appropriate 5, for example, every hour, and the hit rate etc. are calculated.
The actual cache nosh target area and the predetermined virtual cache target area are switched as necessary to control the disk device so as to shorten the apparent access time.

(Effects of the Invention) As explained above, according to the present invention, a disk cache control device is provided with a real cache target area and a virtual cache target area, and the hit rate etc. that accessed the both areas is calculated, and the cough hint This is because the real cache target area and any virtual cache target area are automatically switched based on the ratio, etc.

The apparent access time of the magnetic disk device can always be kept to a minimum in response to changes in jobs to be processed.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram in which the present invention is used. FIG. 2 shows one embodiment of the invention, and FIG. 3 shows another embodiment of the invention. In the figure, 1 is a disk cache controller, 1-1 is a cache memory (CHM), 2-0.2-1 is a magnetic disk controller (DKC), and 3-0°3-1 is a magnetic disk unit (DKU). ), 4-0°4-1 is the central processing unit (
5-1.5-2.5-n is an extent table, 6-1 to 6-4 are counters, 7 is an interface, 8 is a tag decoder, 9-1 is a unit register, 9-2 is a cylinder 9-3 is a head register, 10 is an extent decoder, 11 is a microprocessor, 12 is a control storage (C3), 13
14 represents a target/non-target determination circuit, 14 represents a hash circuit, 15 represents a hash table, and 16 represents an extent table index. Patent applicant Fujitsu Ltd. Representative Patent Attorney Hiroshi Mori (1 other person) Yu 1 m

Claims (1)

[Claims] Provided between a magnetic disk device and a host device. In a disk cache control device that stores a part of data stored in a magnetic disk device in a cache memory, there is a real extent table section that registers address areas to be stored in the cache memory, and a virtual extent table section that registers address areas to be stored in the cache memory. at least one virtual extent table section in which address areas are registered; and an access counter that counts the number of times data in the address area registered in the real extent table section or the virtual extent table section is accessed, respectively; a hit counter that counts the number of times data in an address area held in the cache memory or virtual cache memory is accessed; 1. A disk drive controller comprising: a real/virtual extent table switching section for switching between an extent table section and an extent table section.