JPS60178645A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60178645A
JPS60178645A JP3496584A JP3496584A JPS60178645A JP S60178645 A JPS60178645 A JP S60178645A JP 3496584 A JP3496584 A JP 3496584A JP 3496584 A JP3496584 A JP 3496584A JP S60178645 A JPS60178645 A JP S60178645A
Authority
JP
Japan
Prior art keywords
semiconductor
integrated circuit
oxide layer
substrate body
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3496584A
Other languages
Japanese (ja)
Inventor
Tsutomu Yamaguchi
力 山口
Shoichi Shimaya
嶋屋 正一
Takemi Ueki
植木 武美
Tadashi Matsumoto
忠 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP3496584A priority Critical patent/JPS60178645A/en
Publication of JPS60178645A publication Critical patent/JPS60178645A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/15165Monolayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Landscapes

  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent characteristics of a semiconductor IC substrate from deteriorating even under irradiation with radiation by providing a heat generation resistor to heat said substrate. CONSTITUTION:A container 1 is provided inside its main body 2 with the heat generation resistor 10 to heat the semiconductor IC substrate 5 to dissipate holes, trapped at the interface between the semiconductor substrate body 6 of the substrate 5 and oxide layers or films 8 and 9 (in case a semiconductor element 7 is an MOS type transistor, containing its gate insulation film) or in its neighborhood, out of the oxide layers or films 8 and 9, e.g. in a plurality or in a buried state. Thereby, when the resistors 10 provided in the container 1 are heated, the heat is conducted to the substrate 5 via container 1, resulting in heating the substrate 5.

Description

【発明の詳細な説明】 源λ吐悲伍艷 本発明は、多数の半導体素子を構成している半導体!!
仮本体と、その半導体基板本体内または半導体基板本体
上に形成されている酸化物層乃至膜とを有して半導体集
積回路を構成しCいる半導体集積回路基板が、容器内に
収容されでいる(δ成を右する半導体装置の改良に関り
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductors that constitute a large number of semiconductor elements! !
A semiconductor integrated circuit board comprising a temporary body and an oxide layer or film formed within or on the semiconductor substrate body to constitute a semiconductor integrated circuit is housed in a container. (Related to the improvement of semiconductor devices that affect δ formation.

本光明の背景 このような半導体装置としで、従来、第1図に路線的に
示すような、外部?ll!結用端子片4を植立させてい
る容器本体2と、υ7)Ls体3とを以て構成された容
器1内に、半導体基板本体(図示せず)と、その半導体
基板本体内−またtよ半導体基板本体上に形成されてい
る酸化物層乃至模(図示Uず)とを右し゛CC半導体装
積回路18成している半導体装積回路基板5が収容され
Cいる構成を右し、そして、その半導体装(i回路基板
5が、第2図に示すような、点線で囲まれている旬号7
′c一般的に示されCいる半導体素子(コレクタ領域、
ベース領域、エミッタ領1或、ベース用電極、1ミツタ
用電極などをイjりるバイポーラ型1〜ランジスタ;ソ
ース領域、ドレイン領域、それら間のチ1シンネル領域
、チトンネル領域上に例えば二酸化シリコンでなるゲー
ト絶縁膜を介して対向しているゲート電極などをイ1り
るMO8型トランジスタなど)の多数を構成しくいる半
導体基板本体6と、その半導体基板水イホ6内に、その
上面側において、多数の半導体素子7を互に分離させる
ように形成されIC例えば二酸化シリコンでなる素子分
離用酸化物層乃芋膜8と、半導体基板本体6上に多数の
半導体素子7及び酸化物層乃至膜8を覆って形成され1
.:同様に例えば二酸化シリコンでなる絶縁用乃至j呆
護用酸化物層乃至膜9とを有する構成をイIJるものが
現用されている。
Background of the present invention Conventionally, in the case of such a semiconductor device, an external device as shown schematically in Fig. 1 has been used. ll! A semiconductor substrate body (not shown) and a semiconductor substrate body (not shown) and a t The structure in which the semiconductor integrated circuit board 5 constituting the CC semiconductor integrated circuit 18 is housed is shown by the oxide layer or pattern (not shown) formed on the semiconductor substrate main body, and , the semiconductor device (i circuit board 5 is surrounded by a dotted line as shown in FIG. 2)
'c Generally shown is a semiconductor element (collector region,
A bipolar transistor in which the base region, emitter region 1, base electrode, 1 mitter electrode, etc. are removed; the source region, the drain region, and the channel region and tunnel region between them are covered with silicon dioxide, for example. A semiconductor substrate main body 6 that constitutes a large number of MO8 type transistors, etc. with gate electrodes facing each other via a gate insulating film, and inside the semiconductor substrate main body 6, on its upper surface side, An IC is formed to separate a large number of semiconductor elements 7 from each other. An oxide layer or film 8 for element isolation made of silicon dioxide, for example, and a large number of semiconductor elements 7 and an oxide layer or film 8 are formed on a semiconductor substrate body 6. formed over 1
.. Similarly, a structure having an insulating or protective oxide layer or film 9 made of silicon dioxide, for example, is currently in use.

このJ、うな構成を有する従来の半導体装置の場合、そ
れが通信衛星などに搭載して宇宙空間で使用されること
によって放射線の照射を受けたとき、半導体集積回路基
板5が、容器5を介しく、その放射線の照射を受ける。
In the case of a conventional semiconductor device having this configuration, when it is mounted on a communication satellite or the like and used in outer space and is irradiated with radiation, the semiconductor integrated circuit board 5 is exposed to radiation through the container 5. and are exposed to that radiation.

このように、半導体集積回路基板5が、放射線の照射を
受Gノれば、その酸化物層乃至膜8及び9内に電子・正
孔対が発生し、その電子・正孔対中、移動速度が電子に
比し 1/10+程度に羅い正孔が、半導体集積回路基
板5の半導体基板本体6と、酸化物層乃至膜8及び9と
の間の界面またはその近傍にJ5りる正孔トラップに1
ili獲されlζ状態になる。このため、半導体基板本
体6が1〕型である場合、その半導体基板本体6の酸化
物層乃至膜8及び9どの間で界面を形成している表面が
n型化したり、半導体基板本体6が11型である場合、
その表面がにす11型化したりづる。
In this way, when the semiconductor integrated circuit board 5 is irradiated with radiation, electron-hole pairs are generated in the oxide layer or films 8 and 9, and the electron-hole pairs move. Holes, whose speed is about 1/10+ that of electrons, are located at or near the interface between the semiconductor substrate body 6 of the semiconductor integrated circuit board 5 and the oxide layers or films 8 and 9. 1 in hole trap
ili is captured and enters the lζ state. Therefore, when the semiconductor substrate body 6 is of type 1], the surface forming the interface between the oxide layer or the films 8 and 9 of the semiconductor substrate body 6 may become n-type, or the semiconductor substrate body 6 may become n-type. If it is type 11,
Its surface has become 11-inch.

また、このように半導体基板本体6の酸化物層乃至膜8
及び9との間で界面を形成している表面が11型化し!
こり、より11型化したり(Jれぽ、半導体基板本体6
に構成されている多数の半導体素子の相隣る半導体素子
が、その半導体基板本体6の酸化物層乃至1118及び
9との間の界面を形成している表面を通じて互に干渉し
たりりる。
Further, in this way, the oxide layer or film 8 of the semiconductor substrate body 6
The surface forming the interface between and 9 is now 11-inch!
(JREPO, semiconductor substrate body 6
Adjacent semiconductor elements of a large number of semiconductor elements constructed in the semiconductor substrate body 6 interfere with each other through surfaces forming interfaces between the oxide layers 1118 and 9 of the semiconductor substrate body 6.

また、半導体基板本体6に構成されている多数の半導体
素子の相隣る半導体素子が11型のトランジスタCある
場合、その相隣るn型の1−ランジスタが導通状態にな
ったりする。
Furthermore, when an 11-type transistor C is an adjacent semiconductor element among a large number of semiconductor elements configured on the semiconductor substrate body 6, the adjacent n-type 1-transistor becomes conductive.

さらに、半導体基板本体6に構成されている多数の半導
(41素子中の半導体素子が上述したバイポーラ型1ヘ
ランジスタである場合、そのバイポーラ型1−ランジス
タのエミッタ領域とベース領域との間で大きなリーク電
流が生じ、その結果、バイポーラ型トランジスタの直流
電流増幅率が低1;シたすする。
Furthermore, when a large number of semiconductor elements (out of 41 semiconductor elements) constituted in the semiconductor substrate body 6 are the above-mentioned bipolar type 1-transistor, a large A leakage current occurs, and as a result, the DC current amplification factor of the bipolar transistor becomes low.

まlこ、上述したように、半導体基板本体5が放射線の
照射を受1プれば、その半導体基板本体に構成しCいる
半導体素子が上述したMO8型トランジスタである場合
は、そのゲート絶縁膜と半>9 (41,4板本体6に
おける2ヂトンネル領域との間の界面ま/jはその近傍
にも、上述したと161様に、正孔が捕獲された状態に
より、半導体基板本体にお1]るチャンネル領域の、ゲ
ート絶縁膜との間(゛界面を形成している表面も、n型
化したり、よりn型化したりづることによって、MO8
型1−ランジスタの閾植電圧に、負方向の変化が牛した
リタる。
As mentioned above, when the semiconductor substrate body 5 is irradiated with radiation, if the semiconductor element formed on the semiconductor substrate body is the above-mentioned MO8 type transistor, its gate insulating film will be damaged. and half>9 (41, 4) The interface between the 2nd tunnel region and the 2nd tunnel region in the 4-plate body 6 also exists in the vicinity thereof, as described above in 161, due to the state in which holes are captured, the semiconductor substrate body 1] By making the surface forming the interface between the channel region and the gate insulating film n-type or more n-type, MO8
Type 1 - A negative change in the threshold voltage of the transistor returns.

従って、第1図及び第2図で−L述した従メ(の半導体
装置の場合、それが放射線の照射を受【Jkどき、その
半導体集積回路基板の特性が劣化する、という欠点を有
していk。
Therefore, in the case of the conventional semiconductor device described in FIGS. 1 and 2, when it is exposed to radiation, the characteristics of the semiconductor integrated circuit board deteriorate. Teik.

本発明の目的 よって、本発明は、上述しIこ欠点のない新規な半導体
装置を提案口んとするものである。
According to the object of the present invention, the present invention proposes a novel semiconductor device that does not have the above-mentioned drawbacks.

本発明の開示 本弁明による半導体装置によれば、見掛1、第1図及び
第2図C上述した従来の半導体装iPiと同様の構成を
右するが、その容器または半導体基板本体に、半導体集
積回路基板の半導体基板本体と酸化物層乃至膜との間の
界面またはイの近傍に捕獲される正孔を酸化物層乃至膜
外に放散さけるべく半導体集積回路基板を加熱りるため
の発熱用抵抗体が設りられている。
DISCLOSURE OF THE INVENTION According to the present defense, the semiconductor device has the same configuration as the conventional semiconductor device iPi described above in appearance 1, FIG. 1, and FIG. Heat generation for heating the semiconductor integrated circuit board in order to avoid dissipating holes captured at the interface between the semiconductor substrate body and the oxide layer or film of the integrated circuit board or in the vicinity of the oxide layer or film outside the oxide layer or film. A resistor is provided for this purpose.

このため、本発明による半導体装置によれは、それが放
射線の照射を受りて使用される場合、発熱用抵抗体を用
いることによつで、hit 04 FAの照射を受4J
ても、半導体集積回路基板の特性が劣化し!こりしない
Therefore, when the semiconductor device according to the present invention is used while being irradiated with radiation, by using a heating resistor, it can be used while being irradiated with hit 04 FA.
However, the characteristics of the semiconductor integrated circuit board deteriorate! No stiffness.

木5e明のbr適な実施例 以下、本発明による半導体装置の好適な実施例を述べよ
う。
PREFERRED EMBODIMENT OF THE INVENTION Hereinafter, a preferred embodiment of the semiconductor device according to the present invention will be described.

実施例゛1 本発明による半導体装置の第1の実施例は、第3図に承
りように、且つ第1図で上述したと同様に、外部連結用
端子片4を植立させている容器本体2ど、ぞの蓋体3と
を以て構成された容器1内に、半導体基板本体(図示t
!す゛)と、その半導体基板本体内または半導体基板本
体上に形成されCいる酸化物層乃至欣(図示せず)どを
6 L/ ”C半導体集積回路を構成している半導体集
積回路J、4板5が収容されている構成を有し、−でし
Cイの゛1′導体集積回路基板5が、第2図で1一連し
たとI+11様に、点線で1川まれ−Cいる符号7(・
一般的【ご小されている半導体素子(」レクタ領域、ベ
ース領域、エミッタ領域、ベース用電極、−1ミツタ川
電稚などを有するバイポーラ型トランジスタ;ソース領
域、ドレイン領域、てれら間のチtTンネル領域、チ1
1ンネル領域に例えば二酸化シリコンでなるゲート絶縁
膜を介して対向しCいるグー1〜電極/、1どを右Jる
M OS型1−ランジスタなど)の多数を構成しCいる
半導体基板本体6と、その半導体基板本体(1内に、そ
の上面側において、多数の半導体素子7を互に分離させ
るように形成された例えば二酸化シリコンでなる素子分
離用酸化物層乃至膜8と、半導体基板本体6土に多数の
半導体素子7及び酸化物層乃至膜8を覆って形成された
+i+様に例えば二酸化シリコンでなる絶縁用乃至保護
用酸化物層乃至膜9とを有している構成を右づるしかし
ながら、本ii!明によるrf導(A装置dの第1の実
施例は、上述した構成を1=Jする゛半導体装置におい
て、第3図に示すように、その容器゛1に、その容器本
体2内において、半導体集積回路基板5の半導体15根
本体6ど酸化物層乃至膜8及び9(半導体索子7がMO
3型ト・ランジスタぐある場合、イのグー1−絶縁膜を
含む)どの間の界面またはその近傍に捕獲される正孔を
酸化物層乃至躾8及び9外に放散させるべく半導体集積
回路基板5を加熱Jるための発熱用抵抗体10が、例え
ば複数、例えば埋設された状態に設番ノられCいる。
Embodiment 1 A first embodiment of the semiconductor device according to the present invention has a container body in which external connection terminal pieces 4 are planted, as shown in FIG. 3 and in the same manner as described above in FIG. A semiconductor substrate main body (t
! Semiconductor integrated circuit J, 4 which constitutes a semiconductor integrated circuit (6L/''C) and an oxide layer or layer (not shown) formed within or on the semiconductor substrate body. If the conductor integrated circuit boards 5 are arranged in one series in FIG. (・
A common semiconductor device (a bipolar transistor with a rector region, a base region, an emitter region, an electrode for the base, -1 Mitsutagawa Denchi, etc.; a source region, a drain region, a channel between the tT tunnel region, chi 1
A semiconductor substrate body 6 comprising a large number of MOS transistors (MOS transistors, etc.) facing each other in the channel region through a gate insulating film made of, for example, silicon dioxide. , an element isolation oxide layer or film 8 made of silicon dioxide, for example, formed on the upper surface side of the semiconductor substrate body (1) so as to isolate a large number of semiconductor elements 7 from each other, and a semiconductor substrate body (1). Figure 6 shows a structure in which an insulating or protective oxide layer or film 9 made of silicon dioxide, for example, is formed in +i+ to cover a large number of semiconductor elements 7 and oxide layers or films 8. However, in the first embodiment of the RF conductor (A device d) according to the present invention, in a semiconductor device having the above-mentioned configuration 1=J, as shown in FIG. In the main body 2, the semiconductor 15 base body 6 of the semiconductor integrated circuit board 5, the oxide layers or films 8 and 9 (the semiconductor cables 7 are MO
If there is a type 3 transistor, a semiconductor integrated circuit board is used to diffuse holes captured at or near the interface between the oxide layer (including the insulating film) to the outside of the oxide layer (8 and 9). For example, a plurality of heating resistors 10 for heating the heating element 5 are installed, for example, in a buried state.

以上が、本発明による半導体装置の第1の実施例の41
6成Cある。
The above is the 41st embodiment of the semiconductor device according to the present invention.
There are six Cs.

このJ、うな構成を有づる本発明による半導体装置によ
れば、容器1に設りられている発熱用抵抗体10 /!
:発熱さければ、その熱が、容器1を介しC1半導体集
積回路基板5に伝導し、その半導体集積回路基板5が加
熱されることが明らかである。
According to the semiconductor device according to the present invention having this configuration, the heating resistor 10 /!
: It is clear that if heat generation is avoided, the heat will be conducted to the C1 semiconductor integrated circuit board 5 through the container 1, and the semiconductor integrated circuit board 5 will be heated.

従つ(、第3図に承り本発明による半導体装置が、/l
I QJ線の照射を受けて使用される場合、発熱用抵抗
体10を発熱さUることによって、放射線の照射を受り
ることによって、半導体基板本体6ど酸化物層乃至股8
及び9との間の界面またほぞの近傍の正孔トラップに正
孔が捕獲され゛(b、その正孔が、酸化物層乃至脇8及
び9外に、効果的に1151敗される。
Accordingly, according to FIG. 3, the semiconductor device according to the present invention is /l
When used while being irradiated with IQJ rays, the heating resistor 10 generates heat and the radiation irradiates the semiconductor substrate body 6, oxide layer to crotch 8.
Holes are captured in the hole traps near the interface between and 9 and the tenon (b), and the holes are effectively lost 1151 out of the oxide layer or sides 8 and 9.

このため、第3図に示づ本発明にJ:る半導体装置の場
合、第1図及び第2図をイ1′なっUl−述した従来の
半導体装置が右りる欠貞を右動に回避りることができる
、という特徴を右りる、。
Therefore, in the case of the semiconductor device according to the present invention shown in FIG. It has the characteristic that it can be avoided.

実施例2 本発明による半導体装置の第2の実施例は、第3図に示
ツにうに、且つ第1図C上述したと同様に、外部連結用
端子片4を植立さI!cいる容器本lA2ど、その蓋体
3とを以て構成された容器1内に、半導体基板本体(図
示Uず)と、その半導体基板本体内または半導体基板本
体」−に形成されている酸化物層乃至股(図示I!ヂ)
とを有して半導体集積回路を構成している半導体集積回
路基板5が収容されている構成を右し、そして、その半
導体集積回路基板5が、第2図で上述したと同様に、点
線で囲まれている符号7で一般的に示されている半導体
素子(」レクタ領域、ベース領域、エミッタ領域、ベー
ス用電極、エミッタ用電極などを右するバイボーラ型]
・ランジスタ:ソース領域、ドレイン領域、ぞれら間の
ブヤンネル領域、チt・ンネル領域に例えば二酸化シリ
コンでなるゲート絶縁膜を介しく対向しCいるゲート電
極などを有づるMO8型I・ランジスタなと)の多数を
構成している半導体基板本体6ど、その半導体基板本体
G内に、その上面側において、多数の半導体素子7を互
に分1Illさせるように形成された例えば二酸化シリ
」ンでなる素子分離用酸化物層乃至膜8と、?I’ 聯
(A基板本体6上に多数の半導体素子7及び酸化物層乃
至膜8を覆って形成された同様に例えば二酸化シリコン
でなる絶縁用ノリ至保護用酸化物層乃至膜9とを有して
いる構成を有する。。
Embodiment 2 In a second embodiment of the semiconductor device according to the present invention, as shown in FIG. 3 and in the same manner as described above in FIG. In a container 1 consisting of a container 2 and a lid 3, there is a semiconductor substrate body (not shown) and an oxide layer formed within or on the semiconductor substrate body. ~crotch (illustration I!ヂ)
The structure in which the semiconductor integrated circuit board 5 constituting the semiconductor integrated circuit is housed is shown on the right, and the semiconductor integrated circuit board 5 is indicated by the dotted line as described above in FIG. Semiconductor elements generally indicated by the enclosed symbol 7 (a bibolar type including a rectifier region, a base region, an emitter region, a base electrode, an emitter electrode, etc.)
・Lansistor: An MO8 type I transistor that has a source region, a drain region, a channel region between them, and a gate electrode that faces each other through a gate insulating film made of silicon dioxide, for example. The semiconductor substrate main body 6 constituting the majority of the semiconductor substrate main body G is made of silicon dioxide, for example, and is formed in such a way that a large number of semiconductor elements 7 are separated from each other on the upper surface side thereof. The element isolation oxide layer or film 8, ? I' (A) has an insulating glue or protective oxide layer or film 9 made of silicon dioxide, for example, formed on the A substrate body 6 to cover a large number of semiconductor elements 7 and the oxide layer or film 8. It has the following configuration.

しかしながら、本発明による半導体装置の第2の実施例
は、上述した構成を有する半導体装置におい(、その半
導体集積回路基板5が、第4図に示1ように、その半導
体集積回路基板5に、その半導体基板本体6内においC
1本発明による半導体装置の第1の実施例の場合と同様
の半導体集積回路基板5の半導体基板本体6と酸化物層
乃至RtA8及び9く¥−尋休体子7がMO8型トラン
ジスタである場合、そのグー1〜絶縁膜を含む)との闇
の界廁またはその近傍に捕獲される正孔を酸化物層乃至
躾8及び9外に放敗さ口るべく半導体集積回路基板5を
加熱JるIこめの発熱用抵抗体10が、例えば複数、例
えば埋設されている状態に設()られ°(いる。
However, in the second embodiment of the semiconductor device according to the present invention, in the semiconductor device having the above-mentioned configuration, the semiconductor integrated circuit board 5 is as shown in FIG. Inside the semiconductor substrate body 6
1 When the semiconductor substrate body 6 and the oxide layer to RtA 8 and 9 of the semiconductor integrated circuit board 5 are MO8 type transistors as in the first embodiment of the semiconductor device according to the present invention. , the semiconductor integrated circuit board 5 is heated so that the holes captured in or near the dark world (including the insulating film 1 to the insulating film) are released to the outside of the oxide layer 8 and 9. A plurality of heat-generating resistors 10 are installed, for example, in a buried state.

以上が、本発明による半導体装置の第2の実施例の構成
である。
The above is the configuration of the second embodiment of the semiconductor device according to the present invention.

このような構成を有りる本発明による゛ト脣体装置によ
れば、容器1に設けられ−Cいる発熱用抵抗体10を発
熱させれば、゛[′導体集(^回路jA板5が加熱され
ることが明らかである。
According to the body device according to the present invention having such a configuration, when the heating resistor 10 provided in the container 1 and located at -C is made to generate heat, the It is clear that it is heated.

従って、第1図及び第4図に承り本発明にJ、る半導体
装置が、放射線の照射を受けて使用される場合、第3図
に示す本発明にJ:る半導体装置の場合と同様に、発熱
用抵抗体10を発熱さけることによって、放射線の照射
を受Gプることによって、半導体基板本体6と酸化物層
乃至股8及び9どの間の界面またはその近傍の正孔トラ
ップに正孔が捕獲されても、その正孔が、酸化物層乃i
股8及び9外に放散される。
Therefore, when the semiconductor device J according to the present invention shown in FIGS. By avoiding heat generation in the heating resistor 10 and receiving radiation, holes are created in hole traps at or near the interface between the semiconductor substrate body 6 and the oxide layers 8 and 9. Even if the hole is captured, the hole is absorbed into the oxide layer.
It is radiated to the outside of the thighs 8 and 9.

このため、第1図及び第4図に示1本発明による半導体
装置の場合ら、第1図及び第2図を伴なって上述した従
来の半導体装置が有する欠点を右動に回避りることがで
さる、という特徴をイjづる。
Therefore, in the case of the semiconductor device according to the present invention shown in FIGS. 1 and 4, the drawbacks of the conventional semiconductor device described above with reference to FIGS. 1 and 2 can be avoided. Let's talk about the characteristic of being a monkey.

実施例3 本発明による半導体装置の第3の実施例は、本発明によ
る半導体装置の実施例2の場合と同様に、外部連結用端
子片4を植立さUている容器本体2どその器体3とを以
て(14成された容器1内に、半導体基板本体(図示l
ず)と、その半導体基板本体内または半導体基板本体内
に形成され゛(いる酸化物層乃至膜(図示μず)とをイ
jして半導体集積回路を構成している半導体集積回路J
:I板5が収容されCいる構成を有し、そし−(での1
(4#体集積回路基板5が、点線で囲まれ(いる旬月7
で一般的に示されている半導体素子(コレクタ領域、ベ
ース領域、エミッタ領域、ベース用電極、エミッタ用電
極などをイーjtlるバイポーラ型1〜ランジスタ:ソ
ース領域、ドレイン領域、それら間のチIlンネル領域
、ブ11ンネル領域に例えば二酸化シリ」ンでなるゲー
ト絶縁膜を介して対向しているグー1〜電極などを右り
るM OS型i・ラン。ジスタなと)の多数を構成して
いる半導体基板本体6と、ぞの半導体基板本体6内に、
その上面側において、多数の半導体素子7をnに分離ざ
μるように形成された例えば二酸化シリコンでなる素子
分離用酸化物層乃至股8と、半導体基板本体6土に多数
の半導体素子7及び酸化物層乃〒膜8を覆って形成され
た同様に例えば二酸化シリ」ンでなる絶縁用乃至保訛用
酸化物層乃至膜9どをイjしCいる構成を右りる。
Embodiment 3 The third embodiment of the semiconductor device according to the present invention is similar to the case of the second embodiment of the semiconductor device according to the present invention. A semiconductor substrate body (shown in the figure) is placed in a container 1 with a body 3 (14).
A semiconductor integrated circuit that constitutes a semiconductor integrated circuit by forming a semiconductor integrated circuit (1) and an oxide layer or film (not shown) formed within the semiconductor substrate body or within the semiconductor substrate body.
: It has a structure in which the I plate 5 is accommodated, and
(The #4 integrated circuit board 5 is surrounded by dotted lines.
Semiconductor elements (collector region, base region, emitter region, base electrode, emitter electrode, etc.) generally shown in bipolar type 1 to transistor: source region, drain region, channel between them. It constitutes a large number of MOS type i-runs (such as transistors) that face the channel region and the channel region through a gate insulating film made of, for example, silicon dioxide. Inside the semiconductor substrate body 6 and the other semiconductor substrate body 6,
On the upper surface side, there is an oxide layer for element isolation made of silicon dioxide, for example, formed so as to separate a large number of semiconductor elements 7 into n parts, and a large number of semiconductor elements 7 and An oxide layer or a protective oxide layer or film 9 made of silicon dioxide, for example, is formed to cover the oxide layer or film 8.

しかしながら、本発明にJ、る半導体装置の第J3の実
施例は、上述した構成をイjする崖導体装背において、
その半導体集積回路Li板5が、第5図に承りように、
その半導体yA梢回路基板5に、その酸化物層乃至膜8
内において、本発明による半導体装置の第1及び第2の
実施例の場合と同様の半導体集積回路基板5の半導体基
板本体6ど酸化物層乃至膜8及び9(半導体素子7がM
O8型1〜ランジスタである場合、そのグー1−絶縁膜
を含む)の間の界面まIこはその近傍に捕獲される正孔
を酸化物層乃至牧8及び9外に/lk敗さけるべく半導
体集積回路基板5を加熱りるための発熱用抵抗体10が
、例えば、複数、例えばJ!Ij nQされている状態
に設けられている。
However, in the J3rd embodiment of the semiconductor device according to the present invention, in the cliff conductor mounting back having the above-mentioned configuration,
As shown in FIG. 5, the semiconductor integrated circuit Li board 5 is
The oxide layer or film 8 is placed on the semiconductor yA top circuit board 5.
In the semiconductor substrate body 6 of the semiconductor integrated circuit substrate 5 similar to the first and second embodiments of the semiconductor device according to the present invention, the oxide layer or the films 8 and 9 (the semiconductor element 7 is
In the case of an O8-type transistor, holes captured at or near the interface between the oxide layer (including the insulating film) and the oxide layer should be avoided. For example, a plurality of heating resistors 10 for heating the semiconductor integrated circuit board 5, for example, J! Ij nQ is provided.

以上が、本発明による半導体装置の第3の実施例の41
4成である。
The above is the 41st embodiment of the third embodiment of the semiconductor device according to the present invention.
It is four generations.

このよ、うな構成を有覆る本発明による半導体賛同にJ
、れば、第1図及び第4図番”l述した本発明による半
導体装置の第2の実施例の場合と同様に、容器1に設【
ノられている発熱用抵抗体゛10を光熱さUれば、半導
体集積回路基板5が加熱されることが明らかであるので
、放射線の照射を受りて使用される場合、発熱用抵抗体
10を光熱さUることににっU、/+’J剣線の照射を
受【ノることによつ(、半導体J、i 41z本体6ど
酸化物層乃至膜8及び9との間の界面またほぞの近傍の
正孔トラップにi[孔が捕獲され−くし、その正孔を、
酸化物層乃至膜8及び9外に放敗さUることができ、よ
って、第1図及び第2図を伴なって上述した従来の半導
体装16が右づる欠点を伴なわない、という特徴を右り
る。1なお、上述に於い(は、本発明の1〆M /JX
な実施例を示したにfBまり、本発明の精神を脱するこ
となしに、種々の変型、変更をなし116であるう、。
As described above, J
, then, as in the case of the second embodiment of the semiconductor device according to the present invention described in FIGS.
It is clear that the semiconductor integrated circuit board 5 will be heated if the heated resistor 10 is exposed to light, so if it is used while being irradiated with radiation, the heat generating resistor 10 By being exposed to the irradiation of the light beam, the semiconductor body 6 is exposed to the oxide layer or between the films 8 and 9. A hole is captured in the hole trap near the interface or tenon, and the hole is
The oxide layer or films 8 and 9 can be oxidized to the outside, and therefore, the conventional semiconductor device 16 described above with reference to FIGS. 1 and 2 does not have the disadvantages. Right. 1. In addition, in the above (1〆M/JX of the present invention
Although the embodiments have been shown, various modifications and changes can be made without departing from the spirit of the invention.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図番よ、従来の半導体装置を承り一部をllli面
にした路線的正面図である。 12図は、従来の半導体装δに用い(いる半導体集積回
路基板の要部を示す路線的断面図Cある。 第3図は、本発明による半導体装置の第′1の実施例を
示す一部を断面にし1JW8線的正面図である。 第4図は、本発明による半導体装置の第2の実施例にJ
3い′C用いている半導体集積回路基板の要部の路線的
断面図である。 第5図は、本発明による半導体装置の第3の実施例にJ
3いて用いている半導体集積回路基板の要部の路線的断
面図である。 1・・・・・・・・・・・・・・・容器2・・・・・・
・・・・・・・・・容器本体3・・・・・・・・・・・
・・・・熱体4・・・・・・・・・・・・・・・外部連
結用端子片0・・・・・・・・・・・・・・・半導体集
積回路基板6・・・・・・・・・・・・・・・半導体基
板本体7・・・・・・・・・・・・・・・半導体素子8
.5)・・・・・・・・・・・・酸化物層乃至膜10・
・・・・・・・・・・・・・・発熱用抵抗体出願人 日
本電信電話公社 第1図
Figure 1 is a schematic front view of a conventional semiconductor device, with a portion of the semiconductor device having an lli surface. FIG. 12 is a cross-sectional view C showing the main parts of a semiconductor integrated circuit board used in a conventional semiconductor device δ. FIG. FIG. 4 is a front view taken along the line 1JW8 in cross section. FIG.
FIG. 3 is a cross-sectional view of the main parts of the semiconductor integrated circuit board used in the present invention. FIG. 5 shows a third embodiment of the semiconductor device according to the present invention.
3 is a schematic cross-sectional view of the main parts of the semiconductor integrated circuit board used in the third embodiment. 1・・・・・・・・・・・・Container 2・・・・・・
・・・・・・・・・Container body 3・・・・・・・・・・・・
...Heating body 4 ...... Terminal piece for external connection 0 ...... Semiconductor integrated circuit board 6 ... ...... Semiconductor substrate body 7 ...... Semiconductor element 8
.. 5)...... Oxide layer or film 10.
・・・・・・・・・・・・Heating resistor Applicant Nippon Telegraph and Telephone Public Corporation Figure 1

Claims (1)

【特許請求の範囲】 多数の半導体素子を構成しCいる半導体基板本体と、該
半導体基板本体内または半導体基板本体上に形成されて
いる酸化物層乃至膜とを有して半導体集積回路を構成し
ている半導体集積回路基板が、容器内に収容されている
構成を有づる半導体装置にJ3いて、 上記容器または半導体基板本体に、上記半導体集積回路
基板の半導体基板本体と酸化物層乃〒股との間の界面ま
たはぞの近傍に捕獲される正孔を上記酸化物層乃至膜外
に放散させるべく上記半導体集積回路基板を加熱づるた
めの発熱用抵抗体が設置ノられていることを特徴とづる
半導体装置。
[Claims] A semiconductor integrated circuit is constituted by having a semiconductor substrate body that constitutes a large number of semiconductor elements, and an oxide layer or film formed within or on the semiconductor substrate body. In a semiconductor device having a structure in which a semiconductor integrated circuit board having a structure of A heating resistor is installed to heat the semiconductor integrated circuit board in order to diffuse holes captured at or near the interface between the semiconductor integrated circuit board and the oxide layer or film. Tozuru semiconductor device.
JP3496584A 1984-02-25 1984-02-25 Semiconductor device Pending JPS60178645A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3496584A JPS60178645A (en) 1984-02-25 1984-02-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3496584A JPS60178645A (en) 1984-02-25 1984-02-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60178645A true JPS60178645A (en) 1985-09-12

Family

ID=12428853

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3496584A Pending JPS60178645A (en) 1984-02-25 1984-02-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60178645A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5957099A (en) * 1997-06-26 1999-09-28 Mitsubishi Heavy Industries, Ltd. Air-cooled engine for general use

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5957099A (en) * 1997-06-26 1999-09-28 Mitsubishi Heavy Industries, Ltd. Air-cooled engine for general use

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