JPS60175295A - Method and device for controlling dynamic memory refreshing - Google Patents

Abstract

PURPOSE:To reduce power consumption of at the time of refreshing and to suppress unnecessary noise occurrence by performing a refreshing action only for a bank being used and a bank already used. CONSTITUTION:The above-mentioned device is designed so as to pass a dummy cycle only for a bank being used and a bank already used in response to a bank using condition according to a sequence of a bank A, bank B, bank C, and bank D, and to perform a normal refreshing action. For example, in using the bank B, the device passes the dummy cycle with respect to a bank B and the already used bank B and performs a normal refreshing action for the banks A and B. By providing refreshing control to the device, the power consumption at the time of refreshing can be largely reduced as compared with conventional devices which refresh always collectively all banks.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic memory refresh control method and apparatus for performing refresh control on a dynamic memory whose entire storage area is divided into a plurality of banks.

[Prior art]

In general, dynamic memory stores stored information in the form of charges in the parasitic capacitance of the gate of the memory element.
Due to leakage current, stored information is lost after a predetermined period of time. Therefore, a so-called slow refresh operation is required to amplify and reproduce the information in the memory cell at regular intervals (approximately 2 ms).

The first factor is an example of a general dynamic memory access device.

In FIG. 1, 1 is a dynamic memory using a dynamic RAM array, and 2 is a CPU.

3 is an address signal applied to dynamic memory 1 (normal address is A6-16; refresh address is R8
-6) Multiplexer for switching, 4 is a refresh address generator, 5 is a refresh timer, 6 is an arbiter for switching between the command output from cptr2 and the refresh request signal generated by refresh timer 5, 7 is a timing generator , 8 is a buffer for write enable signal WE, 9 is a buffer for CAS signal, 10 is a RAS decoder, and 20 is a latch for bank address signal.

Address signal A output from CPU2. -15 is divided into 8 bits and input to multiplexer 3.

The output of the multiplexer 3 is alternately supplied to the address terminals ADo-, of the dynamic memory 1 in accordance with the control signal SL supplied from the timing generator 7. On the other hand, the refresh address signal R6-6 is outputted from the refresh address generator 4 at a period determined by the refresh timer 5, and the refresh address signal Re a is dynamically outputted via the multiplexer 3 under the control of the control signal SL from the timing generator 7. It is applied to the address terminal of memory 1.

The arbiter 6 receives command information from the CPU 2 during a period other than the refresh operation, and receives the WE multiplied signal CAS signal and the RA signal from the timing generator 7.
Outputs S signal. The WE signal is supplied to one terminal of the dynamic memory 1 via the WE buffer 8, and is used as an enable signal during writing. CAS signal is C
Cτ1 of the dynamic memory 1 via the AS buffer 9
It is supplied to the terminal and used as a strobe signal for column address. RAS signal is rτj decoder 10
After the logic for bank selection of the dynamic memory 1 is determined by the RAS-decoder 10, it is supplied to the -RAS terminal of the dynamic memory 1 and used as a strobe signal for the row address. Do-
, is a data signal.

FIG. 2 shows the conventional internal configuration of the RAS decoder 10 and the conceptual configuration of the dynamic memory 1.

The dynamic memory 1 is a dynamic type RAM array, and in this case, the total storage capacity is assumed to be 256 bytes. Normally, the entire storage area of such large-capacity memory is divided into multiple banks, in this case 6 banks.
4-bank configuration (Bank A
Bank D).

The RAS decoder 10 is composed of a 2-bit input/4-bit output decoder 11 and several logic gates. A total of 2 bits of extended address signal A16 y A17 is supplied to the input terminal of the decoder 110 from the bank address latch 20 (see FIG. 1), and the decoder 11 decodes the extended address signal AIII+A17 to generate bank selection signals Ba to Bd. Outputs alternatively. Therefore, if the R71J signal is input while any of the bank selection signals Ba-Bd is being output, this will be supplied to the RAS terminal of the corresponding bank of the dynamic memory 1, and only the corresponding bank will be valid. .

Next, conventional refresh control will be explained. Here, a case will be described in which the entire area of each bank is refreshed in 128 cycles. As mentioned above, each memory cell in dynamic memory 1 needs to be refreshed once every 2 ms, so if you try to do this in 128 cycles, you will need to refresh once every 15.6 μs. . Therefore, the refresh address generator 4 generates a fresh address signal Ro-s which is updated one by one every 15.6 μs.
This is sent to dynamic memory 1 via multiplexer 3.
It is commonly input to each bank A, B, C, and D. On the other hand, the refresh timer 5 outputs a refresh request signal RFSH to the RAS decoder 10 via the arbiter 6 and timing generator 7 every 15.6 μS. When the refresh request signal RFSH is input,
Gates 12, 13, 14, 15 in RAS decoder 10
At the same time, each output becomes a logic low level, and the row address strobe terminals RASO, RASI, RAS2°R of each bank A, B, C, D of dynamic memory 1
At the same time, AS3 becomes a low logic level and all banks are selected once. FIG. 3 shows a time chart of the conventional RAS-only refresh described above.

In this manner, in the conventional refresh control method, all banks are refreshed at once.

For this reason, the RAS only reflex sensor δ shown in FIG. 4 and the RAS terminal (R-ASO) of each bank.

RASI, RAS2. The power consumption peaks at the falling and rising points of RAS3), and noise is generated along with this, which may cause the device to malfunction.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a dynamic memory fresh control method and device that reduce power consumption when refreshing a dynamic memory and prevent unnecessary noise from occurring. With the goal.

[Structure of the invention]

In this invention, in accordance with the usage status of each bank of dynamic memory, normal refresh operation is performed after a dummy cycle has elapsed only for banks in use and banks that have already been used. The above objective is achieved by not performing freshy operation on unused banks and placing them in a standby state.

〔Example〕

Hereinafter, the present invention will be described in detail according to embodiments shown in the accompanying drawings.

FIG. 5 shows an embodiment of the main part of the refresh control device according to the present invention, and is similar to the previous FIGS. 1 and 2.
Components that are the same as those shown in the figures are designated by the same reference numerals, and their explanations will be omitted. In this embodiment as well, it is assumed that the dynamic memory 1 has a four-bank configuration of bank A, bank B, bank C, and upper back D.

In FIG. 5, bank selection signals Ba, Bb, Bc, and Bd output from the decoder 11 are output from AND gates 41 and 4.
2. It is input to one input terminal of 43 and 44, respectively. The same 1RAs signal is supplied from the timing generator 7 (see FIG. 1) to the other input terminals of the AND gates 41, 42, 43 and 44, and the AND gates 41, 42, 43 and 44 , and the output is applied to the row address strobe terminals RASO, 45, 46, 47, and 48 of each bank A, B, C, and D in the dynamic memory 1.
RASI, RAS2, and RAS3, respectively. In the device of this embodiment, as in the conventional device shown in FIG. 2, bank selection control for reading, writing, etc. of the dynamic memory 1 is performed by operating these parts.

Next, the bank selection signal Ba output from the decoder 11
, Bb, Bc, and Bd are bank address latches 30
is input. Here, the bank address latch 30 resets all the latches 30-A and 30 by the reset signal R8T.
-B, 30-C, and 30-D are reset all at once, and the descendant latches from which the reset is released receive the respective bank selection signals Ba and Bb.

It operates so that only the first falling edge of Bc and Bd is latched separately, and the latched contents are held until the next reset signal R8T is input. Each output of this bank address latch 30 is inputted to one input terminal of each of AND gates 51, 52, 53, and 54, and is connected to the refresh request signal -RF8H output from the refresh timer 5 (see FIG. 1). The logical AND of is taken. Logical product game h51
．． The respective outputs of 52, 53 and 54 are connected to the OR gate 45,
46, 47 and 48 respectively to the row address strobe terminals RASO and RASI of the dynamic memory 1.

The signals are supplied to RAS2 and RAS3, respectively. In the device of this embodiment, refresh control of the dynamic memory 1 is performed by operating these parts.

Next, a sixth example of the refresh operation by the above embodiment device will be described.
A detailed explanation will be given according to the flowchart shown in the figure.

When the power is turned on, a reset signal R8T is input, and the contents of each latch in the bank address latch 30 are reset all at once. Thereafter, by canceling this reset operation, the bank address latch 30 enters a latchable state, and each bank selection signal B output from the decoder 11
A state is reached in which the first falling edge of a - B d can be latched separately.

As described above, once this falling edge is latched, the latched contents are held until the next reset signal R8T is input.

Thereafter, when a write request is issued to the memory 1, it is determined whether the access is a serial address access or a random address access. First, the operation in case of serial address access will be explained. The bank of dynamic memory 1 is bank A.
, Bank B.

It is assumed that banks C and D are accessed in this order.

Before a write operation for bank A is started, extended address signals At6. Aty is input to the decoder 11, and the signal A16 e
Decode A17. As a result, only the bank selection signal Ba for bank A becomes a logic low level.

The latch 30-A of the bank address latch 30 latches this falling edge and transfers the contents of this latch to the next reset signal i.
Hold until i1 is input. As a result, only the output of the latch 30-A of the bank address latch 30 becomes a logic low level, and the refresh request signal RFS
The logical product of the AND gate 51 is established only when H is input, and the low output of the AND gate 51 is sent to the row address strobe terminal RA of bank A via the logical sum gate 45.
It can be supplied to SO. That is, at this point, only bank A can be refreshed. In this state, it is searched whether the write request for bank A is the first write request for bank A or not. In the case of the first write request, first, a refresh request signal RFSH is inputted appropriately to execute about eight refresh dummy cycles only for bank A. In this case, a dummy cycle whose purpose is not to write or read information is substituted with a refresh cycle. Upon completion of this dummy cycle, the entire address area of bank A becomes ready for write operation for the first time. After this, RAS signal, 11 at j
By appropriately applying signals such as 'WT signal, address signal AO-15, etc., access operations such as writing and reading to bank A are performed in accordance with the address order. Also, during this memory access period,
For example, a normal refresh operation is performed every 15.6 μs, but in this case only bank A is refreshed.

Next, it is assumed that the access to bank A ends and the access shifts to bank B. As described above, before the write operation for bank B is started, extended address signals AI6+AI7 corresponding to bank B are input to the decoder 11, and the decoder 11 decodes this A 16 t A 17. As a result, bank selection signal B for bank B
b is a logic level and becomes a low level. The latch 30-B of the bank address latch 30 latches this falling edge,
This latch content is held until the reset signal 111 is input. In addition, at this point, the set signal -
Since RST has not yet been input, the latched contents of the latch 30-A corresponding to the knock A still hold the low level. Therefore, the bank address latch 30
The AND of the AND gates 51 and 52 is established only when the outputs of the latches 30-A and 30-B maintain a low logic level and the refresh request signal nvsK is input. The low outputs of 52 can be supplied to row address strobe terminals RASO and RASI of banks A and B by passing through OR gates 45 and 46, respectively. That is, at this point, only banks A and B can be refreshed. In this state, it is checked whether the write request for bank B is the first write request for bank B or not. If it is the first write request for bank B, first a dummy cycle is caused to elapse by appropriately inputting the refresh request signal RF S Ii.

However, this dummy cycle is executed not only for bank B but also for bank A. After this, 10"
Face signal, 11 signal, -wr6 signal, address signal AO
By appropriately adding Is, etc., the access operation to bank B is performed in accordance with the address order. The normal refresh operation performed during this memory access period for bank B is performed not only for bank B but also for bank A that has already been accessed.

Next, it is assumed that the access to bank B ends and the access shifts to bank C. In this case as well, before the write operation to bank C is started, bank C
The extended address A16.degree.17 corresponding to is input to the decoder 11, whereby the output of the latch 30-C of the bank address latch 30 becomes low level. At this point, the set signals R8T have not yet been inputted all at once, so the output of the bank address launch 30 is still held at a low level not only in the latch 30-C but also in the latches 30-A and 30-B. Therefore, the dummy cycle in this case is performed not only for bank C but also for bank A and bank B, and the normal refresh operation performed during the memory access period for bank C is also performed for bank A, bank B, and bank C. is executed.

Thereafter, the above-described refresh operation is repeated in the same manner. Then, at the time when the access to the dynamic memory 1 is completed, the -simultaneous reset signal R8T
is re-inputted into the bank address latch 30, and as a result,
Refreshing of the dynamic memory 1 becomes impossible.

That is, in this embodiment, bank A, bank B, bank C
, bank D in the order i. Corresponding to the usage status of the banks, a dummy cycle is caused to elapse and a normal refresh operation is performed only for banks currently in use and banks that have already been used. For example, bank B
When using , a dummy cycle is passed for bank B and already used bank A, and then a normal refresh operation is performed for bank A and bank B.

Since such refresh control is performed, power consumption during refresh can be significantly reduced compared to the conventional method in which all banks are always refreshed at once.

By the way, when the access to the memory 1 is a random address access, the bank selection signal Ba is sent from the decoder 11 so that bank A, bank B, bank C, and bank D are all in the selected state.

Bb, Be, and Bd are all transmitted. As a result, all the outputs of the bank address latch 30 become low level,
All banks become refreshable. and,
By appropriately inputting the refresh request signal RFSR-, all banks undergo a refresh dummy cycle, and as a result, all banks become in a writable state. In the subsequent normal refresh operation, all banks are in the selected state, so all banks are refreshed at once.

Next, FIG. 7 shows another embodiment of the present invention.

This embodiment has a configuration in which one-shot multivibrator circuits 61, 62, 63, and 64 and an OR gate 65 are added to the configuration shown in FIG.

In FIG. 7, each output of each latch 30-A, 30-B, 30-C, 30-D of the bank address launch 30 is connected to a one-shot multi-bye break circuit 61, 62, respectively.
, 63, 64 are input to each input terminal. One-shot multi-bye break circuits 61, 62, 63, and 64 trigger the fall of each output of bank address latch 30, and output a pulse signal of a predetermined width determined by each resistor and capacitor. This pulse width is set to a width corresponding to the required dummy cycle time for each bank. Therefore, the multi-bye break circuits 61, 62,
Each pulse signal output from 63 and 64 represents the required dummy cycle time in each corresponding bank. Multi-bye break circuit 61, 62
, 63°64 are input to the OR gate 65,
After the OR gate 65 performs the logical sum, it is output to the CPU 2 (see Figure 1) as a BUSY signal indicating the waiting time due to the dummy cycle.The CPU 2 receives this BUSY signal. During this period, no write or read operation is started for the dynamic memory 1. With this configuration, the CPU 2 side can accurately calculate the waiting time using dummy cycles, regardless of whether the access is serial address access or random address access. This enables efficient memory access operations.

In the above-described embodiment, the circuit is configured with negative logic, but it goes without saying that the circuit may be configured with positive logic or a combination of positive logic and negative logic.

By the way, the present invention is not limited to the apparatus of the above embodiment. In short, the device should be configured so that refresh control is performed after a dummy cycle has elapsed only for banks currently in use and banks that have already been used, depending on the bank use state for the dynamic memory.

〔Effect of the invention〕

As described above, according to the dynamic memory refresh control method and device according to the present invention, refresh operations are performed only for banks that are in use and banks that have already been used, thereby reducing power consumption during refresh. At the same time, it is possible to suppress the generation of unnecessary noise associated with this.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a general dynamic memory access device, Fig. 2 is a circuit configuration diagram of a conventional RAS decoder, Fig. 3 is a time chart showing general RAS-only refresh timing, and Fig. 4 is a block diagram showing an example of a general dynamic memory access device. The figure is a graph showing the current consumption characteristics of general dynamic memory.
FIG. 5 is a circuit configuration diagram showing one embodiment of the main part of the present invention, FIG. 6 is a flowchart showing an example of the operation of the embodiment shown in FIG. 5, and FIG. FIG. 2 is a circuit configuration diagram showing an example. 1...Dynamic memory, 2...CPU, 3...
- Multiplexer, 4... Refresh address generator, 5... Refresh timer, 6... Arbiter, 7... Timing generator, 8...-
W1 buffer, 9...CAS buffer, 10...R
AS7” Korg, 11...Decoder, 20...Latch, 3o...Bank address latch, 61, 62, 6
3.64...One-shot multivibrator circuit

Claims (4)

[Claims] (1) In a dynamic memory refresh control method that performs refresh control on a dynamic memory in which the entire storage area is constituted by a plurality of banks and each bank is sequentially accessed in a predetermined order, the usage state of each bank is A dynamic memory refresh control method characterized in that a refresh operation is performed after a dummy cycle has elapsed only for banks in use and banks that have already been used. (2) In a dynamic memory flexibility control device that performs refresh control on a dynamic memory whose entire storage area is constituted by a plurality of banks, a decoder means for outputting a bank selection signal that selectively selects a corresponding bank in the dynamic memory. and a bank address latch means that latches each output of the decoder means separately and holds the latched contents at a constant level until a simultaneous reset signal is input, and a bank address latch means that latches each output of the decoder means separately and holds the contents of the latches at a constant level until a reset signal is input all at once. a first logical product means for performing a logical product with the refresh request signal;
a second logical product means for logically multiplying each output of the decoder means and a row address strobe signal of the dynamic memory; and a second logical product means for logically multiplying each output of the second logical product means and each of the first logical product means. and a logical sum means for taking each logical sum with the output corresponding to the corresponding bank and supplying each output to the row address strobe terminal of each bank of the dynamic memory, so that it is not necessary to hold the memory contents of the dynamic memory. 1. A refresh control device for a dynamic memory, characterized in that input of a simultaneous reset signal to the bank address latch means is refrained from being inputted until the bank address latch means is set. (3) In a dynamic memory refresh control device that performs refresh control on a dynamic memory whose entire storage area is constituted by a plurality of banks, a decoder means for outputting a bank selection signal that selectively selects a corresponding bank in the dynamic memory. and a bank address launch means which launches each output of the decoder means separately and holds the contents of the latch at a constant level until a simultaneous reset signal is input, and each output of the bank address latch means and the input during refresh operation. a fourth logical product means for logically ANDing each output of the decoder means and a row address strobe signal of the dynamic memory; each output of the second AND means and the first
and the respective outputs of the logical product means of the logical product means corresponding to the corresponding bank, and supplying each output to the row address strobe terminal of each bank of the dynamic memory; and the bank address latch means of the bank address latch means. A waiting time setting means for setting a waiting time corresponding to the required dummy cycle time for each bank selected based on each output, and a logical sum means for calculating the logical sum of each output of the waiting time setting means and outputting the result. A refresh control device for a dynamic memory, comprising: refraining from inputting a simultaneous reset signal to the bank address latch means until it is no longer necessary to hold the storage contents of the dynamic memory. (4) A patent in which the waiting time setting means is a one-shot multivibrator circuit that is triggered by the rise or fall of each output of the bank address latch means and outputs a pulse signal with a pulse width corresponding to the required dummy cycle time. A dynamic memory refresh control device according to claim (3).