JPS60171700A - Sample hold circuit - Google Patents

Abstract

PURPOSE:To reduce noise generated in a sampling period by limiting the frequency band of a sample holding means to the prescribed range of frequency, and providing a filter for compensating a frequency characteristic to the prestage. CONSTITUTION:The output of an amplifier 1 for voltage gain is supplied to a hold capacitor 3 through a sampling switch 2 and a resistance 6, and a frequency response characteristic in correspondence to the output of an amplifier 4 for voltage gain is decided from an input of the amplifier 1 in accordance with a time constant of the resistance 6 and the capacitor 3. On the other hand, the frequency response characteristic is compensated by an prestage filter 5, becomes flat and an analog signal supplied to the capacitor 3 goes to an original frequency characteristic. As a result, when the band of a sample holding means is set below a half of the sampling frequency, the characteristic is compensated. Assuming that the band is a half of said frequency or below, the noise of the amplifier 1 and the switch 2 are reduced, and S/N of the sample hold circuit is improved.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a chimple hold circuit.

[Technical gastric juice of the invention and its problems]

Conventionally, a sample and hold circuit as shown in FIG. 1 has been known.

Increase analog human power 'tonne pressure ei1. an amplifier 1 with a voltage gain of 1; means for sampling the output of the input amplifier 1 by means of a chimple switch 2 that opens and closes during a chimpling period and a hold period; and a hold condenser 3 that holds the chimple output voltage of the amplifier 1; and an amplifier 4 with a high input impedance and a voltage gain l which amplifies the holding voltage of the hold capacitor f3 and outputs an output voltage e□.

Such a conventional chimple hold circuit C2 has a drawback that noise generated in the amplifier l and the chimple switch 2 during the chimple period is superimposed on the analog input signal and is supplied to the hold capacitor f3. This noise is approximately proportional to the bandwidth of the amplifier 1 and the sample switch 2, and is a factor that determines the 87N of the entire sample and hold circuit. However, due to the problem of the frequency characteristics of the entire chimbling hold circuit, the band fi of the signal characteristics of the sample hold circuit at the time of sampling is forced to have a relationship of at least 3 f (>7) with respect to the chimbling frequency f8. It must be made wider than the band fs of the amplifier l and the sample switch 2, and as a result, the band fs of the amplifier l and the sample switch 2
The noise caused by this is considerable.

[Purpose of the invention]

The present invention has been made in view of the above problems, and an object of the present invention is to provide a sample-and-hold circuit that reduces noise generated during a sampling period.

[Summary of the invention]

The present invention limits the frequency characteristics of the conventional chimple hold circuit during the chimbling period to one or less of the sampling frequency, and inserts (two) filter circuits in the front stage to compensate for this.

〔Effect of the invention〕

In general, in signal processing, it is extremely important to maintain signal transfer characteristics and linearity, and to have low noise.

According to the present invention, it is possible to provide a chimple hold circuit that maintains transmission characteristics and has low noise.Also, since the voltage change in the sample circuit is gradual, it is easier to maintain linearity than before.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to the drawings. Second
The figure shows an embodiment of the chimple hold circuit of the present invention. The sample-and-hold circuit of the present invention differs from conventional circuits in that the frequency characteristic of the sample-and-hold means is limited to less than the sampling frequency T, and that it includes a filter circuit 5 in the preceding stage to supplement the sampling frequency. During the sampling period, the chimple switch is on, and the analog input signal el is supplied to the amplifier l via the filter circuit. amplifier 1
The output of 1 is connected to the hold capacitor via chimple switch 2 and resistor 6. 3. In this case, the amplifier l
The frequency response characteristic from the input to the output of amplifier 4 is
It is determined by the time constant 01-, which is the product of the resistor 6 and the hold capacitor f3, and is shown in FIG. On the other hand, filter circuit 5
If the frequency response characteristic of 1111I8 is canceled out from the frequency response characteristic of FIG.

FIG. 4 shows an example of the frequency response characteristic of only the filter circuit 5, and FIG. 5 shows an example of the overall frequency characteristic during the sampling period.

According to this circuit configuration, the noise of the amplifier l and the chimple switch 2 supplied to the hold capacitor f3 is as follows.
The band is limited by the time constant C, and the noise power is significantly reduced.The analog input signal is band-limited by the time constant C, and the high frequency is emphasized by the filter circuit 5 (2). The analog signal fed to the hold capacitor f3 must have the original frequency characteristics (2). Therefore, in such a configuration (2), the chimple hold means must have a signal characteristic band below the chimpling frequency T. However, its characteristics are compensated by the filter circuit in the previous stage.As a result, the band of the chimple hold means can be lowered by C2 below the sampling frequency, so that the amplifier l and the chimple period T y'- 2 noise can be reduced, and an 87N improvement of the entire chimple hold circuit can be achieved.

An example of such a filter circuit is shown in FIG.

In FIG. 6C2, the output of an amplifier 7 with a voltage gain 1 for amplifying the analog input voltage ei'a' is connected to a resistor 10 via a resistor 9 and two parallel capacitors f9.

The output of the filter circuit is given as the voltage across the resistor 10+2.

The input/output characteristics of the filter circuit shown in FIG. 6 in the frequency domain C2 are as shown in FIG.
is raised from the angular frequency given by the reciprocal of NC', and by taking this C' and the above-mentioned c7 in particular, the above-mentioned effect can be obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional chimple hold circuit, FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 3 is a frequency characteristic diagram of the sample and hold means during the chimple period, and FIG. 4 is a diagram of a filter circuit. FIG. 5 is a frequency characteristic diagram of the chimple hold circuit of the present invention during the chimple period, and FIG. 6 is a diagram showing an example of a filter circuit. l...Amplifier, 2. Chimple switch, 3...
Hold capacitor, 4...Amplifier, 5...Filter circuit 6...Resistor, 7...Amplifier, 8...Resistor, 9...Capacitor lO...Resistor Fig. 1 2 Figure 6

Claims (1)

[Claims] The filter circuit includes a filter circuit to which an input signal G is applied, and a temple hold means that timples and holds the output of the filter circuit every predetermined sampling period, and whose frequency characteristic is less than or equal to the sampling frequency T. A sample-and-hold circuit characterized in that it has a frequency response characteristic that compensates for the frequency characteristic of a holding means, and that a substantially flat frequency characteristic is obtained as a whole.