JPS60169228A - Ad conversion circuit - Google Patents

Abstract

PURPOSE:To attain higher resolution and better vertical correlation to oscillation by providing a means for oscillating a reference signal by 1/2LSB's share and deciding forcibly and definitely a reference signal when a horizontal synchronizing signal is incoming. CONSTITUTION:An analog video signal is applied from an input terminal 2 and a reference signal from a reference voltage generating section of an AD converter 1 for 7 bits is oscillated for 1/2LSB's share by using an output of a dither signal generator 6 to change over switch circuits 8 and 9 thereby improving the resolution. Then the dither signal generator 6 is reset by a horizontal synchronizing signal from an input terminal 11, a dither signal is made to zero forcibly and decided definitely to provide vertical correlation to the oscillation. Even if the fH/2 carrier offset method is applied, the decrease effect of crosstalk disturbance from an adjacent track is not lost.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an AD conversion circuit, and in particular to an AD conversion circuit that converts video signals from analog to digital without impairing the vertical correlation (line correlation) of the video signals. Regarding conversion circuits.

BACKGROUND OF THE INVENTION It is known that an AD conversion circuit for converting a video signal from analog to digital requires a resolution of 7 or 8 bits. However, when the resolution is 7 bits, m-concentration noise becomes noticeable depending on the image pattern, so it is not sufficient from the viewpoint of image quality. On the other hand, A with 8-bit resolution
When a D conversion circuit is used, there is no problem in terms of image quality, but the circuit configuration is more complicated and expensive than a 7-bit AD conversion circuit. For example, when the AD conversion circuit has a parallel comparison type configuration, the voltage comparator that compares the input analog video signal and the reference voltage respectively has a resolution of (2"-1) when the resolution is n bits. Since it is necessary to connect them to the decoder in parallel, an AD conversion circuit with a resolution of 8 bits requires 255 comparators, which requires a resolution of 7 bits.
The number of comparators is considerably larger than the 127 in the case of a 7-bit resolution, and the IC chip area is 2 times that of a 7-bit resolution.
It requires double the amount and is expensive.

Therefore, regarding the conventional AD conversion circuit to which a video signal is supplied, the reference voltage of the comparator of the AD conversion circuit with 7-bit resolution is changed every horizontal scanning period (1H).
/2) There is a known method of obtaining a resolution substantially equivalent to 7.5 bits by alternately changing only the input analog voltage valve corresponding to "LSB".
r: ”WHAT I 5 THE IMPACT OF
GE-28, IEEE J, GE-28
,3,Aug.

1982).

Problems to be Solved by the Invention However, when recording a frequency-modulated wave signal obtained by frequency-modulating a carrier wave with a digital video signal taken out from an AD conversion circuit onto a recording medium such as a magnetic tape, it is necessary to In order to visually reduce crosstalk from the track, the carrier of the frequency modulated wave signal is shifted by a frequency equal to 1/2 of the horizontal scanning frequency f+-+ every track scanning period. 2) There is a problem in that the conventional AD conversion circuit for changing the reference voltage cannot be directly applied to a device that uses the b+carrier offset method. In other words, when reproducing a track pattern in which there is no or very small guard band between adjacent tracks, or when reproducing with a head whose width is larger than the track pitch, the horizontal synchronization signal recording position between adjacent tracks is If they are not aligned in the track width direction, the azimuth loss effect on the carrier portion of the horizontal synchronization signal, which is a relatively low frequency component of the frequency modulated wave signal, will not be sufficient, and this will be reproduced as crosstalk from adjacent tracks. This mixes into the carrier portion of the video signal, which is a relatively high frequency component of the reproduced frequency modulated wave signal of the track to be reproduced, and causes interference after FM demodulation.

Therefore, in the above case, the b+/2 carrier offset method described above records the carriers of the frequency modulated wave signals of adjacent tracks with a difference of b+/2, thereby eliminating the vertical correlation of the video signal during playback. , the crosstalk of the n-th scanning line from the adjacent track and the crosstalk of the n+i-th scanning line are made to have a phase difference of 180 degrees, respectively.As a result, since the video signal has vertical correlation, the crosstalk is caused by the visual integration effect. This is a method of canceling and visually reducing it.

As mentioned above, in order to obtain a resolution equivalent to 7.5 bits with an AD conversion circuit with a resolution of 7 bits, if the reference voltage of the comparator is changed every day, the digital video signal taken out from the AD conversion circuit As a result, the vertical correlation of the frequency modulated wave signal obtained by frequency modulating this digital video signal also collapses, and even if the above (1/2) f + carrier offset method is applied, Crosstalk cancellation is no longer performed completely, and crosstalk becomes noticeable.

Therefore, the present invention solves the above problems by changing the reference voltage while maintaining vertical correlation.
The purpose of this invention is to provide a D conversion circuit.

The invention is to set the level of the reference signal of the AD conversion circuit at a constant frequency higher than the horizontal scanning frequency and lower than the sampling pulse frequency (however, the color subcarrier frequency is lower than the sampling pulse frequency). ), vibrates by the input analog video signal level corresponding to (1/2) LSB, and uniquely and forcibly determines the level of the reference signal when the horizontal synchronization signal in the analog video signal is received. An embodiment thereof will be described below with reference to the drawings.

Embodiment FIG. 1 shows a circuit system diagram of an embodiment of the circuit of the present invention. In the figure, there are m AD conversion circuits 1 each supplied with an analog video signal from an input terminal 2 (where m is equal to 2N-1, and N is the number of pits of the output digital video signal; here, 7), a decode circuit 5 to which each output signal of the comparators 31 to 3m and a sampling pulse from the input terminal 4 are supplied, a dither signal generator 6, a power supply voltage input terminal 7, and ground. It generally consists of switch circuits 8 and 9 connected in series between them and a reference voltage generation circuit section consisting of a resistor.

The common terminal of the switch circuit 8 is connected to the terminal 7, and the common terminal is connected to the terminal 8.
a and 8b have a resistance value of 3R/2. are connected in common to the other input terminal of the comparator 31 through a resistor R, and connected to the other input terminal of the comparator 31 through a resistor R1-1 in series.
It is connected to a common connection point between both resistors R and the other input terminal of the comparator 3m. Resistance value R/2. Each resistor R is connected to terminals 9a and 9b of the switch circuit 9,
Further, the common terminal of the switch circuit 9 is grounded. Each connection point of the 1-i series-connected resistors of resistance value R is connected to the other input terminal of the corresponding one of the comparators 32 to 3m-. The voltage (2) from the input terminal 7 is resistively divided by the resistor network described above and applied to the other input terminals of the comparators 31 to 3m as reference voltages of different values.

The switching of switch circuits 8 and 9 is controlled in conjunction with a dither signal of a constant frequency from dither signal generator 6, and when switch circuit 9 is connected to terminal 9a, switch circuit 8 is connected to terminal 8a. and terminal 9b
When connected to terminal 8b, it is connected to terminal 8b. As a result, the series combined resistance value between terminal 7 and ground is the switch circuit 8
, 9, always 128R (however, N-7
゜m = 127).

On the other hand, the dither signal generator 6 receives, for example, 4 of the color subcarrier frequency rsc as shown in FIG. 2<A) from the input terminal 1o.
A sampling pulse selected to have a double repetition frequency, a video signal entering input terminal 2, and a horizontal synchronization signal and a vertical synchronization signal from input terminals 11 and 12, which are separated and extracted from the input terminal 2, are supplied respectively. . The dither signal generator 6 converts the sampling pulse from the input terminal 10 into 1/2, for example.
The frequency is divided and a pulse train as shown in FIG. 2<8) is generated and outputted as a dither signal, and is reset by a horizontal synchronizing signal as shown in FIG. 2(C) from the input terminal 11.

Therefore, when the horizontal synchronizing signal is received, the logical value of the dither signal is forced to rOJ and is uniquely determined as shown in FIGS. 2(B) and 2(C). As a result, the dither signal has vertical correlation. This dither signal is used as a switching signal in the switch circuits 8 and 9 as described above.
are supplied respectively, and the theory is! ll! When the value rOJ is present, it is connected to the terminals 8a and 9a, and when the logical value is "1", it is switched and connected to the terminals 8b and 9b.

As a result, each M supplied to the comparators 31 to 3+1
For the quasi-voltage, switch circuits 8 and 9 are connected to terminal 8a.

When connected to terminal 9a, the value is lower by V/256 than when connected to terminals 8b and 9b, and the dither signal causes the reference voltage to oscillate up and down by V/256. The voltage value corresponding to the LSB (least significant bit) of the output digital video signal corresponds to the reference voltage V/128 of the comparator 3m.Therefore, the reference voltage is set to (1/2) LSB by the above dither signal. It is caused to vibrate by an amount corresponding to the reference voltage or analog video signal level (V/256).

The analog video signals that have entered the input terminal 2 are simultaneously supplied to each of the comparators 3I to 3m, where they are compared with each of the reference voltages mentioned above, and then supplied in parallel to the decoding circuit 5. The decoding circuit 5 performs sampling using a sampling pulse from the input terminal 4 (same as the sampling pulse from the input terminal 10), converts it into a digital signal with N bits of quantization bits, and outputs it. As a result, the analog video signal from the input terminal 2 is output from the decoding circuit 5 to -number of quantization bits per pixel N pits (here, 7 bits).
is converted into a digital video signal and extracted.

As mentioned above, this digital video signal has a reference voltage (
Since the value is vibrated by 1/2>188 minutes, the value is vibrated by (1/2)188 minutes. That is, if the vertical axis of FIG. 3 shows the value of the lower 3 bits of the digital video signal, and the horizontal axis shows the input level of the analog video signal, then
When the switch circuits 8 and 9 are connected to the terminals 8a and 9a, the threshold level changes as shown by the solid line in the figure, and when it is connected to the terminals Bb and gb, the threshold level changes as shown by the broken line ■ in the figure. Since the threshold level changes as shown, the value of the digital video signal also oscillates by 11/2)188 due to the oscillation of the reference voltage. This digital video signal is recorded on a recording medium through a frequency modulator, or after being subjected to noise reduction and other digital processing, it is sequentially passed through a DA converter and a frequency modulator and recorded on a recording medium. As a result, the reproduced image obtained by demodulating the frequency modulated wave signal obtained by reproducing this recording medium can be obtained by demodulating the output signal of an AD conversion circuit with a conventional resolution (number of quantization bits) of 7 bits. The quantization noise generated in
In this embodiment, the oscillation of the reference voltage caused by the dither signal described above is dispersed within the screen, making it difficult to notice visually, and a resolution of 7.5 pits is substantially obtained by this embodiment. Furthermore, even if the fH/2 carrier offset method described above is applied during recording, the frequency carrier interleaving effect will be impaired because the dither signal has vertical correlation as described above. Therefore, crosstalk interference from @-connected tracks can be reduced.

It should be noted that due to the above-mentioned vibration, a minute signal of vertical stripes is added to the digital video signal. To cancel this, it is sufficient to invert the dither signal every one track scanning period (usually one field). For this reason, the dither signal generator 6 is configured to invert the polarity of the dither signal for each field using a vertical synchronizing signal (this may be a head switching pulse) from the input terminal 12.

Application Example Note that the dither signal is not limited to the above example, and the sampling pulse is 1/3°115.1/6.
You may divide the frequency by a natural number such as ... (however,
If the frequency is the same as rsc, the screen will be colored, so this is excluded. Also, since a reset is applied at r+, the frequency is higher than this. ). The waveform of the dither signal is shown in Figure 4 (A
) and the symmetrical square wave with a frequency of 2fsc/c shown in Fig. 2(B), but if the repetition frequency is 4fsc/3, the waveform as shown in Fig. 4(B) or (C) may be used. In the case of 4fsc15, see Figure 4 (D) or (
Various waveforms such as rlolloJ or [111000J bit pattern waveforms as shown in E) are conceivable.

Furthermore, the present invention is applicable not only to parallel comparison type AD conversion circuits, but also to
It can also be applied to AD conversion circuits such as successive approximation type that use other reference signals.

Effects As mentioned above, according to the present invention, the reference signal is (1/2)18
Since it was made to vibrate for 8 minutes, A with a resolution of N bits
Since the D conversion circuit can practically obtain a resolution of N+ (1/2) bits, and the level of the reference signal when the horizontal synchronization signal is input is uniquely and forcibly determined, the above-mentioned vibration can be avoided. It is possible to have vertical correlation, so this A
Even if the f+/2 carrier offset method is applied when frequency-modulating the output digital video signal of the D-conversion circuit or a signal obtained by further DΔ-converting it and recording it on a recording medium, the adjacent track due to the intended frequency indanileaving is This has the advantage of not impairing the effect of reducing crosstalk interference from other sources.

[Brief explanation of the drawing]

FIG. 1 is a circuit system diagram showing one embodiment of the circuit of the present invention, and FIG.
The figures are a signal waveform diagram for explaining the operation of Figure 1, Figure 3 is a diagram showing changes in threshold level in the circuit of the present invention, and Figure 4 is a diagram showing the change in threshold level in the circuit of the present invention.
The figure shows each side of the dither signal waveform. 1... AD conversion circuit, 2... Analog video signal input terminal, 31-3m... Comparator, 4.10...
Sampling pulse input terminal, 5... decoding circuit,
6... Dither signal generator, 7... Power supply voltage input terminal, 8.9... Switch circuit, 11... Horizontal synchronizing signal input terminal, 12... Vertical synchronizing signal or head switching signal input terminal . Figure 2 Figure 3 Figure 4 (C) 1 00 1 0 0 1 0 (D) 101
10101 (E) 1 11 00 11 1 Continued from page 1 [phase] Inventor Hidetoshi Amagasaki Yokohama City Shrine

Claims (1)

[Claims] (1) Analog lIl! l! In an AD conversion circuit that samples an image signal using a sampling pulse and further quantizes it to output an N-bit (N is an integer of 2 or more) digital video signal, the level of the reference signal is set higher than the horizontal scanning frequency, and , vibrates by an input analog video signal level corresponding to (1/2) LSB at a constant frequency lower than the sampling pulse frequency (excluding the color subcarrier frequency), and horizontal synchronization in the analog video signal. An AD conversion circuit comprising means for uniquely and forcibly determining the level of the reference signal when the signal is input. (2) The AD conversion circuit according to claim 1, wherein the constant frequency is a frequency that is a natural number multiple of the sampling pulse frequency.