JPS60161609A - Method of producing laminated capacitor - Google Patents
Method of producing laminated capacitorInfo
- Publication number
- JPS60161609A JPS60161609A JP1774084A JP1774084A JPS60161609A JP S60161609 A JPS60161609 A JP S60161609A JP 1774084 A JP1774084 A JP 1774084A JP 1774084 A JP1774084 A JP 1774084A JP S60161609 A JPS60161609 A JP S60161609A
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- multilayer capacitor
- capacitor
- block
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Ceramic Capacitors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
（技術分野）
本発明は誘電体シートを積層してなる積層コンデンサブ
ロックに複数組のコンデンサを形成した積層コンデンサ
の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing a multilayer capacitor in which a plurality of sets of capacitors are formed in a multilayer capacitor block formed by stacking dielectric sheets.
（従来技術）
従来、複数枚の誘電体シートを積層してなる一つの積層
コンデンサブロックに複数組のコンデンサを形成した積
層コンデンサの製造方法としては、たとえば第１図（、
）に示すように、一つの辺に沿って等間隔にコンデンサ
電極１，１．・・・、１が形成された誘電体シート２と
、第２図（ｂ）に示すように、一つの辺に沿って等間隔
にコンデンサ電極３゜３、・・・、３が形成されたいま
一つの誘電体シート４とを交互に積層するとともに、第
１図（ｃ）に示すように最上段および最下段に上記コン
デンサ電極１，１．・・・、１および３，３．・・・、
３を有しない誘電体シート５および６を積層して積層コ
ンデンサブロック７を形成し、この積層コンデンサブロ
ック７の相対向する一対の側面７ａおよび７ｂにハケ塗
り等の手法で電極材料を塗布して端子電極８，８１・・
・、８および９，９．・・・、９を形成し、この端子電
極８，８．・・・、８および９，９．・・・。(Prior Art) Conventionally, as a method for manufacturing a multilayer capacitor in which a plurality of sets of capacitors are formed in one multilayer capacitor block formed by laminating a plurality of dielectric sheets, for example, the method shown in FIG.
), capacitor electrodes 1, 1 . . . , 1 were formed on the dielectric sheet 2, and capacitor electrodes 3° 3, . . . , 3 were formed at equal intervals along one side as shown in FIG. 2(b). Another dielectric sheet 4 is alternately laminated, and the capacitor electrodes 1, 1 . ..., 1 and 3, 3. ...,
A laminated capacitor block 7 is formed by laminating the dielectric sheets 5 and 6 that do not have 3, and an electrode material is applied to a pair of opposing side surfaces 7a and 7b of the laminated capacitor block 7 by a method such as brush painting. Terminal electrodes 8, 81...
・, 8 and 9, 9. . . , 9 are formed, and these terminal electrodes 8, 8 . ..., 8 and 9,9. ....
９を上記電極１，１．・・・、１および３，３．・・・
。9 to the above electrodes 1,1. ..., 1 and 3, 3. ...
.
３に導通させるようにしたものが一般に知られている。3 is generally known.
ところで、上記のような積層コンデンサの製造方法では
、多数の端子電極８，８．・・・、８および９．９．・
・・、９は主としてハケ塗りにより塗布しなければなら
ず、端子電極８，８．・・・、８および９．９．・・・
、９の塗布に手間がか・す、量産性が悪いという問題が
あった。By the way, in the method for manufacturing a multilayer capacitor as described above, a large number of terminal electrodes 8, 8 . ..., 8 and 9.9.・
. . , 9 must be applied mainly by brushing, and the terminal electrodes 8, 8 . ..., 8 and 9.9. ...
, 9 was time-consuming and difficult to mass-produce.
（発明の目的）
本発明は上記問題を解消すべくなされたものであって、
その目的は、複数枚の誘電体シートを積層してなる積層
コンデンサブロック側面を切り欠いた後、この側面に端
子電極を形成することにより、隣り合う端子電極を切欠
ぎにより相互に分離し、積層コンデンサブロック側面に
ディンピングやローラにより電極を形成するようにした
量産性が高く信頼性の高い積層コンデンサの製造方法を
得ることである。(Object of the invention) The present invention has been made to solve the above problems, and includes:
The purpose of this is to cut out the side surface of a multilayer capacitor block made by laminating multiple dielectric sheets, and then form terminal electrodes on this side surface, thereby separating adjacent terminal electrodes from each other by the notch, and stacking An object of the present invention is to obtain a method for manufacturing a multilayer capacitor that is highly mass-producible and highly reliable, in which electrodes are formed on the side surface of a capacitor block by dipping or rollers.
（発明の構成）
このため、本発明は、大略四角形状を有する複数枚の誘
電体シートがブロック状に積層され、上記各誘電体シー
トの辺に沿ってはダ等間隔に形成されたコンデンサ電極
の端部が交互に相対向する一対の側面に引き出されてな
る積層コンデンサブロックを用意し、上記コンデンサ電
極の端部の間の積層コンデンサブロック側面を切り欠い
た後、この側面に上記コンデンサ電極の端部に夫々導通
する端子電極を形成するようにしたことを特徴としてい
る。(Structure of the Invention) Therefore, the present invention provides a structure in which a plurality of dielectric sheets each having a substantially rectangular shape are stacked in a block shape, and capacitor electrodes are formed at equal intervals along the sides of each dielectric sheet. A multilayer capacitor block is prepared in which the ends of the capacitor electrodes are drawn out to a pair of opposing side surfaces, and after cutting out the side surface of the multilayer capacitor block between the ends of the capacitor electrodes, the capacitor electrodes are placed on this side surface. It is characterized in that terminal electrodes that are electrically connected are formed at each end.
（実施例） 以下、添付図面を参照して本発明の詳細な説明する。(Example) Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
本発明に係る積層コンデンサの製造方法の一実施例を第
２図（ａ）から第２図（ｆ）に示す。An embodiment of the method for manufacturing a multilayer capacitor according to the present invention is shown in FIGS. 2(a) to 2(f).
先ず、第２図（ａ）に示すように、一つの辺に沿って等
間隔にコンデンサ電極ｉｉ、１ｉ、・・・、１１が形成
された長方形状の誘電体シート１２と、第２図（ｂ）に
示すように、一つの辺に沿って等間隔にコンデンサ電極
１３’、１３．・・・、１３が形成されたいま一つの誘
電体シート１４とを複数枚交互に積層するとともに、第
２図（ｃ）に示すように、最上段および最下段に上記コ
ンデンサ電極１１゜１１、・・・、１１および１３，１
３．・・・、１３を有しない誘電体シート１５および１
６を積層して積層コンデンサブロック１７を用意する。First, as shown in FIG. 2(a), a rectangular dielectric sheet 12 on which capacitor electrodes ii, 1i, . . . , 11 are formed at equal intervals along one side, and As shown in b), capacitor electrodes 13', 13. ..., 13 and another dielectric sheet 14 are alternately laminated, and as shown in FIG. 2(c), the capacitor electrodes 11, 11, ..., 11 and 13,1
3. ..., dielectric sheets 15 and 1 without 13
6 is stacked to prepare a multilayer capacitor block 17.
この積層コンデンサブロック１７の対向する一対の側面
を、第２図（ｄ）に示すように、誘電体シート１２のコ
ンデンサ電極１１，１１．・・・、１１の間および誘電
体シート１４のコンデンサ電極１３．１３．・・・、１
３の間で切り欠いて夫々切欠外１８，１８．・・・、１
８および１９，１９．・・・。As shown in FIG. 2(d), the capacitor electrodes 11, 11 . ..., 11 and the capacitor electrodes 13.13. of the dielectric sheet 14. ..., 1
3 and outside the notch 18, 18. ..., 1
8 and 19, 19. ....
１９を形成する。 その後、上記のような切欠き１８．
１８．・・・、１８および１９．１９．・・・。form 19. Then cut out 18. as above.
18. ..., 18 and 19.19. ....
１９を形成した積層コンデンサブロック１７の上記側面
１７ａおよび１７ｂを、たとえば第２図（ｅ）に示すよ
うに、銀（Ａｇ）ペースト等の電極塗料２１中に、切欠
き１８，１８．・・・、１８および１９゜１９、・・・
、１９の途中まで浸漬して引き上げ、上記側面１７ａお
よび１７１）に付着した電極塗料２１を焼き付けて、第
２図（ｆ）に示すように、上記切欠き１８，１８．・・
・、１８および１９，１９．・・・。As shown in FIG. 2(e), cutouts 18, 18 . ..., 18 and 19°19, ...
, 19), and then the electrode paint 21 adhering to the side surfaces 17a and 171) is baked off to form the notches 18, 18, 19, as shown in FIG. 2(f).・・・
・, 18 and 19, 19. ....
１９により相互に分離されるとともに、第２図（ａ）に
示す誘電体シート１２のコンデンサ電極１１゜１１、・
・・、１１および第２図（う）に示す誘電体シ ′−ト
１４のコンデンサ電極１３．１３．・・・、１３に夫々
導通する端子電極２２，２２．・・・、２２および２３
，２３．・・・、２３を形成している。The capacitor electrodes 11° 11, . . . of the dielectric sheet 12 shown in FIG.
. . , 11 and the capacitor electrode 13 of the dielectric sheet 14 shown in FIG. 2(c). ..., 13, terminal electrodes 22, 22 . ..., 22 and 23
, 23. ..., forming 23.
上記のようにすれば、電極塗料２１に積層フンデンサブ
ロック１７の側面１７ａおよび１．．７ ｂを 。By doing the above, the electrode paint 21 is coated on the side surfaces 17a and 1. ．． 7 b.
浸漬して引き上げるいわゆるディッピングにより電極塗
料２１の塗布を一挙に行うことができ量産性が大巾に向
上する。The electrode coating material 21 can be applied all at once by dipping and pulling up, which greatly improves mass productivity.
なお、端子電極２２，２２．・・・、２２および２３゜
２３、・・・、２３の形成は、上記のようなディッピン
グに代えて、具体的には図示しないが、電極塗料２１を
周面に付着させたローラに積層コンデンサブロック１７
の側面１７ａ＋１７ｂ上を当接させて電極塗料２１を印
刷するローラ法や、積層コンデンサブロック１７全体を
メッキし、エツチングにより不要なメッキ膜を除去する
エツチング法等の量産性１こ優れた手法により端子電極
２２，２２゜・・・、２２および２３，２３．・・・、
２３に形成することができる。Note that the terminal electrodes 22, 22. . . , 22 and 23° 23, . Block 17
The terminals are formed using methods that are excellent in mass production, such as the roller method in which the electrode paint 21 is printed by contacting the side surfaces 17a+17b of the terminal, and the etching method in which the entire multilayer capacitor block 17 is plated and unnecessary plating film is removed by etching. Electrodes 22, 22°..., 22 and 23, 23. ...,
23.
また本発明において、積層コンデンサブロックに形成さ
れる切り欠とは、焼成前、焼成後のいずれにおいて形成
してもよいが、焼成前に打ち抜き等によって形成するこ
とが、加工上有用である。Further, in the present invention, the notches formed in the multilayer capacitor block may be formed either before or after firing, but it is useful for processing to form them by punching or the like before firing.
さらにあらかじめ各誘電体シートに切り欠きを形成して
おくことも可能である。Furthermore, it is also possible to form cutouts in each dielectric sheet in advance.
（発明の効果）
以上、詳述したことからも明らかなように、本発明は、
積層コンデンサブロック側面に切欠ぎを形成した後、こ
の側面にこれら切欠きにより相互に分離される端子電極
を形成するようにしたから、端子電極の形成にディッピ
ング等の量産性の良好な手法を使用することかでと、積
層コンデンサブロックに複数組のコンデンサが形成され
た積層コンデンサの量産が容易になる。また、隣り合う
端子電極が切欠ぎで相互に分離され、これら端子電極が
短絡することもなく、信頼性の高い積層コンデンサを得
ることができる。(Effects of the Invention) As is clear from the detailed description above, the present invention has the following effects:
After notches are formed on the side surface of the multilayer capacitor block, terminal electrodes that are separated from each other by these notches are formed on this side surface, so methods that are suitable for mass production such as dipping are used to form the terminal electrodes. This will facilitate the mass production of multilayer capacitors in which multiple sets of capacitors are formed in a multilayer capacitor block. Further, since adjacent terminal electrodes are separated from each other by the notch, there is no short circuit between these terminal electrodes, and a highly reliable multilayer capacitor can be obtained.
第１図（ａ）、第１図（ｂ）および第１図（ｃ）は夫々
従来の積層コンデンサの製造方法の説明図、第２図（ａ
）、第２図（ｂ）、第２図（Ｃ）、第２図（ｄ）、第２
図（ｅ）および第２図（ｆ）は夫々本発明に係る積層コ
ンデンサの製造方法の説明図である。
１１・・・コンデンサ電極、１２・・・誘電体シート、
１３・・・コンデンサ電極、１４・・・誘電体シート、
１７・・・積層コンデンサブロック、
１７ａ、 １ ’？ｂ−−側面、 １８．１９・・・切
欠き、２１・・・電極塗料、２２．２３・・・端子電極
。FIG. 1(a), FIG. 1(b) and FIG. 1(c) are explanatory diagrams of a conventional method of manufacturing a multilayer capacitor, and FIG. 2(a)
), Figure 2 (b), Figure 2 (C), Figure 2 (d), Figure 2
FIG. 2(e) and FIG. 2(f) are explanatory diagrams of a method for manufacturing a multilayer capacitor according to the present invention, respectively. 11... Capacitor electrode, 12... Dielectric sheet,
13... Capacitor electrode, 14... Dielectric sheet,
17... Multilayer capacitor block, 17a, 1'? b--Side surface, 18.19... Notch, 21... Electrode paint, 22.23... Terminal electrode.
Claims (3)
ロック状に積層され、上記各誘電体シートの辺に沿って
はず等間隔に形成されたコンデンサ電極の端部が交互に
相対向する一対の側面に引き出されてなる積層コンデン
サブロックを用意し、上記電極の端部の間の積層コンデ
ンサブロック側面を切り欠いた後、この側面に上記コン
デンサ電極の端部に夫々導通する端子電極を形成するよ
うにしたことを特徴とする積層コンデンサの製造方法。(1) A plurality of dielectric sheets each having a roughly rectangular shape are stacked in a block shape, and the end portions of capacitor electrodes are formed at equal intervals along the sides of each dielectric sheet, and the end portions of the capacitor electrodes are alternately opposed to each other. Prepare a multilayer capacitor block drawn out from the side surface of the multilayer capacitor block, cut out the side surface of the multilayer capacitor block between the ends of the electrodes, and then form terminal electrodes on this side surface that are electrically connected to the ends of the capacitor electrodes. A method for manufacturing a multilayer capacitor, characterized in that:
を、電極塗料中への浸漬によって行われることを特徴と
する特許請求の範囲第１項記載の積層コンデンサの製造
方法。(2) The method for manufacturing a multilayer capacitor according to claim 1, wherein the terminal electrodes are formed by dipping the multilayer capacitor block into an electrode paint.
外面に電極塗料が付与されたローラに当接されること１
こよって行われることを特徴とする特許請求の範囲第１
項記載の積層コンデンサの製造方法。(3) The formation of the terminal electrodes is carried out by abutting the multilayer capacitor block against a roller whose outer surface is coated with electrode paint.
Accordingly, the first claim is characterized in that
2. Method for manufacturing a multilayer capacitor as described in Section 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1774084A JPS60161609A (en) | 1984-02-01 | 1984-02-01 | Method of producing laminated capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1774084A JPS60161609A (en) | 1984-02-01 | 1984-02-01 | Method of producing laminated capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60161609A true JPS60161609A (en) | 1985-08-23 |
Family
ID=11952140
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1774084A Pending JPS60161609A (en) | 1984-02-01 | 1984-02-01 | Method of producing laminated capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60161609A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6272198A (en) * | 1985-09-25 | 1987-04-02 | 東光株式会社 | Manufacturing laminated circuit substrate |
| JPH03280412A (en) * | 1990-03-29 | 1991-12-11 | Mitsubishi Materials Corp | Capacitor network structure and manufacture thereof |
| US10573466B2 (en) | 2017-01-04 | 2020-02-25 | Murata Manufacturing Co., Ltd. | Method of manufacturing multilayer ceramic capacitor |
-
1984
- 1984-02-01 JP JP1774084A patent/JPS60161609A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6272198A (en) * | 1985-09-25 | 1987-04-02 | 東光株式会社 | Manufacturing laminated circuit substrate |
| JPH03280412A (en) * | 1990-03-29 | 1991-12-11 | Mitsubishi Materials Corp | Capacitor network structure and manufacture thereof |
| US10573466B2 (en) | 2017-01-04 | 2020-02-25 | Murata Manufacturing Co., Ltd. | Method of manufacturing multilayer ceramic capacitor |
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