JPS6016119Y2 - voltage selection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a voltage selection circuit that selects and extracts voltages of different levels.

In recent years, for example, liquid crystal display elements have begun to be used in the display parts of electronic desk calculators, electronic watches, etc., but when driving multi-digit liquid crystal display elements alternately and dynamically, it is necessary to use voltages at multiple levels, for example, four-value levels. It is necessary to select the amount according to the display data and supply it between the two electrodes sandwiching the liquid crystal display element.

In addition, in other electronic printing devices such as ink jet printing devices, it is necessary to perform D-A conversion from a character signal generation circuit and sequentially output voltage signals of multiple levels to the deflection electrodes according to the printed characters. .

The conventional voltage selection circuit that selects and extracts voltages of different levels as described above is constructed as shown in FIG.

Figure 1 shows V. This shows a circuit configuration when eight voltages from V7 to V7 are selected.

In FIG. 1, 1 is a decoder, for example, an inverter 2a
2c and NAND circuits 3a to 3h, each input terminal is given a voltage selection control code signal of "N?A1.A2J".

The decoder 1 decodes the applied code signal and outputs a signal from any one of the NAND circuits 3a to 3h.

Of the decoded outputs, the outputs of the NAND circuits 3a to 3d are directly sent to the P-channel Mω type transistors 4a to 4d, and the outputs of the NAND circuits 3e to 3h are sent to the inverter 5a.
N-channel MO3 type transistor 4e via ~5d
Sent to ~4h.

The source electrodes of the transistors 4a to 4h are supplied with voltages (2) of different levels.

~V7 is supplied, and the drain electrodes are collectively connected to the output terminal 6.
connected to.

In the above configuration, the code signal "AOt A1 t
When a signal is given, the decoder 1 outputs a signal from one of the NAND circuits 3a to 3h according to the input code, and turns on one of the corresponding transistors 4a to 4h.

When one of transistors 4a to 4h is turned on, the voltage applied to its source electrode appears at output terminal 6.

In this way, voltages V0 to V7 having different levels are selected by the code signals ra, .

However, the conventional voltage selection circuit configured as described above requires a decoder and a gate circuit operated by the decoder output, making the configuration complicated.
The number of circuit elements also increases.

In addition, only the gate circuit is C-MOS (complementary symmetric MO3
) transistor), and other circuits include C-MO
Since it does not use S, it has the disadvantage of high power consumption.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a voltage selection circuit that can simplify the circuit configuration, reduce the number of circuit elements, and reduce power consumption.

Embodiments of the present invention will be described below with reference to the drawings.

Figure 2 shows four types of voltage ■ with different voltage levels. This shows an example in which .about.V3 is obtained.

In FIG. 2, reference numeral 11 denotes a first gate circuit, in which one end of a P-channel transistor group consisting of, for example, P-channel MOS transistors lla and 11b and an N-channel transistor group consisting of N-channel MO3 type transistors llc and lld are connected in series. (:, -MO3 circuit structure is complete.

Further, 12 is a second gate circuit, for example, a P channel M
One end of a P-channel transistor group consisting of O3 type transistors 12a and 12b and an N-channel transistor group consisting of N-channel MO3 type transistor 2C912d are connected in series to form a C-MO3 circuit structure.

A selected voltage V is applied to the other ends of the P-channel transistor group and the N-channel transistor group of the first gate circuit 11, that is, the source electrodes of the transistors lla and lld, respectively.

, 3 are supplied, and the selected voltages V, , V2 are supplied to the other ends of the channel transistor group and the N-channel transistor group of the second gate circuit 12, that is, the source electrodes of the transistors 12a and 12d, respectively.

Further, 21a and 21b are signal input terminals to which a control signal A□ is supplied, and a control signal A□ is applied to the input terminal 21a.
.

is applied to the gate electrodes of transistors llb and lie of the first gate circuit 11, and is applied via the inverter 22 to the gate electrodes of transistors 12b and 12C of the second gate circuit 12.

On the other hand, the control signal A1 applied to the input terminal 21b is applied to the transistor 11a of the first and second gate circuits 11.12.
, 11d, 12a, and 12d.

The connection points between the P-channel MO3 type transistors 11b and 12b and the N-channel MO3 type transistor 11C912C of the first and second gate circuits 11 and 12 are collectively connected to the output terminal 23.

Note that the control signals Ao and At are positive logic “0” signals (Lo
The potential level is set so that the P-channel transistor is turned on when the signal is a positive logic 1'' signal (high level), and the N-channel transistor is turned on when the signal is a positive logic 1'' signal (high level).

In the above configuration, the control signal A.

, A1 are both 44099, the first gate circuit 11
Both P-channel MO3 type transistors 11a and 11b are turned on for the voltage IEVo, and the other voltages V1 to V
A pair of transistors 11Ct 11 consisting of a group of P and N channel transistors respectively provided for Ct 11
dw 12 at 12 b and 12c, 12d
At least one of them is turned off.

Therefore, the voltage V.

are P-channel MO3 type transistor group 11a, llb
appears at the output terminal 23 via.

Also, the control signal A.

is °l" and A1 is "O", the second gate circuit 12
The P-channel MO3 type transistors 12a and 12b are turned on for the voltage V1 of V1, and the other voltages [EEV.

, V2. Transistors lla, l forming a pair of P and N channel transistor groups respectively provided for V3
At least one of lb, 11c, lld and 12c, 12d is turned off, and voltage v1 appears at output terminal 23.

Control signal A is generated in the same manner. When is “0” and A1 is 1°, voltage V2 is output, and both Ao and A□ are “1”.
In the case of power, voltage V3 is output.

Table 1 below shows the control signals Ao-At and selected voltages V in the circuit of FIG.

It is a table showing the relationship with ~V3.

Figure 3 shows eight types of voltage ■ with different voltage levels.

~ ■ 7 is shown, and includes first to fourth gate circuits 11 to 14, and each gate circuit 11 to 14
are each three P-channel MOS type transistors 3
1a-31c, 32a-32c, 33a-33c, 34
A group of four P-channel transistors consisting of a to 34c and three N-channel MO3 type transistors 31d to
31f, 32d~32f, 33d~33f, 34d~3
One end of each group of four N-channel transistors starting from 4f is connected in series to form a C-MO3 type circuit structure.

The number of P-channel or N-channel MO3 type transistors in each of the gate circuits 11 to 14 is set corresponding to the number of bits of the control signal, and when the number of voltage selections is N, the number n is 2n=H. Set to relationship.

Therefore, when selecting eight types of voltages, n=3.

Thus, the selected voltages Vo to V7 are supplied to the other ends of the group of P-channel transistors and the group of N-channel transistors of each gate circuit 11 to 14, respectively.

The connection points between the group of P-channel transistors and the group of N-channel transistors of each gate circuit 11 to 14 are collectively connected to the output terminal 23.

Further, in each gate circuit 11 to 14, the gates of a P channel transistor and an N channel transistor located at symmetrical positions with respect to the connection point to the output terminal 23 are connected, and furthermore, the connection point is connected to the input/output terminals 21a to 21, respectively.
c directly or through the inverter 22a as shown in FIG.
, 22b.

In the above configuration, when the control signals AO9AI-A2 are all 0°, all the transistors 31a to 31c are turned on for the voltage Vo of the first gate circuit 11, and three transistors are turned on for each of the other voltages V□ to v7. At least one of the transistors provided in each case is turned off.

As a result, the output terminal 23 has a voltage ■.

appears via transistors 31a to 31c.

Also, the control signal A. is “1°゛”, A1.A2 is “°O”
In the case of °, the transistors 33a to 33e provided for the voltage V1 are turned on, and the other voltages V are turned on.

, 2) At least one transistor of each transistor group provided for V2 to V7 is turned off.

As a result, the voltage V1 is applied to the output terminal 23 of the transistor 3.
2a to 32c.

Control signal A is generated in the same manner.

, A□, and A2, voltages V2 to V7 are selected.

The following Table 2 shows the control signals AO-A4 in the circuit of FIG. A
2 and the selected voltage V.

It is a table showing the relationship with ~V7.

In the above embodiment, each gate circuit is provided with a P-channel transistor group and an N-channel transistor group in correspondence, but it is also possible to exclude the transistor group of one channel in any gate circuit. Any number of voltages can be selected without being limited to.

Furthermore, the selected voltages shown in the above embodiments include those at the ground level.

Furthermore, in the above embodiment, the number of transistors constituting the P-channel and N-channel transistor groups is the same for both channels, but it goes without saying that the number does not necessarily have to be the same when the selected voltage is not this number. .

As described above, according to the present invention, a voltage selection circuit capable of selecting a plurality of voltages can be configured using only a gate circuit, so that the configuration can be simplified.

Furthermore, since each gate circuit can have a C-MO3 type circuit configuration, power consumption can be significantly reduced.

Payment・−

[Brief explanation of drawings]

FIG. 1 shows the configuration of a conventional voltage selection circuit, FIG. 2 shows the configuration of one embodiment of the present invention, and FIG. 3 shows the configuration of another embodiment of the present invention. 2... Decoder, 11-14... Gate circuit, 21a-21c... Input terminal, 23.
...Output terminal.

Claims (1)

[Scope of utility model registration request] A plurality of P-channel transistor groups in which a plurality of P-channel MO3 type transistors are connected in series and have an open source electrode and an open drain electrode at both ends;
A plurality of N-channel transistor groups in which the same number of N-channel MO3 type transistors as channel MOs type transistors are connected in series, each having an open drain electrode and an open source electrode at both ends, an open drain electrode of the P-channel transistor group and the above N-channel transistor. A plurality of complementary MO3) transistor groups, in which the open drain electrodes of the transistor groups are directly connected, and the gate electrodes of each transistor are connected in a complementary manner so as to form a pair of P channel and N channel; Type MO
A voltage output terminal formed by commonly connecting the connection points of both the open drain electrodes of the P channel transistor group and the N channel transistor group of the S transistor group, and the open drain electrodes of the P channel transistor group and the N channel transistor group, respectively. A selected voltage supply terminal that supplies different voltages, a gate control terminal that supplies a control signal to the complementary connected gate electrodes, a set of gate control terminals in one complementary MOS transistor group, and a set of gate control terminals in one complementary MOS transistor group and another A voltage selection circuit comprising a logic circuit that provides different control signals to sets of gate control terminals within a group of complementary MOS transistors.